JPS5843585A - Superconductive wiring - Google Patents

Superconductive wiring

Info

Publication number
JPS5843585A
JPS5843585A JP56140979A JP14097981A JPS5843585A JP S5843585 A JPS5843585 A JP S5843585A JP 56140979 A JP56140979 A JP 56140979A JP 14097981 A JP14097981 A JP 14097981A JP S5843585 A JPS5843585 A JP S5843585A
Authority
JP
Japan
Prior art keywords
wiring
superconductive
ground plane
magnetic shield
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56140979A
Other languages
Japanese (ja)
Inventor
Junshi Asano
浅野 純志
Kunio Yamashita
山下 邦男
Yuji Hatano
雄治 波多野
Yutaka Harada
豊 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56140979A priority Critical patent/JPS5843585A/en
Publication of JPS5843585A publication Critical patent/JPS5843585A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To contrive the reduction of wiring inductances, by providing magnetic shield layers between a superconductive wiring and a superconductive ground plane. CONSTITUTION:The reduction of inductance L is realized by providing superconductive magnetic shields between a supercondutive wiring 5 and a ground plane 1. In a Josephson element, etc. having a multilayer wiring manufactured utilizing a fine pattern working technique, since a thin film 3' for other layer wiring in the same element can be utilized as a magnetic shield layer of the wiring 5 to be noticed, it has an advantage also in a processing meaning. Besides, fine adjustment for inductance values is allowed by providing a magnetic shield by this invention on a part of the wiring.

Description

【発明の詳細な説明】 本発明は、超電導配線に係わ8、特(配−のインダクタ
ンスの低減に関する。  − ジョセフソン効果を利用する論理素子、メモリ素子の研
究が近年盛んである。微細バタン技術を応用して作製す
るこれ等の素子における配線は、超電導グランドプレン
上に設けられるのが通常である。この場合配線とグラン
ドグレンの距離が配線インダクタンスを定める重要パラ
メータとなる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to superconducting wiring, and particularly to reducing the inductance of wiring. - Research on logic elements and memory elements that utilize the Josephson effect has been active in recent years. The wiring in these devices manufactured by applying technology is usually provided on a superconducting ground plane.In this case, the distance between the wiring and the ground plane is an important parameter that determines the wiring inductance.

多層配線の上部層では、距離が大きくなり配線インダク
タンスが大きぐなりすぎる欠点があった。
In the upper layer of multilayer wiring, the distance becomes large and the wiring inductance becomes too large.

本発明は、上記インダクタンスの低減化を目的とする。The present invention aims to reduce the above-mentioned inductance.

第1図は従来配線の典型的断面図である。グランドプレ
ン1上に、超゛電導配線3.5がある。2゜4は絶縁膜
である。問題となるのは配線5である。
FIG. 1 is a typical cross-sectional view of conventional wiring. On the ground plane 1 there is a superconducting wiring 3.5. 2.4 is an insulating film. The problem is the wiring 5.

この配線の単位長当りのインダクタンスは。The inductance per unit length of this wiring is.

L=ζξd 、d=む+t4+λL十λ2μ・ ;真空
透磁率、W、;配線5の線幅t6.;絶縁膜厚、λ)、
λ:  ;t、s層のロン′  ゛         
  トン長となる。Lがdg比例することは、配線5を
流れる電流の作る磁界の拡がりの程度がLに比例するこ
とを意味する。したがって磁界の拡がりを抑えることが
Lの低減化につながる。本発明においては、配線5とグ
ランドプレ4ン1の間に超電導体磁気シールドを設けL
の低減化を実現した。微細バタン加工技術を利用して作
製する、多層配線を用薄膜を利用できるため1本発明の
実現はプロセス的にも容品である。
L=ζξd, d=M+t4+λL+λ2μ・ ; Vacuum permeability, W, ; Line width of wiring 5 t6. ; Insulating film thickness, λ),
λ: ;t, s layer Ron' ゛
Becomes ton length. The fact that L is proportional to dg means that the degree of spread of the magnetic field created by the current flowing through the wiring 5 is proportional to L. Therefore, suppressing the spread of the magnetic field leads to a reduction in L. In the present invention, a superconducting magnetic shield is provided between the wiring 5 and the ground plane 1.
achieved a reduction in Since a thin film can be used for multilayer wiring, which is produced using a fine batten processing technique, the present invention can be realized easily in terms of process.

第2図が実施例の断面図である。グランドプレンlは4
G(1mのNbMであり、そのロンドン畏はλ@g5n
mである。2/、4/はsto絶縁膜でそれぞれの膜厚
はi 、/ += lQQQnm 、 t 、’ :=
soonmである。5.3′は同材料pb−In−Au
で作製した。膜厚は、それぞれls: 80Onms’
s’=200nmである。線幅はs W@ =10t”
 eW1’=100#mである。ロンドン畏れ=λ、−
140 nmであった。ストリップライン3′は。
FIG. 2 is a sectional view of the embodiment. Grand plane l is 4
G (1m NbM, its London size is λ@g5n
It is m. 2/ and 4/ are sto insulating films whose thicknesses are i, / += lQQQnm, t,' :=
It's soon. 5.3' is the same material pb-In-Au
It was made with The film thickness is ls: 80 Onms'
s'=200 nm. The line width is s W @ = 10t”
eW1'=100#m. Fear of London = λ, -
It was 140 nm. Strip line 3' is.

第1図の薄膜層3に相当する。実施例における単位長当
りのインダクタンスは、およそ。
This corresponds to the thin film layer 3 in FIG. The inductance per unit length in the example is approximately.

である。この値はストリツツライ−ンがない場合の約4
596である。    、□、1□釆は大きい。また、
素子配線におけるインダクタンス値の調整などの場合に
関しても本発明は簡便なる手段を提供するものである。
It is. This value is approximately 4 without the stripe line.
It is 596. , □, 1□ buttons are large. Also,
The present invention also provides a simple means for adjusting the inductance value in element wiring.

同、配線の一部に本発明の磁気シールド管段はインダク
タンスの値の微調を行うことも可能である。
Similarly, it is also possible to finely adjust the inductance value of the magnetically shielded tube stage of the present invention in a part of the wiring.

【図面の簡単な説明】 第1図は従来配線の断面図であり、第2図は本発明実施
例を示すものである。 1・・・グランドプレン、2.2’、4.4’・・・絶
縁薄膜、3・・・中間配線、5・・・本発明の対象とな
る配線、yfJ+   図 ? ¥3 2  回 ・
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of conventional wiring, and FIG. 2 shows an embodiment of the present invention. 1... Ground plane, 2.2', 4.4'... Insulating thin film, 3... Intermediate wiring, 5... Wiring targeted by the present invention, yfJ+ Figure? ¥3 2 times ・

Claims (1)

【特許請求の範囲】[Claims] 超電導グランドプレ4ン上に絶縁膜を介して設けられた
超電導配線において、この超電導配線と上記超電導グラ
ンドグレン・層間に磁気シールド層を有することを特徴
とする超電導配線。
A superconducting interconnect provided on a superconducting ground plane via an insulating film, the superconducting interconnect having a magnetic shield layer between the superconducting interconnect and the superconducting ground plane layer.
JP56140979A 1981-09-09 1981-09-09 Superconductive wiring Pending JPS5843585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56140979A JPS5843585A (en) 1981-09-09 1981-09-09 Superconductive wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56140979A JPS5843585A (en) 1981-09-09 1981-09-09 Superconductive wiring

Publications (1)

Publication Number Publication Date
JPS5843585A true JPS5843585A (en) 1983-03-14

Family

ID=15281297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56140979A Pending JPS5843585A (en) 1981-09-09 1981-09-09 Superconductive wiring

Country Status (1)

Country Link
JP (1) JPS5843585A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61244078A (en) * 1985-04-22 1986-10-30 Agency Of Ind Science & Technol Manufacture of superconducting lines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61244078A (en) * 1985-04-22 1986-10-30 Agency Of Ind Science & Technol Manufacture of superconducting lines

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