JPS62115881A - Magnetic field coupling type josephson integrated circuit - Google Patents

Magnetic field coupling type josephson integrated circuit

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Publication number
JPS62115881A
JPS62115881A JP60255089A JP25508985A JPS62115881A JP S62115881 A JPS62115881 A JP S62115881A JP 60255089 A JP60255089 A JP 60255089A JP 25508985 A JP25508985 A JP 25508985A JP S62115881 A JPS62115881 A JP S62115881A
Authority
JP
Japan
Prior art keywords
magnetic field
field coupling
same
coupling lines
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60255089A
Other languages
Japanese (ja)
Other versions
JPH0334868B2 (en
Inventor
Hideo Suzuki
秀雄 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP60255089A priority Critical patent/JPS62115881A/en
Publication of JPS62115881A publication Critical patent/JPS62115881A/en
Publication of JPH0334868B2 publication Critical patent/JPH0334868B2/ja
Granted legal-status Critical Current

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  • Logic Circuits (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To increase the operating margin of a circuit with less variation in magnetic field coupling degree by disposing magnetic field coupling lines of logic elements at the same position for Josephson junction when arranging the different number of magnetic field coupling lines on a Josephson junction of the same size to form different logic elements. CONSTITUTION:In the disposition of magnetic field coupling lines of 2/3 majority gates and 2-input AND gate, lower electrodes 11, 21 are formed of superconducting substance such as lead or niob, and upper electrodes 12, 22 are formed of the same substance. The 2/3 majority gates are the same as the conventional one, but the disposition of the magnetic field coupling line of the AND gate is the same as three of four magnetic field coupling lines of the 2/3 majority gate. With this disposition, the dispositions of the magnetic field coupling line of two types of gate become the same, and the disposition of the magnetic field lines at the center of the upper electrodes having good magnetic field sensitivity can be avoided to reduce the variation in the magnetic field coupling degree. The operating margin of the circuit can be also increased.

Description

【発明の詳細な説明】 〔概要〕 ジョセフソン接合の寸法が同じで、磁界結合線の数が異
なる2種類以上の磁界結合型ジョセフソンゲート素子に
おける、磁界結合線の配置の相違による磁界結合度のば
らつきを小さくするために、磁界結合線の本数の異なる
ゲート素子の磁界結合線の配置を同一にした構成の磁界
結合型ジョセフソン集積回路を提起する。
[Detailed Description of the Invention] [Summary] Magnetic field coupling degree due to difference in arrangement of magnetic field coupling lines in two or more types of magnetically coupled Josephson gate elements having the same Josephson junction dimensions and different numbers of magnetic field coupling lines. In order to reduce variations in the number of magnetic field coupling lines, a magnetically coupled Josephson integrated circuit is proposed in which gate elements having different numbers of magnetic field coupling lines have the same arrangement of magnetic field coupling lines.

〔産業上の利用分野〕[Industrial application field]

本発明はジョセフソン接合寸法が同一で、磁界結合線の
数が異なる2種類以上の素子よりなる磁界結合型ジョセ
フソン集積回路に関する。
The present invention relates to a magnetically coupled Josephson integrated circuit comprising two or more types of elements having the same Josephson junction dimensions and different numbers of magnetic coupling lines.

従来、多数の磁界結合線を持ったジョセフソン論理素子
で論理積や、多数決グーI−を同一回路で作製する際、
磁界結合線の配置は特に考慮されていないため、磁界結
合線の配置の相違による磁界結合度のばらつきが大きく
、その対策が望まれている。
Conventionally, when creating logical product or majority decision I- in the same circuit using a Josephson logic element with a large number of magnetic field coupling lines,
Since no particular consideration is given to the arrangement of the magnetic field coupling lines, the degree of magnetic field coupling varies greatly due to differences in the arrangement of the magnetic field coupling lines, and countermeasures are desired.

〔従来の技術〕[Conventional technology]

第2図(1)、(2)はそれぞれ従来例による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の配置を
説明する平面図である。
FIGS. 2(1) and 2(2) are plan views illustrating the arrangement of magnetic field coupling lines of a conventional 2/3 majority gate and a two-input AND gate, respectively.

図において、11.21は鉛、あるいはニオブ等の超伝
導物質よりなる下部電極、12.22は同じ超伝導物質
よりなる上部電極、13.23はジョセフソン接合領域
、14.15.16.17、および24.25.26は
磁界結合線である。
In the figure, 11.21 is a lower electrode made of a superconducting material such as lead or niobium, 12.22 is an upper electrode made of the same superconducting material, 13.23 is a Josephson junction region, and 14.15.16.17 , and 24.25.26 are magnetic field coupling lines.

磁界結合線は上部電極13.23の中央に集中させて2
/3多数決ゲートは4本、2入力論理積ゲートは3本設
けられている。
The magnetic field coupling line is concentrated at the center of the upper electrode 13.23.
Four /3 majority gates and three 2-input AND gates are provided.

両方のゲートの磁界結合線の1本は磁界のオフセットを
あたえるだめのものである。
One of the magnetic field coupling lines for both gates is for providing a magnetic field offset.

磁界のオフセットはこの磁界結合線に直流を流して、適
当な値に磁界のバイアスをあたえることにより行う。
Offset of the magnetic field is performed by passing a direct current through this magnetic field coupling line and biasing the magnetic field to an appropriate value.

この例の磁界結合線の配置では、2/3多数決ゲートと
2入力論理積ゲートの磁界結合度が異なり、さらに中央
に磁界結合線を設けた論理積ゲートでは中央の磁界結合
線の磁界結合度が、他の2本より大きくなり、同一ゲー
トの磁界結合線間での磁界結合度のばらつきが大きくな
るという欠点があなり、本来、第2図+1)と(2)の
回路は同一信号レベルが入力されるため、各回路は同一
レベルで応答する特性とはならないで、動作マージンが
小さくなる。
In the arrangement of the magnetic field coupling lines in this example, the degree of magnetic field coupling is different between the 2/3 majority gate and the two-input AND gate, and furthermore, in the AND gate with the magnetic field coupling line in the center, the degree of magnetic field coupling of the central magnetic field coupling line is different. is larger than the other two lines, and there is a disadvantage that the degree of magnetic coupling between the magnetic coupling lines of the same gate increases.In essence, the circuits in Figure 2 +1) and (2) have the same signal level. is input, each circuit does not have the characteristic of responding at the same level, and the operating margin becomes small.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の、ジョセフソン接合寸法が同一で、磁界結合線の
数が異なる2種類以上の素子よりなる磁界結合型ジョセ
フソン集積回路においては、磁界結合度のばらつき(差
)が大きく、回路の動作マージンが小さい。
In conventional magnetically coupled Josephson integrated circuits, which are made up of two or more types of elements with the same Josephson junction dimensions and different numbers of magnetic coupling lines, variations (differences) in the degree of magnetic coupling are large, and the operating margin of the circuit is limited. is small.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、同一寸法を有するジョセフソン接
合上に、異なる数の磁界結合線を配設して異なる論理素
子を形成する際に、それぞれの素子の磁界結合線をそれ
ぞれのジョセフソン接合に対して同一位置に配置してな
る本発明による磁界結合型ジョセフソン集積回路により
達成される。
To solve the above problem, when different numbers of magnetic field coupling lines are arranged on Josephson junctions having the same dimensions to form different logic elements, the magnetic field coupling lines of each element are connected to each Josephson junction. This is achieved by a magnetically coupled Josephson integrated circuit according to the present invention, which is arranged in the same position as the magnetic field.

特に、1本の磁界オフセット用磁界結合線と、3、およ
び2本の入力信号用磁界結合線をそれぞれ同一寸法を有
するジョセフソン接合上に配設して2/3多数決ゲート
素子、および2入力論理積グー ト素子を形成する際に
、磁界結合綿をそれぞれのジョセフソン接合の中央に対
して対称に2本ずつ、およびその内の1本を除いた配置
で設けてなる磁界結合型ジョセフソン集積回路において
、発明の効果は大きい。
In particular, one magnetic field coupling line for magnetic field offset, three and two magnetic field coupling lines for input signals are arranged on Josephson junctions having the same dimensions, respectively, to form a 2/3 majority gate element and two input signals. When forming an AND element, two magnetic field coupling fibers are arranged symmetrically with respect to the center of each Josephson junction, and one of them is removed. The invention has great effects in integrated circuits.

〔作用〕[Effect]

本発明はジョセフソン接合寸法が同一で、磁界結合線の
数が異なる2種類以上の素子よりなる磁界結合型ジョセ
フソン集積回路においては、各素子ごとに磁界結合線の
配置を同一にすることにより磁界感度差を小さくできる
ことを実験的に確かめて、論理回路に適用したものであ
る。
The present invention provides a magnetically coupled Josephson integrated circuit consisting of two or more types of elements with the same Josephson junction dimensions and different numbers of magnetic coupling lines, by making the arrangement of the magnetic coupling lines the same for each element. It was experimentally confirmed that the difference in magnetic field sensitivity could be reduced, and the result was applied to logic circuits.

特に、磁界結合綿は接合中央においては磁気感度が大き
くなってしまうので、中央部を避けて配置した。
In particular, the magnetic field coupling cotton has a high magnetic sensitivity at the center of the joint, so it was arranged to avoid the center.

〔実施例〕〔Example〕

第1図(1)、(2)はそれぞれ本発明による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の配置を
説明する平面図である。
FIGS. 1(1) and 1(2) are plan views illustrating the arrangement of magnetic field coupling lines of a 2/3 majority gate and a two-input AND gate, respectively, according to the present invention.

実施例においても、第2図の従来例と対比して、回路構
成は簡明のために上記の組み合わせを採用する。
In this embodiment as well, in contrast to the conventional example shown in FIG. 2, the above combination is adopted for the circuit configuration for simplicity.

図において、11.21は鉛、あるいはニオブ等の超伝
導物質よりなる下部電極、12.22は同じ超伝導物質
よりなる上部電極、13.23はジョセフソン接合領域
、14.15.16.17、および24八、25A、2
6八は磁界結合線である。
In the figure, 11.21 is a lower electrode made of a superconducting material such as lead or niobium, 12.22 is an upper electrode made of the same superconducting material, 13.23 is a Josephson junction region, and 14.15.16.17 , and 248, 25A, 2
68 is a magnetic field coupling line.

第1図(1)の273多数決ゲートは第2図(1)の従
来例と同じであるが、第1図(2)の論理積ゲートの磁
界結合線の配置を273多数決ゲートの4本の磁界結合
線の内の3本と同一にしている。
The 273 majority gate in Figure 1 (1) is the same as the conventional example in Figure 2 (1), but the arrangement of the magnetic field coupling lines of the AND gate in Figure 1 (2) has been changed to the four 273 majority gates. It is made the same as three of the magnetic field coupling wires.

また、第1図(2)では最も下の磁界結合線を除いたが
、他のどれを除いてもよい。
Furthermore, in FIG. 1(2), the lowermost magnetic field coupling line is removed, but any other line may be removed.

このような配置にすることにより、2種類のゲートの磁
界結合線の配置が同一になるとともに、磁界怒度が特別
よい上部電極の中央に磁界結合線を配置することが避け
られ、磁界結合度のばらつきを低減でき、回路の動作マ
ージンを大きくすることができる。
By adopting this arrangement, the arrangement of the magnetic field coupling lines of the two types of gates is the same, and it is possible to avoid arranging the magnetic field coupling lines in the center of the upper electrode, where the magnetic field intensity is particularly good. It is possible to reduce variations in the circuit and increase the operating margin of the circuit.

第3図はジョセフソン、素子の構造を説明する八−へ断
面図である。
FIG. 3 is a cross-sectional view along the line 8 to explain the structure of the Josephson device.

図において、1は薄いアルミナ層等よりなるトンネル接
合で、それぞれ超伝導物質よりなる下部電極21と上部
電極22間に形成されてジョセフソン接合を構成する。
In the figure, reference numeral 1 denotes a tunnel junction made of a thin alumina layer or the like, which is formed between a lower electrode 21 and an upper electrode 22 each made of a superconducting material to form a Josephson junction.

2ばジョセフソン素子の領域23を画定する厚い絶縁層
である。
2 is a thick insulating layer that defines the area 23 of the Josephson element.

磁界結合線24A 、25A 、26Aば上部電極22
の上に絶縁層3を介して形成される。
The magnetic field coupling lines 24A, 25A, 26A are the upper electrode 22
is formed on top of the insulating layer 3 with an insulating layer 3 interposed therebetween.

つぎに、以上の例で説明した異なる種類のゲートで構成
された回路例として、全加算器について述べる。
Next, a full adder will be described as an example of a circuit configured with the different types of gates explained in the above example.

第4図(1)、(2)はジョセフソン素子による電流フ
リップフロップを用いた全加算器の回路図である。
FIGS. 4(1) and 4(2) are circuit diagrams of a full adder using current flip-flops using Josephson elements.

第4図(1)は和信号発生回路、第4図(2)は桁上げ
信号発生回路を示す。
FIG. 4(1) shows a sum signal generating circuit, and FIG. 4(2) shows a carry signal generating circuit.

全加算器を超伝導ループからなる電流フリップフロップ
で構成する際の一例として、和信号S、。
As an example of configuring a full adder with a current flip-flop consisting of a superconducting loop, consider the sum signal S.

、桁上げ信号C,,は、それぞれつぎのような論理で実
現できる。
, carry signal C, , can be realized by the following logic.

Sn =An (B、、Cn−+  ”Bn Cn−+
 )+An(Bh Cn−11−B、、c、−、> 。
Sn = An (B,, Cn-+ "Bn Cn-+
)+An(Bh Cn-11-B,,c,-,>.

Cn =AII Bn + C1N−1(All +B
n ) 。
Cn = AII Bn + C1N-1 (All + B
n).

で−、=A、、B、十で。−1(τn +■n ) 。So -, = A, , B, ten. -1 (τn + ■n).

ここで、All、BI、は入力信号、C,、−1は前段
からの桁上げ信号である。
Here, All, BI are input signals, and C, , -1 are carry signals from the previous stage.

和信号S7は上記の論理通りに、論理和と論理積ゲート
で構成できる。
The sum signal S7 can be constructed from a logical sum and an AND gate according to the above logic.

桁上げ信号C7は上記の論理通りでも実現できるが、回
路の段数を低域するために、2/3多数決ゲ一ト1段で
実現できる。
The carry signal C7 can be realized according to the above logic, but in order to reduce the number of circuit stages, it can be realized with one stage of 2/3 majority gate.

すなわち、2/3多数決ゲートは入力信号A1、B7、
および前段からの桁上げ信号C,,−+の3入力の内2
つ以上が“1゛であれば桁上げ信号c7は“1”となる
動作を行う。
That is, the 2/3 majority gate has input signals A1, B7,
and 2 of the 3 inputs of carry signals C,, -+ from the previous stage
If one or more are "1", the carry signal c7 becomes "1".

図において、各ループはそれぞれの分枝にジョセフソン
接合を有する電流フリ・7プフロツプである。
In the figure, each loop is a current flip-flop with a Josephson junction in each branch.

×印はジョセフソン接合(JJであらゎす)、矢印とコ
の字型の記号は磁界結合線をあられし、ここに上記の入
力信号があたえられる。
The x mark indicates a Josephson junction (referred to as JJ), and the arrow and U-shaped symbol indicate a magnetic field coupling line, to which the above input signal is applied.

この場合、2入力の論理積ゲートと273多数決ゲート
はすべての磁界結合線のしきい値〔ジョセフソン接合に
超伝導電流を流すことができる制御電流(磁界結合線に
流す電流)の限界値〕を同一にすることが望まれるため
、本発明による第1図の構造を採用した。
In this case, the 2-input AND gate and the 273 majority vote gate are the threshold values of all magnetic field coupling lines [the limit value of the control current (current flowing through the magnetic field coupling lines) that allows superconducting current to flow through the Josephson junction] Since it is desired that the two parts be the same, the structure shown in FIG. 1 according to the present invention was adopted.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、ジョセフソ
ン接合寸法が同一で、磁界結合線の数が異なる2種類以
上の素子よりなる磁界結合型ジョセフソン集積回路にお
いては、磁界結合度のばらつきが小さく、回路の動作マ
ージンが大きい。
As explained in detail above, according to the present invention, in a magnetically coupled Josephson integrated circuit consisting of two or more types of elements having the same Josephson junction dimensions and different numbers of magnetic coupling lines, variations in the degree of magnetic coupling can be achieved. is small, and the circuit operating margin is large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(1)、(2)はそれぞれ本発明による2、′3
多数決ゲートと2入力論理積ゲートの磁界結合線の配置
を説明する平面図、 第2図(1)、(2)はそれぞれ従来例による2/3多
数決ゲートと2入力論理積ゲートの磁界結合線の配置を
説明する平面図、 第3図はジョセフソン素子の構造を説明する第1図の八
−へ断面図、 第4図(1)、(2)はジョセフソン素子による電流フ
リ・ノブフロップを用いた全加算器の回路図である。 図において、 11.21は下部電極、 12.22は上部電極、 13.23はジョセフソン接合領域、 14.15.16.17.24A 、 25A 、 2
6Aは磁界結合線 である。 特許出願人 工業技術院長 等々力 達従来f111t
zよる会壱フンン呵巽托槌陶伝図蕃2Z
Figure 1 (1) and (2) are 2 and '3 according to the present invention, respectively.
A plan view illustrating the arrangement of the magnetic field coupling lines of the majority gate and the two-input AND gate. Figures 2 (1) and (2) are the magnetic field coupling lines of the conventional 2/3 majority gate and the two-input AND gate, respectively. Figure 3 is a cross-sectional view taken along line 8 in Figure 1 to explain the structure of the Josephson element. Figures 4 (1) and (2) show a current free knob flop using the Josephson element. FIG. 3 is a circuit diagram of the full adder used. In the figure, 11.21 is the lower electrode, 12.22 is the upper electrode, 13.23 is the Josephson junction region, 14.15.16.17.24A, 25A, 2
6A is a magnetic field coupling line. Patent applicant: Director of the Agency of Industrial Science and Technology Tatsu Todoroki Conventional f111t
Z-Yoru-kai 1 Hunun 2

Claims (2)

【特許請求の範囲】[Claims] (1)略同一寸法を有するジョセフソン接合上に、異な
る数の磁界結合線を配設して異なる論理素子を形成する
際に、それぞれの素子の磁界結合線をそれぞれのジョセ
フソン接合に対して同一位置に配置してなることを特徴
とする磁界結合型ジョセフソン集積回路。
(1) When arranging different numbers of magnetic field coupling lines on Josephson junctions having approximately the same dimensions to form different logic elements, the magnetic field coupling lines of each element are connected to each Josephson junction. A magnetically coupled Josephson integrated circuit characterized by being arranged at the same position.
(2)1本の磁界オフセット用磁界結合線と3、および
2本の入力信号用磁界結合線をそれぞれ略同一寸法を有
するジョセフソン接合上に配設して2/3多数決ゲート
素子、および2入力論理積ゲート素子を形成する際に、
磁界結合線をそれぞれのジョセフソン接合の中央に対し
て対称に2本ずつ、およびその内の1本を除いた配置で
設けてなることを特徴とする特許請求の範囲第1項記載
の磁界結合型ジョセフソン集積回路。
(2) One magnetic field offset magnetic field coupling line and two input signal magnetic field coupling lines are arranged on Josephson junctions having approximately the same dimensions to form a 2/3 majority gate element, and 2 When forming the input AND gate element,
The magnetic field coupling according to claim 1, characterized in that two magnetic field coupling lines are provided symmetrically with respect to the center of each Josephson junction, and one of the magnetic coupling lines is arranged except for one. Type Josephson integrated circuit.
JP60255089A 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit Granted JPS62115881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60255089A JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60255089A JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Publications (2)

Publication Number Publication Date
JPS62115881A true JPS62115881A (en) 1987-05-27
JPH0334868B2 JPH0334868B2 (en) 1991-05-24

Family

ID=17273971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60255089A Granted JPS62115881A (en) 1985-11-15 1985-11-15 Magnetic field coupling type josephson integrated circuit

Country Status (1)

Country Link
JP (1) JPS62115881A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01302785A (en) * 1988-02-10 1989-12-06 Sharp Corp Ceramic superconducting device
JPH01302784A (en) * 1988-02-10 1989-12-06 Sharp Corp Ceramic superconducting device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589381A (en) * 1981-07-08 1983-01-19 Hitachi Ltd Josephson logical circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS589381A (en) * 1981-07-08 1983-01-19 Hitachi Ltd Josephson logical circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01302785A (en) * 1988-02-10 1989-12-06 Sharp Corp Ceramic superconducting device
JPH01302784A (en) * 1988-02-10 1989-12-06 Sharp Corp Ceramic superconducting device

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JPH0334868B2 (en) 1991-05-24

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