JPS5843520A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5843520A JPS5843520A JP56141897A JP14189781A JPS5843520A JP S5843520 A JPS5843520 A JP S5843520A JP 56141897 A JP56141897 A JP 56141897A JP 14189781 A JP14189781 A JP 14189781A JP S5843520 A JPS5843520 A JP S5843520A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- semiconductor device
- layer
- exfoliation
- dummy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置ｔｔｃ＊Ｄ、特に密着露光方式にお
けるフォトレジストのはがれによる歩留シの低下を防止
出来る半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device ttc*D, and particularly to a semiconductor device that can prevent a decrease in yield due to peeling of photoresist in a contact exposure method.
最近、集積回路の高密度化が急速に進んでおシ。Recently, the density of integrated circuits has been rapidly increasing.
面方向の縮小化はもちろんの事、縦方向についても、二
層、三層構造が一般化している。In addition to shrinking in the plane direction, two-layer and three-layer structures are becoming common in the vertical direction as well.
しかしながら、縦方向の重なシがふ見るにつれて密着露
光方式におけるフォトレジストはがれが問題となってく
る。４ＩＫ微細化に対応するためポジ型フォトレジスト
（例えば商品名人ｚ−ｔａｙ。However, as the number of overlapping lines in the vertical direction increases, peeling of the photoresist in the contact exposure method becomes a problem. In order to respond to 4IK miniaturization, positive photoresists (for example, the product Meijin Z-tay.
など）を用いる場合には、ポジ型フォトレジストと酸化
膜、又はポリシリコン等の密着性が悪いため、突起部で
のフォトレジストとマスクの密着くよる。フォトレジス
トのはがれが大きな問題となる。etc.), the adhesion between the positive photoresist and the oxide film, polysilicon, etc. is poor, resulting in the photoresist and mask coming into close contact at the protrusions. Peeling of photoresist becomes a major problem.
第１図はフォトレジストはがれの一例について示すもの
である。第１図（ａ） において半導体基板（１）上に
酸化膜（２）を成長させ、−″層ポＩＪ ｙ ＩＪコ／
（２）をパター／ユングしたあと酸化し、その上に二層
目のポリシリコｙ（３）を成長させる。このポリシリコ
。FIG. 1 shows an example of photoresist peeling. In FIG. 1(a), an oxide film (2) is grown on a semiconductor substrate (1), and -'' layer po IJ y IJ co/
After patterning/junging (2), it is oxidized, and a second layer of polysilico (3) is grown on it. This polysilico.
ン（４）のパターン二／グのためにポジ型フォトレジス
ト（５）を塗布し１位置合せ後フォトマスク（６）と強
制密着させる。この時、突起部がＡ部のみで、近傍に他
の突起部が壜いときマスクの圧力は全て人に集中し、そ
の結果第１図（ｂ） Ｋ示す如く、突起部の７オトレジ
ストがはがれてしまいポリシリコンのエッチフグ後は、
第１図（Ｃ）に示す如く、フォトレジストがはがれたと
ころのポリシリコ／は、工、チングされてしまい、その
テップは不良となってしまう。パ
本発明は上記の欠点が改＾され先手導体装置を・提供す
ゐ事を目的としている。A positive type photoresist (5) is applied for patterning the pattern (4), and after one positioning, it is forcibly brought into close contact with a photomask (6). At this time, when the protrusion is only part A and there are other protrusions nearby, all the pressure of the mask is concentrated on the person, and as a result, as shown in Figure 1 (b) K, the 7 otoresist on the protrusions peels off. After etching the polysilicon,
As shown in FIG. 1(C), the polysilico layer where the photoresist has peeled off is etched, resulting in a defective step. SUMMARY OF THE INVENTION It is an object of the present invention to provide a proactive conductor device in which the above-mentioned drawbacks are corrected.
本発明の４黴は、半導体基板表面に、この表面よシ突出
した突起部を有する素子が設けられ、この素子の近傍Ｉ
／ｃこの突ｉ部と同じ高さか、それ以上の高さ宝有する
ダミー素子が設けられた半導体装置ＫＴｏる。例えに、
半導体基板表面に設けられえ、突起部のうち央起高さが
最大である素子のごく近傍に前記最高突起部゛と同じ高
さか、それ以上の高さを有するダン−“素子−設けた半
導体装置である。In the fourth mold of the present invention, an element having a protrusion protruding from the surface is provided on the surface of a semiconductor substrate, and an I
/c A semiconductor device KTo is provided with a dummy element having a height equal to or greater than the protrusion i. For example,
A semiconductor device which can be provided on the surface of a semiconductor substrate, and has a dan-shaped element having the same height as or greater than the highest protrusion in the vicinity of the element having the largest central elevation among the protrusions. It is a device.
以下１本発明の一笑施一について１図面を用いて説明す
る。Hereinafter, the present invention will be explained with reference to one drawing.
第２図は本発明の−→例を示すものである。FIG. 2 shows a −→ example of the present invention.
１１ｇ２図（ａ）Ｋ示す如く１本来必要とする素子ムの
ごく近傍に同じ高さか、それ以上の高さを有するダン−
領域Ｂ、Ｃを設ける事を特徴としている。11g2 As shown in Fig. 2(a)K, there is a damper with the same height or higher in the vicinity of the originally required element.
It is characterized by providing areas B and C.
このような構造をもつ装置に第２図書）に示す如くフォ
トマスク（６）を強制書着させても圧力は均一に・ か
かるか、又はＢ、ｃｍ領域に強くかかシ１本来必要とす
る人の領域の７オトレジストがはがれる事はなく従うて
歩留）の低下はない。Even if the photomask (6) is forcibly attached to an apparatus with such a structure as shown in Figure 2), the pressure is applied uniformly, or the pressure is applied strongly to the area B, cm, which is originally required. 7 The photoresist in the human area does not peel off, so there is no decrease in yield.
以上の説明は、二層ポリシリコン層を有する半導体装置
について行ったが他の材料及びさらに多層の構造をもつ
半導体装置についても全く同様に説明できる。Although the above explanation has been made regarding a semiconductor device having a two-layer polysilicon layer, the same explanation can be applied to a semiconductor device made of other materials and having a multilayer structure.
以上の説明より１本発明を用いれば、フォトレジストの
はがれによる歩留夛の低下を、おさえ得る事が十分可能
である事がわかる。From the above explanation, it can be seen that by using the present invention, it is possible to suppress the decrease in yield due to photoresist peeling.
第１図（ａ） 、 （ｂ） 、 （ｃ）は従来の構造を
有する半導体装置について説！する途中工種の断面図、
第２図（ｓｄ 、 （ｂ）ｄＥＥ発明叶実總例を示す半
導体装置の途中王権の断面図、である。
なお図において、１・・・・・・半導体基板、２・・・
・・・酸化膜、３・・・・・・第一層ポリシリコン、４
・・・・・・第二層ポリシリコン、ト・・・・・フォト
レジスト、６・・・・・・７オトマスク、 である。。
、′
−＋ ３ １
。Figures 1 (a), (b), and (c) describe semiconductor devices with conventional structures! A cross-sectional view of the work in progress,
FIG. 2 (sd, (b) is a cross-sectional view of a semiconductor device showing an example of the implementation of the dEE invention. In the figure, 1... semiconductor substrate, 2...
...Oxide film, 3...First layer polysilicon, 4
. . . second layer polysilicon, . . . photoresist, 6 . . . 7 photomask. . ,' −+ 3 1
.
Claims (1)
子が設けられ、該素子の近傍に前記突起部と同じ高さか
、それ以上の高さを有するダ（−素子が設けられている
事を特徴とする半導体装置。An element having a protrusion protruding from the center of the surface of the semiconductor substrate is provided, and a da(-element) having a height equal to or greater than the protrusion is provided near the element. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141897A JPS5843520A (en) | 1981-09-09 | 1981-09-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56141897A JPS5843520A (en) | 1981-09-09 | 1981-09-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5843520A true JPS5843520A (en) | 1983-03-14 |
Family
ID=15302702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56141897A Pending JPS5843520A (en) | 1981-09-09 | 1981-09-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843520A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60177669A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor memory device |
| JPS61194771A (en) * | 1985-02-25 | 1986-08-29 | Hitachi Ltd | Semiconductor memory |
-
1981
- 1981-09-09 JP JP56141897A patent/JPS5843520A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60177669A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor memory device |
| US5416347A (en) * | 1984-02-24 | 1995-05-16 | Hitachi, Ltd. | Semiconductor memory device with additional conductive line to prevent line breakage |
| JPS61194771A (en) * | 1985-02-25 | 1986-08-29 | Hitachi Ltd | Semiconductor memory |
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