JPH04372133A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the packing density of a semiconductor device by providing an interconnection for small current and a thick interconnection for large current on the same layer so that the interconnection for large current may be narrowed to reduce the area of interconnections. CONSTITUTION:A first interconnection 6 for small current is formed on an insulating film 2 over a semiconductor substrate 1. A second interconnection 7 for large current, thicker than the first interconnection, is formed on the same layer as the first interconnection. For example, a first PR film 4 is applied over an aluminum layer 3, and it is patterned into a mask to be used to form the interconnection for large current. The mask is used to anisotropically etch the upper part of the aluminum layer 3. As a result, the aluminum layer is thinned selectively. Then, a second PR film is applied and patterned into a mask to be used to form the interconnection for signal interconnection on the thin part of the aluminum layer 3. The aluminum layer 3 is subjected to anisotropic etching with the PR films 4 and 5 used as masks to form the first and second interconnections 6 and 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to wiring and a method of manufacturing the same.

0002

[Prior Art] A conventional semiconductor integrated circuit is shown in FIG.
As shown in (b), a P-channel MOSFET is formed in the N-type well 9 provided in the P-type silicon substrate 1, and an N-channel MOSFET is formed in the P-type silicon substrate 1, and the power source V
Connect to cc and GND wiring 8 and input and output wiring 6 and connect CM
It constitutes an OS inverter circuit.

0003

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit, the Vcc wiring and GND wiring, which serve as power supply sources, usually have a wide wiring width (40 μm or more) and have a layout configuration that is resistant to noise. Must be. On the other hand, if the signal wiring is too thick, the wiring capacitance will increase, causing a delay in switching speed, and will also cause an increase in the layout area. It is preferable to leave it as

With the recent increase in the scale of LSIs, microfabrication technology has progressed, and as technology such as adding Cu to aluminum wiring becomes possible as a measure to enhance migration, signal wiring becomes thinner and thinner, and wiring film thickness also increases. While the trend is towards thinner films, Vcc and GND wiring cannot be made thinner due to the need to maintain their performance, and on the contrary, there are cases where they have to be designed thicker, which hinders downsizing. This is a major contributing factor.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a first wiring for small current disposed on an insulating film provided on a semiconductor substrate, and a layer in the same layer as the first wiring. and a second wiring for large current, which is disposed in the second wiring and has a thicker film thickness than the first wiring.

The method for manufacturing a semiconductor integrated circuit of the present invention includes the steps of depositing a metal layer on an insulating film provided on a semiconductor substrate, and depositing a first photoresist film patterned on the metal layer. a step of anisotropically etching the upper part of the metal layer using the first photoresist film as a mask to reduce the thickness of the metal layer; and heating and hardening the first photoresist film. After that, applying a second photoresist film to the surface including the first photoresist film and patterning it to form a pattern for forming wiring on a thin region of the metal layer; and a step of anisotropically etching the metal layer using a second photoresist film as a mask to simultaneously form a thin first wiring for small current and a thick second wiring for large current. It consists of:

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

First, as shown in FIG. 1(a), an aluminum layer 3 is deposited to a thickness of 2 to 3 μm by sputtering on an interlayer insulating film 2 formed on a P-type silicon substrate 1. A first photoresist film (hereinafter referred to as PR film) 4 is coated on the aluminum layer 3 and patterned to form a pattern for forming large current wiring such as a power supply or ground line.

Next, as shown in FIG. 1(b), the PR film 4
Using this as a mask, the upper part of the aluminum layer 3 is anisotropically etched to reduce the thickness of the aluminum layer 3 to about 1 μm. Next, baking is performed to harden the PR film 4.

Next, as shown in FIG. 1(c), the PR film 4
A second PR film 5 is applied to the surface including the.

Next, as shown in FIG. 1(d), a signal wiring pattern is formed on the thin area of the aluminum layer 3 by exposure using a reticle with a signal wiring pattern and development. Form. Here, since the PR film 4 is baked, it remains without being peeled off by a normal developing method.

Next, as shown in FIG. 1(e), the PR film 4
, 5 as a mask, and then the PR films 4 and 5 are peeled off using a plasma method to form a narrow first wiring 6 for small current and a thin first wiring 6 for large current. Each of the second wirings 7 having a wide width and a thick film thickness is formed.

In the above embodiment, the spacing between the interconnections 6 should satisfy the conventional spacing of about 1 μm, but the spacing between the interconnections 6 and 7 is different from that between the first and second PR films. 4
, 5 and the difference in the film thickness of the PR film 5 at the end of the wiring 7, it is necessary to widen the interval (approximately 4 to 5 μm), but the effect of reducing the wiring width is greater. is large and does not hinder the reduction of the layout area.

[0015]

As explained above, the present invention provides a thin first wiring for small current and a thick second wiring for large current in the same layer. This has the effect of reducing the width of the large current wiring, which occupies a large area in the past, thereby reducing the area occupied by the wiring and improving the degree of integration.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a layout diagram and an enlarged cross-sectional view taken along line A-A' showing an example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 P-type silicon substrate 2 Interlayer insulation film 3 Aluminum layer 4,5 PR film 6,7,8 Wiring 9 N type well

Claims (3)

[Claims] 1. A first wiring for small current disposed on an insulating film provided on a semiconductor substrate, and a first wiring disposed on the same layer as the first wiring and further from the first wiring. 1. A semiconductor integrated circuit comprising: a second wiring for large current having a thick film thickness. 2. The semiconductor integrated circuit according to claim 1, wherein the second wiring is a power supply wiring or a ground wiring. 3. Depositing a metal layer on an insulating film provided on a semiconductor substrate; providing a first photoresist film patterned on the metal layer; a step of anisotropically etching the upper part of the metal layer using a resist film as a mask to reduce the thickness of the metal layer, and heating the first photoresist film to harden it, and then curing the first photoresist film. a step of applying and patterning a second photoresist film on a surface including the metal layer to form a pattern for forming wiring on a thin region of the metal layer; and masking the first and second photoresist films. a step of anisotropically etching the metal layer to simultaneously form a thin first wiring for small current and a thick second wiring for large current. Method of manufacturing circuits.