JP2887370B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2887370B2
JP2887370B2 JP5012570A JP1257093A JP2887370B2 JP 2887370 B2 JP2887370 B2 JP 2887370B2 JP 5012570 A JP5012570 A JP 5012570A JP 1257093 A JP1257093 A JP 1257093A JP 2887370 B2 JP2887370 B2 JP 2887370B2
Authority
JP
Japan
Prior art keywords
layer
forming
hole
mask pattern
electrode material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5012570A
Other languages
Japanese (ja)
Other versions
JPH06224250A (en
Inventor
干城 清水
明 初谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Denki Co Ltd
Original Assignee
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Denki Co Ltd filed Critical Sanyo Denki Co Ltd
Priority to JP5012570A priority Critical patent/JP2887370B2/en
Publication of JPH06224250A publication Critical patent/JPH06224250A/en
Application granted granted Critical
Publication of JP2887370B2 publication Critical patent/JP2887370B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は多層配線技術により積層
した構造を有するボンディングパッド部分の改良に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a bonding pad portion having a structure laminated by a multilayer wiring technique.

【０００２】[0002]

【従来の技術】半導体集積回路においては、内部回路を
外部に接続するためのボンディングパッドを有する。ボ
ンディングパッドは内部回路の接続配線の一部として形
成され、接続配線が２層、３層構造を有する場合はボン
ディングパッドも同じく２層、３層構造となる。2. Description of the Related Art Semiconductor integrated circuits have bonding pads for connecting internal circuits to the outside. The bonding pad is formed as a part of the connection wiring of the internal circuit. When the connection wiring has a two-layer or three-layer structure, the bonding pad also has a two-layer or three-layer structure.

【０００３】２層構造のボンディングパッドの断面構造
を図７に示す。同図において、（１）はシリコン酸化
膜、（２）は１層目Ａｌ配線により形成したボンディン
グパッドの第１の層、（３）はポリイミド系樹脂から成
る層間絶縁膜、（４）は層間絶縁膜（３）に形成したス
ルーホール、（５）は２層目Ａｌ配線により形成したボ
ンディングパッドの第２の層である。ボンディングパッ
ドの第１と第２の層（２）（５）は同じく１５０×１５
０μ程の大きさを有し、第１の層（２）からはシリコン
酸化膜（１）上を延在する幅１０μ程度の電極配線で内
部回路と結線されている。ワイヤのボールを熱圧着する
ための平坦部分をできるだけ広くとるため、スルーホー
ル（４）は大きな面積で開口されている。FIG. 7 shows a sectional structure of a bonding pad having a two-layer structure. In the figure, (1) is a silicon oxide film, (2) is a first layer of a bonding pad formed by a first-layer Al wiring, (3) is an interlayer insulating film made of polyimide resin, and (4) is an interlayer insulating film. The through hole formed in the insulating film (3), and (5) is the second layer of the bonding pad formed by the second-layer Al wiring. The first and second layers (2) and (5) of the bonding pad are also 150 × 15
It has a size of about 0μ, and is connected to the internal circuit by an electrode wiring of about 10μ width extending from the first layer (2) on the silicon oxide film (1). The through hole (4) is opened with a large area in order to make the flat portion for thermocompression bonding of the wire ball as wide as possible.

【０００４】一方、層間絶縁膜（３）に用いたポリイミ
ド系樹脂は、安価で被覆性に優れる等の優れた特徴を有
するものの、Ａｌドライエッチに対する耐性に劣るとい
う性質を有する。そのため、２層目Ａｌ配線のパターニ
ングはウェット手法で行うのが一般的である。２層目Ａ
ｌ配線をパターニングする時の状況を図８に示す。先ず
スルーホール（４）を形成した層間絶縁膜（３）の上に
Ａｌ層（６）を被着し、被着したＡｌ層（６）の上にホ
トレジスト層（７）を形成する。ホトマスクを用いてホ
トレジスト層（７）を部分的に感光させ、マスクパター
ン（８）となる領域を除いてホトレジスト層（７）を除
去し、残ったマスクパターン（８）によりＡｌ層（６）
をウェットエッチングしてボンディングパッドの第２の
層（５）を形成するものである。On the other hand, the polyimide resin used for the interlayer insulating film (3) has excellent characteristics such as being inexpensive and excellent in coatability, but has a property of being inferior in resistance to Al dry etching. Therefore, patterning of the second layer Al wiring is generally performed by a wet method. Second layer A
FIG. 8 shows a situation when patterning the l wiring. First, an Al layer (6) is deposited on the interlayer insulating film (3) in which the through hole (4) is formed, and a photoresist layer (7) is formed on the deposited Al layer (6). The photoresist layer (7) is partially exposed using a photomask, the photoresist layer (7) is removed except for a region to be the mask pattern (8), and the Al layer (6) is formed by the remaining mask pattern (8).
Is wet-etched to form a second layer (5) of the bonding pad.

【０００５】[0005]

【発明が解決しようとする課題】しかしながら、ホトレ
ジスト層（７）は粘性を有する溶液をスピンオンコート
してウェハ上に形成することから、ウェハ表面の凹凸を
平坦化するようにして被着する。すると、図８に示すよ
うに第１の層（２）と層間絶縁膜（３）とにより形成さ
れた段差により、スルーホール（４）周辺部分の膜厚ｔ
1が最も薄くなる。条件にもよるが、平坦部での膜厚ｔ2
を１．５μとした場合に、スルーホール（４）周辺部分
の膜厚ｔ1は４０００Å程度にしかならない。膜厚がこ
れだけ薄くなると、ホトレジスト層（７）の密着力が低
下してくる。However, since the photoresist layer (7) is formed on the wafer by spin-on coating with a viscous solution, the photoresist layer (7) is applied so as to flatten the unevenness on the wafer surface. Then, as shown in FIG. 8, a step formed by the first layer (2) and the interlayer insulating film (3) causes a film thickness t around the through hole (4).
1 is the thinnest. Depending on the conditions, the film thickness t 2 at the flat portion
Is 1.5 μm, the thickness t 1 around the through hole (4) is only about 4000 °. When the film thickness is so thin, the adhesion of the photoresist layer (7) decreases.

【０００６】このように密着力が低下してくると、ホト
レジスト層（７）をベークした際にホトレジスト層
（７）自身の収縮力により、パターンが図９に示すよう
な形状に縮退し、マスクパターン（７）がＡｌ層（６）
からはがれてしまう。特にボンディングパッドは比較的
大面積を有し、第２の層（５）は他とは接続されない島
状のパターンを有することから、他の電極配線パターン
に比べてはがれ易い状態にある。また、微細加工に適し
たポジ型レジストを用いると、元来の密着力がネガ型の
ものより劣るのではがれも大きい。そのため、マスクパ
ターン（８）のはがれが生じたままでウェットエッチン
グを行うと、Ａｌエッチャントがはがれた部分にも侵入
し、ボンディングパッドのパターン原形が崩れるばかり
か、極端な例では図１０に示すように第１の層（２）ま
でエッチングされてしまうことがあった。第１の層
（２）には内部回路との接続配線が連続しているので、
この様な部分がエッチングされると内部回路との導通を
失うこともある。When the adhesion decreases, the pattern shrinks to the shape shown in FIG. 9 due to the contraction force of the photoresist layer (7) itself when the photoresist layer (7) is baked. Pattern (7) is Al layer (6)
It will come off. In particular, since the bonding pad has a relatively large area and the second layer (5) has an island-shaped pattern that is not connected to the other, it is in a state where it is more easily peeled off than other electrode wiring patterns. In addition, when a positive resist suitable for fine processing is used, the original adhesive strength is inferior to that of a negative resist, and the peeling is large. Therefore, if wet etching is performed while the mask pattern (8) is peeled off, the Al etchant also penetrates the peeled part, not only disturbing the original pattern of the bonding pad, but also in an extreme case, as shown in FIG. In some cases, the first layer (2) was etched. Since the connection wiring with the internal circuit is continuous in the first layer (2),
When such a portion is etched, conduction with an internal circuit may be lost.

【０００７】[0007]

【課題を解決するための手段】本発明は上述した従来の
欠点に鑑み成されたもので、ボンディングパッドの第２
の層（１８）を形成するマスクパターン（１７）を形成
するに際し、その端を膜厚が十分に厚くなる位置まで拡
張することによりマスクパターン（１７）のはがれによ
る不具合を解消した半導体装置の製造方法を提供するも
のである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages, and has been made in consideration of the above-mentioned problems.
Of forming a mask pattern (17) for forming the layer (18) of the present invention, the end of the mask pattern (17) is expanded to a position where the film thickness becomes sufficiently large, thereby eliminating the problem caused by peeling of the mask pattern (17). It provides a method.

【０００８】[0008]

【作用】本発明によれば、レジスト膜厚が厚くなる位置
までマスクパターン（１７）の端を増大させたので、端
部での密着力が強化されてマスクパターン（１７）のは
がれを防止できる。According to the present invention, the end of the mask pattern (17) is increased to a position where the resist film thickness is increased, so that the adhesion at the end is strengthened and the peeling of the mask pattern (17) can be prevented. .

【０００９】[0009]

【実施例】以下に本発明の一実施例を図面を参照しなが
ら詳細に説明する。図１を参照して、半導体チップの表
面にはＢｉＰ，ＭＯＳ、受動素子等が通常のプロセスに
よって作り込まれており、その表面はシリコン酸化膜
（１１）で被覆された状態になっている。シリコン酸化
膜（１１）に図示せぬコンタクトホールを開孔した後膜
厚１．０μ程度のＡｌ又はＡｌ−Ｓｉ層をスパッタ堆積
し、これをホトエッチすることにより各回路素子を相互
接続する１層目電極配線を形成すると同時にチップの周
辺部分にボンディングパッドの第１の層（１２）を形成
する。第１の層（１２）はワイヤボンディングするのに
十分な大きさ、例えば１５０×１５０μの正方形に形成
され、その一部にはシリコン酸化膜（１１）上を延在し
て前記１層目電極配線と連続する線幅１０μ程度の電極
配線が引き出されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. Referring to FIG. 1, BiP, MOS, passive elements, and the like are formed on the surface of a semiconductor chip by a normal process, and the surface is covered with a silicon oxide film (11). After opening a contact hole (not shown) in the silicon oxide film (11), an Al or Al-Si layer having a thickness of about 1.0 μm is sputter-deposited, and this is photoetched to form a single layer for interconnecting the circuit elements. At the same time as forming the eye electrode wiring, a first layer (12) of a bonding pad is formed on a peripheral portion of the chip. The first layer (12) is formed in a square having a size sufficient for wire bonding, for example, 150 × 150 μm, and partially extends on the silicon oxide film (11) to form the first layer electrode. An electrode wiring with a line width of about 10 μ continuous with the wiring is drawn out.

【００１０】次いで全面にポリイミド系樹脂をスピンオ
ンコート法により被着して膜厚２．０μ程の層間絶縁膜
（１３）を形成し、これをホトエッチングすることによ
り層間接続用のスルーホール（１４）を形成する。スル
ーホール（１４）はマスクずれ量を考慮した大きさで第
１の層（１２）の大部分を露出する。図２を参照して、
２層目電極配線を形成するためのＡｌ又はＡｌ−Ｓｉか
ら成る第２の電極材料層（１５）を全面にスパッタ被着
する。膜厚は１．０μ程度である。スパッタ被着する電
極材料に平坦化作用は無く、ポリイミド系樹脂の平坦化
作用にも限度があるので、スルーホール（１４）の周辺
部分に第１の層（１２）と層間絶縁膜（１３）とによる
段差を生じることになる。Next, a polyimide resin is applied to the entire surface by spin-on coating to form an interlayer insulating film (13) having a thickness of about 2.0 μm, and this is photo-etched to form a through hole (14) for interlayer connection. ) Is formed. The through hole (14) exposes most of the first layer (12) in a size taking into account the mask shift amount. Referring to FIG.
A second electrode material layer (15) made of Al or Al-Si for forming a second-layer electrode wiring is deposited by sputtering over the entire surface. The thickness is about 1.0 μm. Since the electrode material to be sputter-deposited has no flattening action and the flattening action of the polyimide resin is limited, the first layer (12) and the interlayer insulating film (13) are provided around the through hole (14). And a step due to the above.

【００１１】図３を参照して、第２の電極材料層（１
５）をホトエッチするためにその上にホトレジスト層
（１６）を形成する。ホトレジストとして例えばＯＦＰ
Ｒ８００（東京応化）なるポジ型レジストを用い、これ
をスピンオンコートして平坦部での膜厚が１．５μとな
るように形成した。レジスト自体は粘性を有する液体で
あるから、前記スルーホール（１４）周囲の段差部分で
最も薄く、凹んだ部分で厚く被着する。Referring to FIG. 3, a second electrode material layer (1
5) A photoresist layer (16) is formed thereon for photoetching. For example, OFP as a photoresist
R800 (Tokyo Ohka Co., Ltd.) was used and spin-on coated to form a film having a thickness of 1.5 μm on a flat portion. Since the resist itself is a viscous liquid, the resist is thinnest at the step around the through hole (14) and thick at the recess.

【００１２】図４を参照して、２層目電極配線をパター
ニングするためのホトマスクによりホトレジスト層（１
６）を露光してパターン転写する。前記ホトマスクのパ
ターンは設計変更によりパッド部のみ約５μ程度従来よ
り拡張されており、マスクパターン（１７）となる感光
領域の端が拡張された分だけ第１の層（１２）より外側
に位置することになる。スルーホール（１４）周端から
外側に外れるほどレジスト層の平坦化作用により膜厚が
厚くなるので、マスクパターン（１７）端部でのレジス
ト膜厚は最も薄い部分（約０．４μ）より厚く０．８〜
１．２μ程度となる。Referring to FIG. 4, a photoresist layer (1) is formed using a photomask for patterning the second-layer electrode wiring.
6) is exposed and the pattern is transferred. The pattern of the photomask is expanded by about 5 μm only in the pad portion as compared with the conventional one due to a design change, and the photomask pattern (17) is located outside the first layer (12) by the expanded end of the photosensitive region. Will be. The thickness of the resist layer at the end of the mask pattern (17) is larger than the thinnest portion (about 0.4 μm) because the thickness of the resist layer at the end of the mask pattern (17) is greater as the resist layer becomes flatter outside the periphery of the through hole (14). 0.8 ~
It is about 1.2 μ.

【００１３】図５を参照して、ホトレジスト層（１６）
を現像することにより未感光部分を除去し、ベークした
後残ったマスクパターン（１７）により第２の電極材料
層（１５）をパターニングして第２の層（１８）を形成
する。パターニングはＡｌのウェットエッチャントで行
う。本発明によればマスクパターン（１７）端部の膜厚
が十分厚くなっており、ホトレジストの収縮力に十分耐
えられるだけの密着力が保たれているので、マスクパタ
ーン（１７）のはがれは無い。よって正確なパターンで
第２の層（１８）を形成することができる。Referring to FIG. 5, a photoresist layer (16)
The second electrode material layer (15) is patterned by the mask pattern (17) remaining after baking to remove the unexposed portion by developing the second layer (18). Patterning is performed with a wet etchant of Al. According to the present invention, the thickness of the end portion of the mask pattern (17) is sufficiently large, and the adhesion strength enough to withstand the contraction force of the photoresist is maintained, so that the mask pattern (17) does not peel. . Therefore, the second layer (18) can be formed in an accurate pattern.

【００１４】その後、マスクパターン（１７）を除去す
ると図６に示すように第１の層（１２）より第２の層
（１８）が全周にわたり拡張されたボンディングパッド
が得られる。（１９）は第１の層（１２）から連続する
電極配線である。第２の層（１８）の上には最終的なパ
ッシベーション被膜が形成され、パッシべーション被膜
にはワイヤボンド用の開孔がスルーホール（１４）より
同じかやや広い面積で設けられている。Thereafter, when the mask pattern (17) is removed, a bonding pad in which the second layer (18) is extended from the first layer (12) over the entire circumference as shown in FIG. 6 is obtained. (19) is an electrode wiring continuous from the first layer (12). A final passivation film is formed on the second layer (18), and the passivation film has openings for wire bonding with the same or slightly larger area than the through holes (14).

【００１５】このように本発明によれば、マスクパター
ン（１７）を拡張することによって、マスクパターン
（１７）のはがれというプロセス的な問題を解消できる
ものである。尚、本発明は２層配線を例にして説明して
きたが、３層配線、４層配線の場合も順次拡張していけ
ば良いことは言うまでもない。As described above, according to the present invention, by expanding the mask pattern (17), it is possible to solve the process problem of peeling of the mask pattern (17). Although the present invention has been described by taking the two-layer wiring as an example, it goes without saying that the case of three-layer wiring and four-layer wiring may be sequentially expanded.

【００１６】[0016]

【発明の効果】以上に説明した通り、本発明によればホ
トレジスト層（１６）を膜厚が厚い位置でパターニング
することによりマスクパターン（１７）の密着力を増大
し、そのはがれを防止することによって従来の不具合を
解消できる利点を有する。また、マスクパターンの変更
のみで即実施可能であり、さらには２層目以降は配線密
度に対する要求が緩やかになるので、第２の層（１８）
を拡張したことによるチップサイズの増大が無い利点を
も有する。As described above, according to the present invention, the adhesion of the mask pattern (17) is increased by patterning the photoresist layer (16) at a position where the film thickness is large, and the peeling thereof is prevented. This has the advantage that conventional problems can be solved. In addition, since it is possible to immediately carry out only by changing the mask pattern, and since the demand for the wiring density becomes loose in the second and subsequent layers, the second layer (18)
There is also an advantage that there is no increase in chip size due to the expansion of.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の説明するための第１の断面図である。FIG. 1 is a first sectional view for explaining the present invention.

【図２】本発明の説明するための第２の断面図である。FIG. 2 is a second sectional view for explaining the present invention.

【図３】本発明の説明するための第３の断面図である。FIG. 3 is a third sectional view for explaining the present invention.

【図４】本発明の説明するための第４の断面図である。FIG. 4 is a fourth sectional view for explaining the present invention.

【図５】本発明の説明するための第５の断面図である。FIG. 5 is a fifth sectional view for explaining the present invention.

【図６】本発明の説明するための平面図である。FIG. 6 is a plan view for explaining the present invention.

【図７】従来構造を示す断面図である。FIG. 7 is a sectional view showing a conventional structure.

【図８】従来の欠点を説明するための第１の断面図であ
る。FIG. 8 is a first sectional view for explaining a conventional defect.

【図９】従来の欠点を説明するための平面図である。FIG. 9 is a plan view for explaining a conventional defect.

【図１０】従来の欠点を説明するための第２の断面図で
ある。FIG. 10 is a second sectional view for explaining a conventional defect.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−51863（ＪＰ，Ａ) 特開 昭52−95171（ＪＰ，Ａ) 特開 昭62−217624（ＪＰ，Ａ) 特開 平４−302153（ＪＰ，Ａ) 実開 昭58−122447（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 301 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-51863 (JP, A) JP-A-52-95171 (JP, A) JP-A-62-217624 (JP, A) 302153 (JP, A) Japanese Utility Model Showa 58-1222447 (JP, U) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60 301

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 多層構造を有する外部接続用ボンディン
グパッドの製造方法であって、 第１の電極材料を被着しこれをパターニングすることに
より前記ボンディングパッドの第１の層を形成する工程
と、 前記第１の層の表面を被覆するポリイミド系の層間絶縁
膜を形成する工程と、 前記層間絶縁膜に前記第１の層の表面を露出するスルー
ホールを形成する工程と、 全面に、前記層間絶縁膜と前記スルーホールとで形成さ
れる表面段差に準じた段差を有する、第２の電極材料を
被着する工程と、 前記第２の電極材料の上に、スピンオンコートにより、
前記スルーホールの上部で膜厚が厚く、前記スルーホー
ルの周辺部分で膜厚が薄く、前記スルーホールの周辺部
分から離れた箇所で再び膜厚が厚くなる、ホトレジスト
層を形成する工程と、 前記ホトレジスト層を露光、現像してマスクパターンを
形成するに際し、その端をホトレジスト層の膜厚が前記
スルーホールの周辺部分の薄い膜厚より厚くなる位置ま
で拡張してマスクパターンを形成する工程と、前記マスクパターンを選択マスクとして前記第２の電極
材料をウェットエッチングすることにより、 前記第１の
層より拡張された大きさを有する第２の層を形成する工
程とを具備することを特徴とする半導体装置の製造方
法。1. A method of manufacturing a bonding pad for external connection having a multilayer structure, comprising: forming a first layer of the bonding pad by applying a first electrode material and patterning the first electrode material. forming an interlayer insulating film of polyimide covering the surface of said first layer, forming a through hole to expose the surface of the first layer in the interlayer insulating film, on the entire surface, the interlayer Formed by an insulating film and the through hole
A step of applying a second electrode material having a step corresponding to the surface step to be performed, and spin-on coating on the second electrode material ,
The film thickness is thick at the upper part of the through hole and thin at the peripheral part of the through hole, and the peripheral part of the through hole
A step of forming a photoresist layer in which the film thickness is increased again at a location away from the substrate , and exposing and developing the photoresist layer to form a mask pattern. Forming a mask pattern extending to a position thicker than the thin film thickness of the portion; and forming the second electrode using the mask pattern as a selection mask.
Forming a second layer having a size larger than that of the first layer by wet-etching the material . 【請求項２】 前記ホトレジストがポジ型レジストであ
ることを特徴とする請求項１記載の半導体装置の製造方
法。2. The method according to claim 1, wherein said photoresist is a positive resist.
JP5012570A 1993-01-28 1993-01-28 Method for manufacturing semiconductor device Expired - Lifetime JP2887370B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5012570A JP2887370B2 (en) 1993-01-28 1993-01-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5012570A JP2887370B2 (en) 1993-01-28 1993-01-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH06224250A JPH06224250A (en) 1994-08-12
JP2887370B2 true JP2887370B2 (en) 1999-04-26

Family

ID=11809022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5012570A Expired - Lifetime JP2887370B2 (en) 1993-01-28 1993-01-28 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2887370B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002062119A1 (en) 2000-12-22 2002-08-08 Cereva Networks, Inc. Electronic circuitry enclosure with air vents

Also Published As

Publication number Publication date
JPH06224250A (en) 1994-08-12

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