JPS5841679B2 - How to mount components on a multilayer wiring board - Google Patents

How to mount components on a multilayer wiring board

Info

Publication number
JPS5841679B2
JPS5841679B2 JP53126079A JP12607978A JPS5841679B2 JP S5841679 B2 JPS5841679 B2 JP S5841679B2 JP 53126079 A JP53126079 A JP 53126079A JP 12607978 A JP12607978 A JP 12607978A JP S5841679 B2 JPS5841679 B2 JP S5841679B2
Authority
JP
Japan
Prior art keywords
wiring board
leads
multilayer wiring
heating
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53126079A
Other languages
Japanese (ja)
Other versions
JPS5553486A (en
Inventor
信雄 笹川
勇吉 竹田
和美 田中
勝比古 白井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53126079A priority Critical patent/JPS5841679B2/en
Publication of JPS5553486A publication Critical patent/JPS5553486A/en
Publication of JPS5841679B2 publication Critical patent/JPS5841679B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は多層配線基板への電子部品の実装方法特に複数
連にフラットリードを有する部品の実装方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for mounting electronic components on a multilayer wiring board, and particularly to a method for mounting components having a plurality of series of flat leads.

従来、多層配線基板にLSIの如く多数のリードを持ち
第1図に示す如くその複数連にフラットリード1を配し
た電子部品2を実装するときには、予め半田被覆を施し
たパッドに各リードを位置合せして載せた後、加熱用チ
ップをリードに押圧してパッド上の半田を溶融させて接
合する、いわゆるリフローボンディング法が一般に用い
られている。
Conventionally, when mounting an electronic component 2 having a large number of leads such as an LSI on a multilayer wiring board and having flat leads 1 arranged in multiple series as shown in FIG. 1, each lead is positioned on a pad coated with solder in advance. A so-called reflow bonding method is generally used, in which the heating chip is pressed against the leads to melt the solder on the pads and bond the pads together after they are placed together.

この場合普通は1個の加熱用チップにより各辺を順次ボ
ンディングするので所要時間が長く、また押圧と半田を
溶融させる工程が同時に行なわれるためリードがパッド
よりずれてリード間の短絡あるいは接続不良などの不具
合を生ずることがある。
In this case, each side is normally bonded sequentially using a single heating chip, which takes a long time, and since the pressing and solder melting processes are performed at the same time, the leads may shift from the pads, resulting in short circuits or poor connections between the leads. This may cause problems.

本発明はこの次点を改良するために案出されたものであ
る。
The present invention has been devised to improve this second problem.

このため本発明においては、複数連にフラットリードを
有する電子部品を多層配線基板に実装する場合に、該電
子部品の各辺のリードを各辺に夫夫対応する複数個の加
熱用チップにより多層配線基板上のパッドに押圧してお
き、各加熱用チップへの通電制御を行なう制御回路を付
けて加熱用チップを順次通電加熱し、各辺のリードを順
次パッドに接合せしめることを特徴とするものである。
For this reason, in the present invention, when an electronic component having a plurality of flat leads is mounted on a multilayer wiring board, the leads on each side of the electronic component are connected to each other by a plurality of heating chips corresponding to each side in a multilayer wiring board. It is characterized in that it is pressed against a pad on a wiring board, and a control circuit is attached to control the supply of electricity to each heating chip, and the heating chips are successively energized and heated, and the leads on each side are joined to the pads in sequence. It is something.

以下添付図面に基づいて本発明の実施例につき詳細に説
明する。
Embodiments of the present invention will be described in detail below based on the accompanying drawings.

第2図において2はその4辺にフランh l)−ドをも
つ電子部品、1はそのリードである。
In FIG. 2, 2 is an electronic component having flanges on its four sides, and 1 is its lead.

3〜6は夫々独立して動作できる加熱用チップであり第
3図にその1例の斜視図を示す。
Reference numerals 3 to 6 are heating chips that can each operate independently, and FIG. 3 shows a perspective view of one example.

この加熱用チップ3〜6は端子部AよりBに通電するこ
とにより下面γが発熱し半田を溶融することができるよ
うになっている。
The heating chips 3 to 6 are configured so that when current is applied from terminal A to B, the lower surface γ generates heat and melts the solder.

このような加熱用チップ3〜6は電子部品2の各辺のリ
ードに夫々対応して設けられ、夫々リードワイヤ8によ
り制御回路9に接続されている。
Such heating chips 3 to 6 are provided corresponding to the leads on each side of the electronic component 2, and are connected to the control circuit 9 by lead wires 8, respectively.

また制御回路9には電源10が接続さされている。Further, a power source 10 is connected to the control circuit 9.

このように構成された装置による電子部品の実装手順を
次に説明する。
Next, a procedure for mounting electronic components using the apparatus configured as described above will be described.

先ず電子部品2を多層配線基板の所定位置のパッドにそ
のリード1を載せ、各加熱用チップ3〜6により押圧す
る。
First, the leads 1 of the electronic component 2 are placed on pads at predetermined positions on a multilayer wiring board, and the electronic component 2 is pressed by each of the heating chips 3 to 6.

次に制御回路9より第1の加熱用チップ、例えばチップ
3に通電しチップ3を発熱させてパッド上に予め被覆さ
れている半田を溶融せしめた後、通電を止める。
Next, the control circuit 9 supplies power to the first heating chip, for example chip 3, causing the chip 3 to generate heat and melting the solder previously coated on the pads, and then the supply of power is stopped.

次に第2の加熱用チップ、例えばチップ4に通電し、こ
のチップに対応するパッド上の半田を溶融させた後通電
を止め、次の第3の加熱用チップ、例えばチップ5に通
電する。
Next, the second heating chip, for example, chip 4, is energized to melt the solder on the pad corresponding to this chip, and then the energization is stopped, and the next third heating chip, for example, chip 5, is energized.

このように順次各別熱チップに通電することにより各辺
のリードを順次パッドに接合することができる。
By sequentially supplying current to each separate thermal chip in this manner, the leads on each side can be sequentially joined to pads.

以上説明したように本発明方法は従来の如く、各辺のリ
ードを■個の加熱チップで順次接合する場合のようなチ
ップを移動する手数を要しないためその作業能率は向上
する。
As explained above, the method of the present invention improves work efficiency because it does not require the trouble of moving the chips, which is required when the leads on each side are successively joined by two heating chips, as in the conventional method.

また複数個の加熱チップを順次動作させることにより、
不動作中のチップがリードを押圧固定し、パッドとリー
ドの位置ずれを防止することができる。
In addition, by sequentially operating multiple heating chips,
The non-operating chip presses and fixes the leads, thereby preventing the pads and the leads from being misaligned.

なお複数個の加熱チップを同時に通電する場合にはチッ
プ間の漏洩電流により電子部品の素子に損傷を与えるこ
とがあるが順次通電する本発明方法によれはその恐れも
lSい。
Note that when a plurality of heating chips are energized at the same time, the elements of the electronic component may be damaged due to leakage current between the chips, but this risk is eliminated by the method of the present invention in which energization is sequentially applied.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は複数連にフラットリードを有する電子部品の1
例の斜視図、第2図は本発明にかかる実施例の多層配線
基板への電子部品の実装方法の説明図、第3図は加熱用
チップの1例の斜視図である。 1・・・・・・フラットリード、2・・・・・・電子部
品、3〜6・・・・・・加熱用チップ、9・・・・・・
制御回路。
Figure 1 shows an electronic component with multiple flat leads.
FIG. 2 is an explanatory diagram of a method of mounting electronic components on a multilayer wiring board according to an embodiment of the present invention, and FIG. 3 is a perspective view of an example of a heating chip. 1...Flat lead, 2...Electronic component, 3-6...Heating chip, 9...
control circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 複数連にフラットリードを有する電子部品を多層配
線基板に実装する場合に、該電子部品の各辺のリードを
各辺に夫々対応する複数個の加熱用チップにより多層配
線基板上のパッドに押圧しておき、各加熱用チップへの
通電制御を行う制御回路を介して加熱用チップを順次通
電加熱し、各辺のリードを順次パッドに接合ぜしめるこ
とを特徴とする多層配線基板への部品実装方法。
1 When mounting an electronic component having multiple series of flat leads on a multilayer wiring board, the leads on each side of the electronic component are pressed against the pads on the multilayer wiring board by a plurality of heating chips corresponding to each side. A component for a multilayer wiring board, characterized in that the heating chips are heated in sequence through a control circuit that controls energization to each heating chip, and the leads on each side are sequentially bonded to pads. How to implement.
JP53126079A 1978-10-16 1978-10-16 How to mount components on a multilayer wiring board Expired JPS5841679B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53126079A JPS5841679B2 (en) 1978-10-16 1978-10-16 How to mount components on a multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53126079A JPS5841679B2 (en) 1978-10-16 1978-10-16 How to mount components on a multilayer wiring board

Publications (2)

Publication Number Publication Date
JPS5553486A JPS5553486A (en) 1980-04-18
JPS5841679B2 true JPS5841679B2 (en) 1983-09-13

Family

ID=14926083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53126079A Expired JPS5841679B2 (en) 1978-10-16 1978-10-16 How to mount components on a multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS5841679B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339707U (en) * 1976-09-08 1978-04-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339707U (en) * 1976-09-08 1978-04-06

Also Published As

Publication number Publication date
JPS5553486A (en) 1980-04-18

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