JPS63284890A - Mounting method of electronic part - Google Patents
Mounting method of electronic partInfo
- Publication number
- JPS63284890A JPS63284890A JP11881687A JP11881687A JPS63284890A JP S63284890 A JPS63284890 A JP S63284890A JP 11881687 A JP11881687 A JP 11881687A JP 11881687 A JP11881687 A JP 11881687A JP S63284890 A JPS63284890 A JP S63284890A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- printed wiring
- electronic part
- electronic component
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 239000000758 substrate Substances 0.000 abstract description 6
- 239000011888 foil Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は１本体部の端面及び下面に多数の面付実装用リ
ード及び支持パターンをそれぞれ有する電子部品（半導
体ＩＣ）を印刷配線基板に実装する方法に関するもので
ある。Detailed Description of the Invention [Field of Industrial Application] The present invention is a method for mounting an electronic component (semiconductor IC) on a printed wiring board, which has a large number of leads and support patterns for surface mounting on the end surface and bottom surface of one main body, respectively. It's about how to do it.
従来、本体部の端面に多数の面付実装用接続端子を有す
る電子部品を、印刷配線基板に実装する場合には、例え
ば特公昭６０−５８６００号公報に記載されているよう
に、電子部品の接続端子と印刷配線基板上の導電箔とを
半田を介して接合することにより、電子部品と印刷配線
基板とを一体に結合していた。Conventionally, when mounting an electronic component having a large number of connection terminals for surface mounting on the end face of the main body on a printed wiring board, for example, as described in Japanese Patent Publication No. 60-58600, The electronic component and the printed wiring board have been integrally bonded by joining the connecting terminals and the conductive foil on the printed wiring board via solder.
上記従来例では、電子部品の接続端子と印刷配線基板の
導電箔とを半田を介して接合することにより、印刷配線
基板の表裏両面に電子部品をそれぞれ実装する場合、前
記一方面（例えば裏面）に電子部品を実装する際に、先
に前記他方面（例えば表面）に実装した電子部品の半田
が再溶融するため、該表面の電子部品はは（離して落下
するという問題があった。In the above conventional example, when mounting electronic components on both the front and back surfaces of the printed wiring board by joining the connection terminals of the electronic components and the conductive foil of the printed wiring board through solder, the one side (for example, the back side) When electronic components are mounted on the other surface, the solder of the electronic components mounted on the other surface (for example, the front surface) is remelted, which causes the electronic components on the surface to separate and fall.
本発明は、印刷配線基板の裏面（又は表面）に電子部品
を実装する場合に、先に該基板の表面（又は裏面）に実
装した別個の電子部品が、その接合半田の再溶融により
、印刷配線基板からはくして落下するのを防止すること
ができる電子部品の実装方法を提供することを目的とす
る。In the present invention, when electronic components are mounted on the back surface (or front surface) of a printed wiring board, the separate electronic components previously mounted on the front surface (or back surface) of the printed circuit board are printed by remelting the bonding solder. It is an object of the present invention to provide a method for mounting electronic components that can prevent them from peeling off and falling from a wiring board.
上記問題点は、電子部品の端面に取付けた面付実装用リ
ード及び該電子部品に設けた支持パターンに、印刷配線
基板上に設けたリードパターン及び保持パターンをそれ
ぞれ対向させ、該対向部を半田を介して接合することに
より、前記電子部品と印刷配線基板を一体化することに
より解決される。The above problem is solved by making the lead pattern and holding pattern provided on the printed wiring board face each other to the surface mounting lead attached to the end face of the electronic component and the support pattern provided on the electronic component, and then soldering the opposing parts. This problem can be solved by integrating the electronic component and the printed wiring board by bonding the electronic component and the printed wiring board together.
電子部品の端面及び下面にそれぞれ設げたリード及支持
パターンと、これらに対向するように印刷配線基板に設
けたリードパターン及び保持パターンを半田により接合
して一体化する。この際、半田の表面張力は、再リフロ
一時に電子部品がはく離しない所定の力となるため、作
業中に電子部品が落下する恐はない。The lead and support patterns provided on the end and lower surfaces of the electronic component, respectively, and the lead and support patterns provided on the printed wiring board so as to face these are joined by solder and integrated. At this time, the surface tension of the solder becomes a predetermined force that will not cause the electronic components to peel off during reflow, so there is no fear that the electronic components will fall during the work.
以下、本発明の一実施例を図面について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、電子部品（以下、半導体と称す）１は
、その本体部の両端面に実装兼電気接続をつかさどる２
状のリード２が多数段けられ、かつ本体部下面に支持パ
ターン７が設けられている。In FIG. 1, an electronic component (hereinafter referred to as a semiconductor) 1 has two parts on both end faces of its main body that are responsible for mounting and electrical connection.
A large number of shaped leads 2 are arranged in stages, and a support pattern 7 is provided on the lower surface of the main body.
印刷配線基板３は、その表裏両面上の前記リード２及び
支持パターン７に対向する位置に、リードパターン４及
び保持パターン６をそれぞれ設けた構成からなる。The printed wiring board 3 has a structure in which lead patterns 4 and holding patterns 6 are respectively provided at positions facing the leads 2 and support patterns 7 on both the front and back surfaces thereof.
上記リードパターン４及び保持パターン６上に半田ペス
ートを印刷で施した後に、該パターン４゜６に対向して
半導体１のリード２及び支持パターン７を配置し、印刷
配線基板３上に半導体１を搭載する。ついで、リフロー
を行って半田５により半導体１と印刷配線基板３を接合
して一体に結合する。After printing a solder paste on the lead pattern 4 and holding pattern 6, the leads 2 and support pattern 7 of the semiconductor 1 are placed facing the pattern 4°6, and the semiconductor 1 is placed on the printed wiring board 3. Mount. Then, reflow is performed to join the semiconductor 1 and the printed wiring board 3 with the solder 5 to integrally bond them.
この場合、上記リード２とリードパターン４の接合部及
び支持パターン７と保持パターン６の接合部の綜合接合
面積は、半田５の溶融状態において半導体１の自重の３
倍以上の表面張力を発生するように設定されている。In this case, the combined joint area of the joint between the lead 2 and the lead pattern 4 and the joint between the support pattern 7 and the holding pattern 6 is 3 of the dead weight of the semiconductor 1 when the solder 5 is in a molten state.
It is set to generate a surface tension that is more than twice as strong.
次に第２図に示すように印刷配線基板３の裏面又は表面
に、別個の半導体８を半田５及び接続パターン９を介し
てリフローなどにより半田付けする。このように別個の
半導体８を実装するために、リフロー例えばペーパーリ
フロー炉を通しても、印刷配線基板３上の半導体１を固
定する半田５の表面張力により、半導体１は保持されて
いるから、はく離して落下する恐れがない。その理由を
次に詳述する。Next, as shown in FIG. 2, a separate semiconductor 8 is soldered to the back or front surface of the printed wiring board 3 via the solder 5 and the connection pattern 9 by reflow or the like. In order to mount the separate semiconductors 8 in this way, even when the semiconductors 1 are passed through a reflow oven, for example, in a paper reflow oven, the semiconductors 1 are held by the surface tension of the solder 5 that fixes the semiconductors 1 on the printed wiring board 3, so that they cannot be peeled off. There is no risk of it falling. The reason for this will be explained in detail below.
前述したように半導体１は、リード２、半田５及びリー
ドパターン４を介して印刷配線基板３に実装兼電気接続
されると共に、本体部の支持パターン７、半田５及び保
持パターン６を介して印刷配線基板３に固定されている
。前記半田５の表面張力は、下記（１）式で示され、再
リフロ一時には半導体１がはく離して落下するのを防ぐ
作用をする。As described above, the semiconductor 1 is mounted and electrically connected to the printed wiring board 3 via the leads 2, solder 5, and lead pattern 4, and is also printed via the support pattern 7, solder 5, and holding pattern 6 of the main body. It is fixed to the wiring board 3. The surface tension of the solder 5 is expressed by the following equation (1), and acts to prevent the semiconductor 1 from peeling off and falling during reflow.
ただし、Ｔｇ：表面張力（ｇｒ）、ｔ：半田の周囲長（
ｃＷｌ）、を二重力加速度（創／−２）、ｆ３：溶融半
田の表面張力（ａｙｎｅ／ｃｍ）実験の結果によると、
安全率（＝半田の表面張力／電子部品の重量）が３以上
であれば１作業中に半導体１がはく離して落下するのを
防止することが可能である。However, Tg: surface tension (gr), t: circumferential length of solder (
cWl), double force acceleration (wound/-2), f3: surface tension of molten solder (ayne/cm) According to the experimental results,
If the safety factor (=surface tension of solder/weight of electronic component) is 3 or more, it is possible to prevent the semiconductor 1 from peeling off and falling during one operation.
例えば、Ｓ ＯＰ （Ｓｍａｌｌ ０ｕｔ−１ｉｎｅ
Ｐａｃｋａｇｅ）型１４ビンＩＣの重量は（Ｌ ２ ｇ
ｒである。そこで。For example, S OP (Small 0ut-1ine
The weight of the 14-bin IC (Package) type is (L 2 g
It is r. Therefore.
安全率を３に設定すると、半田溶融温度２５５℃では半
田の表面張力がａ６ｇｒとなり、かつ、半田の周囲長さ
は１２■となる。又前記ＳＯＰ屋ＩＣのモールドの本体
部は、幅５．５■×長さ１０■である。これらより該本
体部ＫＡ８■φの半田接合部を設ければ、前記ＳＯ２型
ＩＣが再リフロ一時にはく離して落下するのを防止でき
る。If the safety factor is set to 3, the surface tension of the solder will be a6gr at the solder melting temperature of 255°C, and the circumferential length of the solder will be 12cm. The main body of the mold of the SOP shop IC has a width of 5.5 cm and a length of 10 cm. By providing a solder joint of the main body part KA8■φ from these, it is possible to prevent the SO2 type IC from peeling off and falling during reflow.
以上説明したように１本発明によれば、印刷配線基板の
表裏両面に電子部品を実装する場合、該基板の一面に電
子部品を後から実装するに際し、該基板の他面に先に実
装した別個の電子部品が、その接合半田の再溶融により
、該基板からはく離して落下する従来の欠点を除去する
ことができる。As explained above, according to one aspect of the present invention, when electronic components are mounted on both the front and back surfaces of a printed wiring board, when electronic components are later mounted on one side of the board, the electronic parts are mounted on the other side of the board first. The conventional drawback of separate electronic components being separated from the substrate and falling due to remelting of their bonding solder can be eliminated.
又、電子部品の本体部を半田により印刷配線基板に実装
したため、加熱時に熱膨張係数差による高さ方向の熱ス
トレスを発生しないので、電子部品が破損するのを防止
することができる。Furthermore, since the main body of the electronic component is mounted on the printed wiring board by soldering, thermal stress in the height direction due to the difference in thermal expansion coefficient is not generated during heating, so it is possible to prevent the electronic component from being damaged.
第１図は本発明の一実施例を示す斜視図、第２図は本発
明の別の実施例を示す正面図である。
符号の説明
１．８・・・・・・電子部品、２・・・・・・リード、
３・・・・・・印刷配線基板、４・・・・・・リードパ
ターン、５・・・・・・半田、６・・・・・・保持ハタ
ーン、７・・・・・・支持パターン。
代理人 弁理士 小川勝男 ゛
、−ノ
３−２１西乙緯、蒸ヰｔ ６ Ｑま弁バプーン
ｑ 撞本先パターン」２図FIG. 1 is a perspective view showing one embodiment of the invention, and FIG. 2 is a front view showing another embodiment of the invention. Explanation of symbols 1.8...Electronic component, 2...Lead,
3...Printed wiring board, 4...Lead pattern, 5...Solder, 6...Holding pattern, 7...Support pattern. Agent Patent Attorney Katsuo Ogawa ゛、-3-21 Nishi Otsuki, Steam 6 Q Maben Bapoon
q. Book tip pattern” 2
Claims (2)
該電子部品の下面に設けた支持パターンに、印刷配線基
板上に設けたリードパターン及び保持パターンをそれぞ
れ対向させ、該対向部を半田を介して接合することによ
り、前記電子部品と印刷配線基板を一体化することを特
徴とする電子部品の実装方法。(1) The surface mounting lead attached to the end face of the electronic component and the support pattern provided on the bottom surface of the electronic component are opposed to the lead pattern and holding pattern provided on the printed wiring board, respectively, and the opposing parts are soldered. A method for mounting an electronic component, characterized in that the electronic component and the printed wiring board are integrated by bonding via a .
半田の溶融状態において電子部品の自重の３倍以上の表
面張力を発生するこうに設定したことを特徴とする特許
請求の範囲第１項記載の電子部品の実装方法。(2) The area of the joint between the electronic component and the printed wiring board is
2. The method of mounting an electronic component according to claim 1, wherein the solder is set to generate a surface tension three times or more greater than the weight of the electronic component when the solder is in a molten state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881687A JPS63284890A (en) | 1987-05-18 | 1987-05-18 | Mounting method of electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881687A JPS63284890A (en) | 1987-05-18 | 1987-05-18 | Mounting method of electronic part |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63284890A true JPS63284890A (en) | 1988-11-22 |
Family
ID=14745848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11881687A Pending JPS63284890A (en) | 1987-05-18 | 1987-05-18 | Mounting method of electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63284890A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5169056A (en) * | 1992-02-21 | 1992-12-08 | Eastman Kodak Company | Connecting of semiconductor chips to circuit substrates |
| EP0656741A2 (en) * | 1993-12-01 | 1995-06-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
| FR2724054A1 (en) * | 1994-06-09 | 1996-03-01 | Samsung Electronics Co Ltd | SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE |
| EP0835047A3 (en) * | 1996-10-02 | 1999-12-01 | Matsushita Electric Industrial Co., Ltd. | RF-driven semiconductor device |
-
1987
- 1987-05-18 JP JP11881687A patent/JPS63284890A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5169056A (en) * | 1992-02-21 | 1992-12-08 | Eastman Kodak Company | Connecting of semiconductor chips to circuit substrates |
| EP0656741A2 (en) * | 1993-12-01 | 1995-06-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor package |
| EP0656741A3 (en) * | 1993-12-01 | 1996-08-28 | Mitsubishi Electric Corp | Semiconductor package. |
| FR2724054A1 (en) * | 1994-06-09 | 1996-03-01 | Samsung Electronics Co Ltd | SEMICONDUCTOR PACKAGE MOUNTING STRUCTURE |
| EP0835047A3 (en) * | 1996-10-02 | 1999-12-01 | Matsushita Electric Industrial Co., Ltd. | RF-driven semiconductor device |
| US6046501A (en) * | 1996-10-02 | 2000-04-04 | Matsushita Electric Industrial Co., Ltd. | RF-driven semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR910007103B1 (en) | Cast solder leads for leadless semiconductor circuits | |
| JPS63284890A (en) | Mounting method of electronic part | |
| JP3813767B2 (en) | Resin wiring board and manufacturing method thereof | |
| JPS617692A (en) | Method of securing conductor pin and printed circuit board secured with conductor pin | |
| JPH07114216B2 (en) | Method of mounting film carrier type semiconductor device | |
| JPS63213936A (en) | Manufacture of hybrid integrated circuit device | |
| JP2827965B2 (en) | Ball grid array mounting method | |
| JPH08340164A (en) | Surface mounting structure of bga type package | |
| JPS63283001A (en) | Chip electronic component | |
| JPS59188996A (en) | Method of mounting electronic part | |
| JPS634690A (en) | Thick film hybrid integrated circuit substrate | |
| JPH04164358A (en) | Thick film printed board provided with i/o pins | |
| JPS6262533A (en) | High-density mounting method for semiconductor element | |
| JPH1012992A (en) | Mounting method and electronic component housing pallet | |
| JP2755087B2 (en) | Removable jig | |
| JPS63211655A (en) | Solder-buried resist sheet | |
| JPS61263191A (en) | Mounting of electronic component | |
| JPH04368196A (en) | Printed substrate | |
| JPH01191491A (en) | Multiple circuit board | |
| JP2642175B2 (en) | Soldering mounting method of electronic components to the substrate | |
| JPS62260393A (en) | Double-sided printed wiring board | |
| JPH0294591A (en) | Printed wiring board | |
| JPS594061A (en) | Semiconductor device | |
| JPS6355189B2 (en) | ||
| JPH01286384A (en) | Mounting structure for package |