JPS5837917A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5837917A
JPS5837917A JP56136677A JP13667781A JPS5837917A JP S5837917 A JPS5837917 A JP S5837917A JP 56136677 A JP56136677 A JP 56136677A JP 13667781 A JP13667781 A JP 13667781A JP S5837917 A JPS5837917 A JP S5837917A
Authority
JP
Japan
Prior art keywords
region
impurity density
parts
energy beam
singlecrystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56136677A
Other languages
Japanese (ja)
Other versions
JPH0136244B2 (en
Inventor
Seiichiro Kawamura
河村 誠一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56136677A priority Critical patent/JPS5837917A/en
Publication of JPS5837917A publication Critical patent/JPS5837917A/en
Publication of JPH0136244B2 publication Critical patent/JPH0136244B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve singlecrystallization by crystallizing a non-singlecrystal Si in a well-controlled manner after being subjected to the energy beam irradiation through the use of the crystallizing temperature difference in terms of the impurity density. CONSTITUTION:A non-singlecrystal semiconductor (a polycrystalline Si for instance) 4 is formed via an insulating film (a gate oxide film here) 3 on a substrate 1, and this non-singlecrystal semiconductor 4 is single-crystallized by enlarging its crystal grains by means of the energy beam irradiation. In that case the impurity density in the non-singlecrystal semiconductor region 4 is made partially varied beforehand. For instance, ions are implanted by using an SiO2 film 5 as a mask so that the impurity density at the peripheral parts of the region 4 is made higher than that of the center parts. Because of this, crystallization after the energy beam irradiation starts from the low impurity density parts at the center and proceeds to the higher density parts, thereby enlarging crystal grains.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特に非単結晶シリコン
の結晶粒の拡大成いは単結晶化方法に関す。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for enlarging crystal grains of non-single crystal silicon or for single crystallizing it.

半導体装置の展進工程において、非単結晶シリコンすな
わち多結晶シリコン或いは非晶質シリコンにエネルギ線
すなわち光或いは電子線等のビームを照射することによ
υ、その結晶粒を拡大し或いはある領域を形成する非単
結晶シリコンを単結晶シリコンとすることが行われてい
る。
In the development process of semiconductor devices, non-single crystal silicon, polycrystalline silicon, or amorphous silicon is irradiated with an energy beam, that is, a beam of light or an electron beam, to enlarge its crystal grains or to expand a certain region. The non-single-crystal silicon to be formed is made into single-crystal silicon.

この場合において、各非単結晶シリコン領域に関して、
一般的にはその中央部分に比較してその周辺部が低温と
なり、融解後の結晶化は周辺部よシ開始され易く、結晶
粒の拡大あるいは単結晶化の目的達成のためには何等か
の処置が必要とされるO この目的達成のために(例えば元ビーム照射による単結
晶化に対して目的とする非単結晶領域の中央部分の当該
光ビームの反射率をその周辺部分より高くすることによ
り、中央部分の温度をその周辺部分に比較して低温とし
、中央部分が結晶化温度に最初に到達して、ここより周
辺に向って結晶化が進み、単結晶化が達成される方法、
或いは任意のエネルギ線照射による単結晶化に対して、
目的とする非単結晶傾城の中央部分とその基板下面との
間の熱抵抗を、咳非単結晶領域のその他の部分とその基
板下爾との間の熱抵抗よシ低くすることによシ、中央部
分より周辺に向って結晶化を進める方法等が提案されて
いる。
In this case, for each non-single crystal silicon region,
In general, the temperature at the periphery is lower than that at the center, and crystallization after melting is more likely to start from the periphery. Measures are required to achieve this objective (e.g., for single crystallization by original beam irradiation, the reflectance of the light beam in the central part of the target non-single crystal region is higher than that in the surrounding parts) A method in which the temperature of the central part is lower than that of the surrounding part, the central part reaches the crystallization temperature first, and the crystallization progresses from here toward the periphery to achieve single crystallization,
Or for single crystallization by irradiation with arbitrary energy beams,
By making the thermal resistance between the central part of the target non-single crystal inclined wall and the bottom surface of the substrate lower than the thermal resistance between the other parts of the non-single crystal region and the bottom surface of the substrate. , a method of proceeding crystallization from the center toward the periphery has been proposed.

しかしながら前記方法は、光学し干渉を応用する薄膜の
厚さの精密な制御が必要モされ、或いは目的とする半導
体装置の構造によ)てその適用が制限される場合がある
などの制約C受けている。
However, the above method is subject to limitations such as requiring precise control of the thickness of the thin film for which optical interference is applied, or its application may be limited depending on the structure of the target semiconductor device. ing.

本発明は、エネルギ線照射に15非単結晶シリコンの結
晶粒の拡大成いは単結晶比を、半導体装置製造方法とし
て習熟し、かつ広く適用可能な方法によって達成するこ
とを目的とする。
An object of the present invention is to achieve the expansion of the crystal grains of non-single-crystalline silicon by energy beam irradiation, or to increase the single-crystal ratio by a method that is familiar to and widely applicable to semiconductor device manufacturing methods.

本発明の前記目的は、非単結晶シIJ 3ン領域内で部
分的に不純物の濃度を変化せしめる、例えば該領域の周
辺部の不純物の濃度をその中央部分よシ高くすることに
よシ、不純物濃度の高い部分が不純物濃度の低い部分よ
り結晶化温度が低いために、エネルギ線照射後の結晶化
が不純物濃度の低い部分から開始されて不純物濃度の高
い部分に進行することにより達成される。
The object of the present invention is to partially change the impurity concentration within the non-single crystal silicon region, for example, by making the impurity concentration in the peripheral part of the region higher than in the central part. Since the crystallization temperature in the areas with high impurity concentration is lower than in the areas with low impurity concentration, crystallization after irradiation with energy beams is achieved by starting from the areas with low impurity concentration and progressing to the areas with high impurity concentration. .

以下、本発明を実施例により図面を用いて具体的に説明
する。
Hereinafter, the present invention will be specifically explained using examples and drawings.

最初に#I、1図にシリコンに不純物として砒素(As
)を注入したときの不純物濃度に対する結晶化温度を示
す。第1図に示す如く、結晶化温度はAs 1lJW4
 x 10 t′/cdにおいて1410 ′cf4 
V テあるのに対し、A8濃度1.5 X 10!l 
/dにおりて1300℃程変であって、更にA+s濃度
を増加すれば共晶温度1073℃に接近する。
First #I, Figure 1 shows arsenic (As) as an impurity in silicon.
) is shown as a function of the impurity concentration and the crystallization temperature when implanted. As shown in Figure 1, the crystallization temperature is As 1lJW4
1410'cf4 at x 10 t'/cd
While there is V Te, A8 density is 1.5 x 10! l
/d, it changes by about 1300°C, and if the A+s concentration is further increased, it approaches the eutectic temperature of 1073°C.

この不純物濃度による結晶化温冷の差を応用した、Sl
ゲー)MO3型電界効果トランジスタ(以下MO8FE
Tと称する)のゲートを構成する多結晶シリコンの結晶
粒拡大の実施例を説明する。
By applying this difference in crystallization temperature and cooling due to impurity concentration,
MO3 type field effect transistor (hereinafter referred to as MO8FE)
An example of enlarging the crystal grains of polycrystalline silicon constituting the gate (referred to as T) will be described.

第2図は本実施例の断面図であって、P型シリコン基板
1上に熱酸化法によりフィールド絶縁膜2を選択的に形
成し、次にゲート酸化膜3を厚さ約40−に形成し、(
にモノシラン(SiH,)の600乃至700 ℃にお
ける熱分解法により多結晶シリコン膜4を厚さ約500
 m−ic影形成る。続いて同じくモノシランによる化
学蒸着法にょヤニ酸化シリコン(810g)膜5を厚さ
約150%mに積層形成し九後、二酸化シリコン膜5及
び多結晶シリフン膜4を選択的に除去してゲート電極を
形成する。然る後にゲート電極上の二酸化シリコンM5
の全周辺の幅10μSの部分を第3図に示す如く選択的
に除去する。
FIG. 2 is a cross-sectional view of this embodiment, in which a field insulating film 2 is selectively formed on a P-type silicon substrate 1 by thermal oxidation, and then a gate oxide film 3 is formed to a thickness of approximately 40 mm. death,(
A polycrystalline silicon film 4 is formed to a thickness of approximately 500° C. by thermal decomposition of monosilane (SiH) at 600 to 700° C.
m-ic shadow formation. Next, a silicon oxide (810 g) film 5 is formed by chemical vapor deposition using monosilane to a thickness of about 150%. After that, the silicon dioxide film 5 and the polycrystalline silicon film 4 are selectively removed to form a gate electrode. form. After that, silicon dioxide M5 on the gate electrode
As shown in FIG. 3, a portion having a width of 10 .mu.S around the entire periphery is selectively removed.

次にAs+イオンを120KeVにてxx1016/c
11のドーズ量にイオン注入を行った後、15Wの連続
波にレーザの光束直径を約50μ■とじ、走査速度を約
10aa/secとして、予め温度500℃に加温され
た前期基板に照射することにより加熱処理を実施した。
Next, As+ ions were applied to xx1016/c at 120KeV.
After performing ion implantation at a dose of 11, irradiate the substrate pre-heated to 500°C with a 15W continuous wave laser beam diameter of about 50μ and a scanning speed of about 10aa/sec. Heat treatment was carried out by this.

この結果として、ゲート電極を形成する多結晶シリコン
の結晶粒は、前記加熱処理前においてそのサイズが数十
nmでありだのに対して、加熱処理後においては数十乃
至数^mと大幅に拡大され、また比抵抗値は数tooh
m/jlを得た。
As a result, the size of the polycrystalline silicon crystal grains forming the gate electrode is several tens of nanometers before the heat treatment, but after the heat treatment, the size significantly increases to several tens to several meters. expanded, and the resistivity value is several too
m/jl was obtained.

前記実施例の他、例えば表面が絶縁物よりなる基板上に
島状に分離された半導体素子を形成するS I O(8
111con On In5ulatinf、mubg
trate)構造の半導体装置の製造工程において、絶
縁基板面上の非単結晶シリコンよりなる島状に分離され
た領域をエネルギ線照射によシ単結晶化する場合にも、
本発明を全く同様に実施することが可能である。
In addition to the above-mentioned embodiments, for example, an SIO (8
111con On In5ulatinf, mubg
In the manufacturing process of a semiconductor device with a trate) structure, when island-like isolated regions made of non-single crystal silicon on an insulating substrate surface are made into single crystals by irradiation with energy beams,
It is possible to implement the invention in exactly the same way.

この場合において、形成された単結晶シリコン領域の周
辺部における不純物が不都合であるならば、当該部分を
選択的に除去し、或いは酸化物等の絶縁物とすることに
より問題を解決することが可能である。
In this case, if impurities in the peripheral area of the formed single crystal silicon region are inconvenient, the problem can be solved by selectively removing the area or using an insulator such as oxide. It is.

結晶粒の拡大成いは単結晶化を行なう領域の幅が照射す
るビームの直径とほぼ等しい場合には、領域の両端に沿
って不純物濃度を高めることによって、照射するビーム
のエネルギ分布をサドル(Saddl・)型としたと同
様な効果が得られる。一般に目的とする領域のパターン
が長方形である場合には、その長辺方向にエネルギ線を
走査することが望ましい、 更に本発明の効果を再現性よく精密に求める場合には、
目的とする非単結晶領域の周辺或いは両端から中央に向
って不純物濃度を段階的に、或いは連続的に変化させて
注入すれば好ましい結果が得られる。
When the width of the region to be single-crystallized is approximately equal to the diameter of the irradiating beam, grain expansion is achieved by increasing the impurity concentration along both edges of the region to saddle the energy distribution of the irradiating beam. A similar effect can be obtained by using the Saddl.) type. Generally, when the pattern of the target area is rectangular, it is desirable to scan the energy beam in the long side direction of the rectangle.
Favorable results can be obtained if the impurity concentration is varied stepwise or continuously from the periphery or both ends of the target non-single crystal region toward the center.

本発明は以上説明した如く、エネルギ線照射によシ非単
結晶シリコンの結晶粒を拡大し、或いはエネルギ綾照射
後の結晶化が不純物a度の低い部分から開始されて不純
物濃度の高い部分に進行せしめることにより、確実にそ
の目的を達成するものである。
As explained above, the present invention expands crystal grains of non-single crystal silicon by energy irradiation, or crystallization after energy irradiation starts from a region with a low impurity concentration and moves to a region with a high impurity concentration. By making progress, the goal will definitely be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は不純物源Flχによる結晶化温度の変化の一例
を示す図、第2図は本発明の実施例を示す断面図、済3
図は本発明の実施例を示す平面図である。 図において、1は基板、2はフィールド絶縁膜、3はゲ
ート酸化膜、4は多結晶シリコン膜、5は二酸化シリコ
ン膜を示す。
FIG. 1 is a diagram showing an example of a change in crystallization temperature due to an impurity source Flχ, and FIG. 2 is a cross-sectional view showing an embodiment of the present invention.
The figure is a plan view showing an embodiment of the present invention. In the figure, 1 is a substrate, 2 is a field insulating film, 3 is a gate oxide film, 4 is a polycrystalline silicon film, and 5 is a silicon dioxide film.

Claims (1)

【特許請求の範囲】[Claims] 基板上に非単結晶半導体よりなる領域を形成し、エネル
ギ線の照射により該非単結晶半導体を融解し結晶化せし
めて、結晶粒を拡大し、或いは該領域を単結晶とする半
導体装置の製造方法において、該非単結晶半導体領琥内
の不純物の濃度を部分的に変化せしめておいて、前記エ
ネルギ線の照射を行うことを特徴とする半導体装置の製
造方法。
A method for manufacturing a semiconductor device in which a region made of a non-single crystal semiconductor is formed on a substrate, and the non-single crystal semiconductor is melted and crystallized by irradiation with energy beams to enlarge crystal grains or to make the region a single crystal. A method of manufacturing a semiconductor device, characterized in that the irradiation with the energy beam is performed while partially changing the concentration of impurities in the non-single crystal semiconductor region.
JP56136677A 1981-08-31 1981-08-31 Manufacture of semiconductor device Granted JPS5837917A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56136677A JPS5837917A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56136677A JPS5837917A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5837917A true JPS5837917A (en) 1983-03-05
JPH0136244B2 JPH0136244B2 (en) 1989-07-31

Family

ID=15180889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56136677A Granted JPS5837917A (en) 1981-08-31 1981-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5837917A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4947630A (en) * 1972-06-05 1974-05-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4947630A (en) * 1972-06-05 1974-05-08

Also Published As

Publication number Publication date
JPH0136244B2 (en) 1989-07-31

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