JPS5837697B2 - MIS - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor IC (integrated circuit device), and mainly relates to a MIS type semiconductor IC (integrated circuit device) used in a clock oscillator.
The target is

P-channel MO on the same semiconductor substrate as a clock oscillator
S field effect transistor (FET) and n-channel MO
There is a so-called complementary MOS semiconductor IC of the type in which SFET is formed.

In order to achieve stable oscillation in such an electronic circuit device, a high-resistance element is required to short-circuit the input side and output side for direct current and insulate them for alternating current. There is an idea to increase the degree of integration by forming it on one semiconductor substrate together with a bimentary MOS/IC.

A specific method is to use a MOS type FET made by doping a portion of a semiconductor substrate with an impurity having a conductivity type opposite to that of the substrate as the above-mentioned high-resistance body.

However, the resistance value of the resistor of such a MOS FET depends on the voltage and is capacitively coupled to the semiconductor substrate, resulting in fluctuations in the oscillation frequency, changes in the operating range of the circuit, and The inventor of the present application has revealed that this reduces the precision of a clock.

Therefore, the inventor of this application considered forming a resistor through an insulating film on the surface of a MOS IC, but if the resistor was formed by diffusing impurities into a silicon film, the resistance value would be low and uneven. Since the resistance value is large, we came up with the idea of increasing the precision of the resistance value by ion-implanting impurities into the silicon film.

The present invention was born as a result of such a process, and one of its purposes is to make it possible to produce a high-resistance element without significantly changing the manufacturing process of MOS type semiconductor devices. Another purpose is to improve the electrical properties of high-resistance materials.

The gist of the present invention for achieving the above object is to provide a thick insulating film in a portion of the main surface of a semiconductor substrate where a resistance region is provided, and a gate thinner than the thick insulating film in a portion of the main surface where a gate of an MIS type transistor is provided. a step of forming an insulating film, a step of forming a polycrystalline silicon layer on the thick insulating film and a gate insulating film, and introducing an impurity for adjusting a resistance value into the polycrystalline silicon layer; a step of selectively removing the polycrystalline silicon layer and forming a polycrystalline silicon layer for a resistance region on the thick insulating film and a polycrystalline silicon layer for a gate electrode on the gate insulating film; A second polycrystalline silicon layer
Using the polycrystalline silicon layer for gate electrode as a mask, impurities are introduced into the semiconductor substrate on both sides of the polycrystalline silicon layer for gate electrode in order to form a source and a drain/region. A method of manufacturing an MIS type semiconductor integrated circuit device includes a step of introducing impurities into a polycrystalline silicon layer for a gate electrode.

The present invention will be explained below with reference to Examples.

FIG. 1 shows an embodiment of the present invention in the order of steps.

(a) An acceptor such as boron is selectively diffused into an n-type semiconductor substrate 1 to form an n-channel MOSFET operating region 2.

(b) Next, a Si02 film 3 is formed on the entire surface of the semiconductor substrate 1, and then the portions corresponding to the source, drain, and gate of each MOSFET are selectively removed, and the surface of the substrate 1 is further heated and oxidized to a thin layer. Then, a Si02 film 4 for forming a gate insulating film is formed.

(c) A polycrystalline silicon layer 5 is formed on the Si02 films 3 and 4.

The silicon layer is then implanted with conductive ions to cause the substantially insulating silicon layer to have a resistivity.

(a) By selectively etching the polycrystalline silicon layer 5, a silicon gate electrode 6 and a high resistance film 7 are formed.
to expose the source and drain regions on the semiconductor surface.

(e) Si0 is deposited on the surface of the semiconductor substrate 1 by vapor phase growth.
2 film 3, Si02 film p-channel MOSFE
Only the portion covering the T element portion is selectively removed to expose the source and drain portions of the element.

Then, using the partially formed Si02 film as a mask, an acceptor such as boron is diffused into the semiconductor surface to form source 8 and drain region 9 of the p-channel MOSFET.

(f) Next, the high-resistance film 7 and the p-channel M
OSFET is covered with Si02 film, and n-channel MOS
Only the source and drain parts of the FET part are exposed.

Then, using the partially formed Si02 film as a mask, a donor such as phosphorus is diffused onto the semiconductor surface to form an n-channel MOS.
A source 10 and drain region 11 of the FET are formed to create a complementary MOSIC with a high resistance film 7.

Note that the annealing treatment after ion implantation is a heat treatment for diffusion, specifically, in the case of boron diffusion, annealing treatment at 1050 ° C.
0 minutes, 7 minutes at 1100℃, 2 minutes at 1100℃ for phosphorus
Since the heat treatment is performed at 1050° C. for 10 minutes, no special process is required.

This example utilizes the fact that silicon to which no impurities are added is substantially an insulator and can be made to have any resistance by doping with impurities using the ion implantation method. At least the silicon film is masked during diffusion so that the resistance value of the main resistor does not change due to source and drain diffusion.

According to this embodiment, since the resistor is formed on the same substrate as the complementary MOSFET, not only high integration of the IC is possible, but also the resistor is insulated from the silicon semiconductor substrate. Because there is, MOS
The circuit operates much more stably than in conventional cases due to the fact that leakage current does not flow as in the case of resistors with type FET structure, there is no capacitive coupling with the semiconductor substrate, and the resistance value does not depend on voltage. be able to.

Furthermore, since a high resistance film is formed by doping silicon with impurities by ion implantation, the resistance value can be higher and more precise than when using diffusion.

Furthermore, since the annealing treatment required after ion implantation can be performed by heat treatment for diffusion, there is no need for a special annealing treatment process and the process does not become complicated. Regardless of the method, the resistance value of the resistor can be made highly accurate by the ion implantation method, and the circuit can be operated accurately and stably.

The present invention can be widely applied to MIS type semiconductor devices having resistors.

[Brief explanation of drawings]

FIGS. 1a to 1f are cross-sectional views of an IC device showing embodiments of the present invention in the order of steps. 1... N-type semiconductor substrate, 2... P-type semiconductor region for n-channel MOSFET type, 3...
...Si02 film, 4...Si02 for gate insulation
Film, 5... Polycrystalline silicon layer, 6...
Silicon gate electrode, 7...Resistor, 8-11
...source or drain.

Claims (1)

[Claims] 1. Forming a thick insulating film on a portion of the main surface of the semiconductor substrate where a resistance region is to be provided and a gate insulating film thinner than the thick insulating film on a portion of the main surface where a gate of an MIS type transistor is to be provided, the thick insulating film and A step of forming a polycrystalline silicon layer on the gate insulating film and introducing a resistance adjustment impurity into the polycrystalline silicon layer, selectively removing the polycrystalline silicon layer into which the resistance adjustment impurity has been introduced, and performing the above steps. A step of forming a polycrystalline silicon layer for a resistance region on a thick insulating film and a polycrystalline silicon layer for a gate electrode on the gate insulating film; Using the polycrystalline silicon layer for gate electrode as a mask, impurities are introduced into the semiconductor substrate on both sides of the polycrystalline silicon layer for gate electrode to form source and drain regions. A method for manufacturing an MIS semiconductor integrated circuit device, comprising the step of introducing impurities into a crystalline silicon layer.