JPS5818785B2 - Seizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate field effect transistor, particularly an integrated circuit with low leakage current between transistors.

In a MIS type semiconductor device composed of metal (M), insulating film (I), and semiconductor (S), wiring metal, insulating film, and A parasitic MIS structure is formed by the semiconductor substrate, and when a voltage is applied to the wiring metal, the surface of the semiconductor substrate becomes of the opposite conductivity type, leakage current flows, and the device often does not operate normally.

For this reason, impurities of the same conductivity type as the substrate are usually introduced in advance into the regions between the active elements of the semiconductor substrate by a diffusion method, thereby increasing the threshold voltage of the regions between the active elements and preventing leakage current. ing.

For example, in a p-channel MO8 type integrated circuit, a method is used in which antimony, for example, is diffused in advance into regions between active elements before the step of forming source and drain diffusions.

However, if the concentration of antimony is increased, the withstand voltage of the source and drain junctions decreases, so there is a restriction on the concentration of antimony that it is necessary to control the concentration in a low concentration region.

However, in the diffusion method, once impurities enter the solid solubility limit, it is extremely difficult to perform low concentration diffusion precisely, and there is wide variation, which is a major factor in reducing the yield in manufacturing this type of transistor. It becomes.

Furthermore, this method requires an oxidation step, a photoetching step, and a diffusion step, making the process complicated, which is also a major factor in reducing the yield.

An object of the present invention is to provide a technique for forming a leakage current blocking region with high accuracy and a small number of man-hours, thereby dramatically improving the yield.

The present invention uses, for example, an ion implantation method as an impurity introduction method, and implants ions of the same electrical conductivity type as the substrate into the entire surface of the substrate under appropriate conditions without using a mask, thereby increasing the threshold voltage only in the region between active elements. This is intended to form a leakage current blocking region.

The present invention is based on the fact that acceptor or donor type impurities caused by ions implanted into the space charge layer on the surface of a MIS type semiconductor fluctuate the threshold voltage, and when ions are implanted through an insulating film, The depth of the distribution can be controlled by adjusting the thickness of the insulating film and the energy of the implanted ions;
This was made based on the discovery that impurities implanted deeper than the space charge layer have no effect on the threshold voltage, and the discovery that impurities implanted shallowly into the substrate surface at low concentrations have no effect on withstand voltage. be.

The manufacturing method of the present invention eliminates the need for the photo-etching process and impurity thermal diffusion process for forming leakage current blocking regions, which were conventionally required.As a result, the number of photo-etching processes and the process of exposing the semiconductor to high temperatures are reduced. This has the effect of improving product yield.

An embodiment of the present invention will be described in detail below with reference to the drawings.

In this example, an n-channel MO8 type semiconductor device will be explained.

FIG. 1 shows a cross-sectional view of a transistor element in which a source region 2 and a drain region 3 have already been formed in a p-type semiconductor substrate 1 by diffusion, and the oxidation process of a gate film 4 has also been completed.

In this case, the thickness of the insulating film 4 in the active region is formed to be thinner than the thickness of the insulating film 5 in the region other than the active region.

Incidentally, the thickness of the insulating film 4 is, for example, approximately 1000, and the thickness of the insulating film 5 between the active elements is, for example, approximately 1 μm.

After going through the step of making the insulating film 5 on the regions other than the active constituent elements thicker than the insulating film 4 in at least the gate region of the constituent transistors, impurities of the same conductivity type as the substrate, such as boron ions 6, are applied over the entire surface of the substrate 1. Inject using the implantation method.

The driving conditions are as follows.

t□Xp+xd >R>t□XF ”=-”°=
°(1) max p Rp 3△Rp>toXG+XdmaX・・・・・・
・・・・・・・・・(2) Here, R is the range (implantation depth) of boron ion 6, △R9 is the standard deviation of the range, tox
c is the thickness of the insulating film 4 on the gate, tOXF is the thickness of the insulating film 5 in a region other than the active element, and Xdmax is the maximum value of the extension of the space charge layer measured from the surface of the semiconductor substrate.

For example, as in the example mentioned above, the thickness of the insulating films 4 and 5 is 10
00λ and 1μ, the acceptor concentration is 10"'cIrL"
If a substrate of 10" to 1012 crn' is used, approximately 600 keV of boron ions 6 may be implanted.

This is a table (published in the United States) that shows the implanted ion distribution once the impurity concentration of the substrate into which the ions are implanted, the implanted ions, and the thickness of the insulating film deposited on the substrate are determined. The driving energy is determined by:

Conversely, if the implantation energy has been determined, the thickness of the insulating film can be determined to obtain the distribution center of the implanted ions at a desired depth.

The implanted ions have a Gaussian distribution, that is, a distribution characteristic in which the maximum concentration is at a specified position and the concentration gradually decreases around this position. Therefore, if ions are implanted under the conditions of the first and second equations, they will become active. In the inter-element region, the position where the concentration of the implanted ion layer 7 matches the impurity concentration of the substrate 1 is located within the space charge layer, and in the active region, especially in the channel region under the gate, the implanted ions are placed below the space charge layer. Layer 7' is formed.

In this case, an implanted ion layer T is also formed inside the source and drain regions 2 and 3, but since the amount of implantation is small, the implanted layer T formed in the source and drain regions reverses the electrical conductivity type of the source and drain regions. It does not go so far as to cause any damage, and does not have any effect on the characteristics of the transistor.

Next, after the ion implantation, heat treatment is performed in, for example, nitrogen gas at a temperature such as about 900° C. for about 30 minutes at a temperature such that the implanted ions do not diffuse, thereby activating the implanted ions.

That is, the atoms in the injected state are not fused with semiconductor molecules, and therefore cannot function as acceptors.

This is heat-treated to cause fusion and activate the implanted ions as acceptors.

In the region between active devices, the acceptor increases the threshold voltage and forms a leakage current blocking region.

Furthermore, in the channel region under the gate, the injection layer T is located under the space charge layer, so it does not have any effect on the gate threshold voltage of the transistor element.

After ion implantation, holes are made in the insulating layer at positions corresponding to the source and drain regions 2 and 3, and source and drain electrodes 8 and 9 are attached as shown in FIG. 2, and a gate electrode 10 is formed on the gate insulating film 4. and get the finished product.

As described above (according to the present invention, it is not necessary to use a mask to form the leakage current blocking region 7, so that the process can be simplified.

However, by appropriately adjusting the thickness of the insulating films 5 and 4 and the energy of the implanted ions, it is possible to increase only the threshold voltage of the region between the active elements, and the threshold voltage can be easily increased by changing the amount of implanted ions. can be controlled, and can be expected to reduce man-hours and greatly improve yield.

Furthermore, in the region between active elements, the implanted ion concentration is 1011 to 1
Since the concentration is as low as 012cIIL-2 and the implantation is shallow within the substrate surface, the withstand voltage of the source and drain junctions is not affected by the ion implantation, and it is possible to avoid a decrease in yield due to a decrease in the withstand voltage. .

In addition, heat treatment after injection can be performed at a low temperature of 1000°C or less, so
This has the advantage of avoiding defects caused by high-temperature heat treatment.

Furthermore, since the impurity concentration can be controlled in a low concentration region by taking advantage of the characteristics of ion implantation, it is easier to control the impurity concentration than with the thermal diffusion method, which requires entering the solid solubility limit once.

If necessary, a step may be added to control the threshold voltage of the gate by implanting ions such as boron or phosphorus into the depletion layer of the active region of the transistor.

At this time, two ion-implanted layers exist under the gate.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an n-channel MO8 type semiconductor device shown for explaining the manufacturing method of the present invention, and FIG. 2 is a cross-sectional view showing the structure of the semiconductor device completed by the manufacturing method of the present invention. 1: Semiconductor substrate, 2: Source region, 3 Nidrain region,
4: Insulating film in gate region, 5: Insulating film in areas other than active region, 6: Implanted ion beam, 7°7': Implanted ion layer

Claims (1)

[Claims] 1. preparing a semiconductor substrate having a first insulating film on a plurality of active regions and a second insulating film thicker than the first insulating film on a region between the active regions; , a step of ion-implanting impurity ions of the same conductivity type as the semiconductor substrate onto the first and second insulating films, and a step of heat-treating the ion-implanted semiconductor substrate, An impurity layer made of ions is located under the second insulating film on the surface of the semiconductor substrate, and under the first insulating film is located at a location deeper than the space charge layer on the surface of the semiconductor substrate. A method of manufacturing an integrated circuit device.