JPS58213442A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a short circuit of metallic wiring and a semiconductor substrate by activating an impurity through beam irradiation without heating the whole semiconductor substrate and shallowly forming source-drain diffusion layer regions. CONSTITUTION:A P-well 2 is formed to the N type silicon substrate 1, and an oxide film 3 is formed. A thin gate oxide film 4 is formed through thermal oxidation, and the source-drain diffusion layer regions 9, 10 of the P type impurity are formed. The diffusion layer regions 7, 8 by the N type impurity are formed, the whole surface on the substrate 1 is coated with an oxide film 11, and contact holes 12, 13 are bored to sections required. The P type impurity is implanted to the surface of the substrate 1 through the contact hole 12 on the diffusion layers 9, 10. The N type impurity 17 is implanted similary to the surface of the P well 2 in the substrate 1 through the contact hole 13. Beams are irradiated in order to activate the impurities 19, 20. The diffusion layers are formed to the contact holes on the substrate 1, and a short circuit of the metallic wiring and the substrate is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a high-density, high-performance semiconductor integrated circuit device.

Generally, in a semiconductor integrated circuit device, in order to make electrical contact between a diffusion layer region in a semiconductor substrate (usually silicon) and an electrode or wiring, a part of an insulating film formed on the semiconductor substrate is used. Fully open the contact hole.

In recent semiconductor integrated circuit devices, in order to improve the degree of integration, the distance from the end of a contact hole formed in a diffusion layer region to the end of the diffusion layer region is designed to be as small as possible. For this reason, contact holes to be opened in the diffusion layer region may be opened protruding from the diffusion layer region due to manufacturing variations. Contact with the board may result in a short circuit. Conventionally, this defect is removed next.

The contact hole opened protruding from the diffusion layer region? ion implantation of impurities of the same conductivity type as the diffusion layer region into the entire surface of the semiconductor substrate.

Ion-implanted impurities are subjected to high-temperature heat treatment.

V by heating the entire semiconductor substrate.

Activated within the semiconductor substrate and newly expanded, t! ! L
Ii! A diffusion layer of the same conductivity type as the diffusion layer region is formed to prevent the metal wiring from coming into contact with the semiconductor substrate outside the diffusion layer region through the contact hole, which is opened protruding from the diffusion layer region.

However, in order to improve the performance of MO8 type transistors that constitute sandwiched semiconductor integrated circuits, it is required to form a shallow source/drain diffusion region.
According to the conventional method, the entire semiconductor substrate is heated during the high-temperature heat treatment after ion implantation, so that the source/drain diffusion layer regions of the MOS transistor are re-diffused.
Shallow source drain diffusion! It is difficult to realize this in ii1).

rc, the source/drain diffusion layer region of a p-channel MO8 type transistor device is formed.

The poron atom is often used as a P-type impurity.

Because the diffusion coefficient is significantly larger than that of arsenic atoms, which are N-type impurities, even a slight heat treatment causes deep diffusion, resulting in a shallow diffusion layer. I couldn't make it happen.

It was not possible to realize a high-performance P-channel MO8) transistor.

The purpose of the present invention is to overcome these drawbacks of conventional methods. A high-performance MOS) transistor in high-density semiconductor integrated circuit devices? The goal is to achieve even higher performance semiconductor integrated circuit interleaving.

The present invention provides a method for manufacturing a semicircular integrated circuit device, comprising:
A first diffusion layer region having conductivity opposite to that of the semiconductor substrate in one main surface of the conductive semiconductor substrate? A step of forming an insulating film on the first diffusion layer region? a step of forming a contact hole in the insulating film; and a step of forming a contact hole in the insulating film. Do the impurities have the same conductivity type as the first diffusion layer region?
The step of implanting ions into the surface of the semiconductor substrate, and the implanted impurity group, are activated by light irradiation without heating the entire substrate, instead of the conventional high temperature heat treatment, and the first diffusion layer region is activated by light irradiation without heating the entire substrate. With the same contact hole,
A step of forming a metal wiring @ in contact with the first diffusion layer region and the second diffusion layer region and extending and depositing on the insulating film? Features.

In the semiconductor integrated circuit device according to the present invention, the entire semiconductor substrate? Can a defect be caused by a short circuit between the metal wiring and the semiconductor substrate due to misalignment of the mask with respect to the diffusion r@ layer region of the contact hole without heating? 1 MO because it becomes possible to prevent
It has become possible to fabricate high-performance MOS (MOS) transistors in which the depth of the source and drain diffusion layers of type 8 transistors can be made shallow, thereby creating a high-density, high-performance semiconductor integrated circuit device. This is something that can be provided.

This will be explained in detail using examples below. In this implementation, N-type silicon substrate? The array of complementary 1M08 semiconductor devices used will be explained. As shown in FIG. 1, a l'M diffusion layer region (hereinafter referred to as P well 2) is formed in an N-type silicon substrate 1 by a conventional method, and then as shown in FIG. A thick field oxide film 3 is formed by a well-known method. After forming a thin gate oxide film 4 by vigorously oxidizing the surface of the silicon substrate 1, a gate polysilicon growth process and a gate polysilicon photoetching process are performed.
Source/drain diffusion layer region 9.1 (l
After forming an edge by ion implantation of boron atoms and source/drain diffusion using N-type impurities [formed by ion implantation of 7 and 8 t arsenic atoms in the A region, the entire surface of the silicon substrate 1 is coated by CVD (chemical vapor phase). (growth method), the oxide film 1
Only the contact hole 13 opened on the plate #1 is covered with a photoresist 14, and the Pi diffusion #9 exposed in the contact hole 12 is passed through the contact hole 12 opened on the P diffusion layer 9.10. .10. After implanting P-type impurity 1, for example, IFI ions of boron atoms into the surface of the silicon substrate 1 exposed due to misalignment of the mask of the contact hole 12, a photoresist 1 used as a mask for ion implantation is applied.
Remove 4. Similarly, as shown in FIG.
, 10 are covered with a photoresist 16, and the N-type diffusion layers 7.8 exposed in the contact holes 13 pass through the contact holes Bi formed on the N-type diffusion layers 7.8. After ion-implanting N-type impurities, for example, phosphorus atoms 17, into the surface of the P-well 2 in the silicon substrate 1 exposed due to misalignment of the mask for the contact hole 13, the photoresist 16 used as a mask for ion implantation is removed. Remove. Injected impurities 19, 20
Light irradiation for T-activation, Ar pulse racer 18? By irradiating only the contact holes or the entire surface of the wafer, as shown in Figure 6,
Only the exposed silicon substrate portion is heated and the impurities are activated. At this time, since the temperature rise of the entire substrate is slight, the source/drain diffusion layer in the transistor portion does not re-diffuse, and the transistor characteristics do not change. It is equally effective to use a Xe 7 lash lamp instead of the Ar laser beam, and is particularly suitable for mass processing. Even if the contact hole is not above the diffusion layer region 19, 20 after activation of the diffusion Fi 21, 22, a new diffusion layer is formed in the area where the contact hole was formed on the silicon substrate 1, and the metal wiring is short-circuited with the silicon substrate. Prevent money from becoming defective. Next, as shown in Figure 7, is the aluminum film used as the metal wiring? Necessary aluminum wiring 21 is formed by vapor deposition and photoetching, and a complementary MO8 semiconductor device is completed.

As is clear from the above, the semiconductor integrated circuit device according to the present invention can prevent defects caused by short circuits between the metal wiring and the semiconductor substrate due to misalignment of the mask with respect to the diffusion layer region of the contact hole, and can also prevent transistor leases and Since the depth of the drain diffusion layer can be made shallower, the inside of the gate of the MO8 type transistor can be made smaller, and the transistor performance can be improved. The present invention is intended to realize a high-density, high-performance semiconductor integrated circuit device.

Note that the present invention is not limited to the above-mentioned assembly and arrangement, but can be implemented in various modifications without departing from the spirit thereof.

[Brief explanation of drawings]

1 to 7 are cross-sectional views showing the manufacturing process of a complementary MO8 semiconductor as an embodiment of the semiconductor integrated circuit device according to the present invention. 1... Nu semiconductor substrate, 2... P well diffusion layer region, 3... field oxide film, 4...
...Gate oxide film, 5.6...Gate polysilicon, 7,8...N-type source/drain diffusion layer region, 9.10...P Type north/drain diffusion layer region, 11... interlayer oxide film, 12...
・Contact hole on PM diffusion layer, 13...Nll
Contact hole on diffusion layer, 14.16...Photoresist, 15...Ion implantation of boron atoms. 17... Phosphorus atom ion implantation, 18...
...Ar laser light, 19...Ion-implanted phosphorus atoms. 20...Ion-implanted boron atoms, 21.
Old...19 phosphorus atoms are fired by Ar laser! 7 Activated to become an N-type diffusion layer, 22... 2o boron atoms activated by Ar laser to become a P diffusion layer, 22... Aluminum This is the wiring. Agent Patent Attorney Susumu Uchihara α-Ring 1 S 1 Kushi ZI 21' Kayazun

Claims (1)

[Claims] a step of forming a first diffusion layer region of a conductivity type opposite to that of the flrJ semiconductor substrate on one main surface of a semiconductor substrate of one conductivity type; and a step of forming an insulating film on the first diffusion layer region;
Is there a contact hole in the insulating film? forming a hole; ion-implanting an impurity having the same conductivity type as the first diffusion layer region into the surface of the semiconductor substrate through the contact hole; activating the ion-implanted impurity by light irradiation; A second diffusion layer region of the same conductivity type as the first diffusion layer region? and forming a metal wiring layer in contact with the first 1 mm diffusion region and the second diffusion layer region through the contact hole and extending over and depositing on the insulating film. case? A method for manufacturing a semiconductor integrated circuit device characterized by: