JPS5832448A - Manufacture of complementary mos field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain the titled transistor having a desired value of withstand voltage of small fluctuations by a method wherein the windows on the region, on which p type and n type impurities will be introduced, are provided simultaneously. CONSTITUTION:A p type well 2 is formed on an n type semiconductor substrate rate 1, and the surface of the substrate 1 is covered by an Si oxide film. Then, windows to be used for implantation of impurities of n type and p type are bored simultaneously, a resist 14 is covered only on the region in which impurities giving an n-conduction type will be implanted. Then, impurities giving p- induction type are implanted, and a p type source region 4, a drain region 5 and a channel stopper region 6 are formed. A resist 14 is covered on the whole surface excluding the windows which will be used for introduction of n type impurities. Impurities which give n-induction type are introduced and an n type source region 7, a drain region 8 and a channel stopper region 9 are formed. Through these procedures of manufacture, the desired withstand voltage value of small fluctuations can be obtained for the respective MOSFET of -MOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing complementary MO8 field effect transistors.

A complementary MO8 field effect transistor is one in which P-channel type and N-channel type MO8 field effect transistors are incorporated in the same chip. is formed near the surface of the semiconductor substrate, and a P or N channel type MO8 field effect transistor is formed in this region, and an N or P channel type MO8 field effect transistor is formed in the -1 semiconductor substrate.

Furthermore, each MO8 field effect transistor has a source region, a drain region, and a channel region between the source region and the drain region. I'm surrounded by NO〆-. Each MO8
The withstand voltage between the source and drain of a field effect transistor needs to be higher than the power supply voltage used, but in many cases, each MO8
The breakdown voltage of the source region and drain region of a field effect transistor is sufficiently high, but the breakdown voltage of the source region or drain region and channel stopper region is small, and each MO
The breakdown voltage of a field effect transistor is determined by the distance between the source region or drain region and the channel strapper region. In the conventional manufacturing method of complementary MO8 field effect transistors, it is difficult to accurately control the distance between the source region or drain region and the channel stopper region, and the breakdown voltage of each MO8 field effect transistor shows large variations. A conventional manufacturing method will be described below with reference to the drawings.

As shown in FIG. 1 (Jl), on a semiconductor substrate 1 of N (or P)ffi, (P or N)l! As shown in FIG. (or N) type channel MO8 field effect transistor, the source region 4 and drain region 5 and a part of the surface of the well 2 have a new MO8 effect.
Rounded P (or N) to prevent the occurrence of field effect transistors
P (or N) II channel stopper region 6
Figure 1 (
C) N (or P) in well 2! III Channel M
An N (or P) type channel stopper region 9 is formed in the source region 7 and drain region 8 of the O8 field effect transistor and in a part of the semiconductor substrate 1. #I1 As shown in Figure (d), gate electrode 11.1
1', source electrode 12.12', drain electrode 13.1
3' to form P-channel type and N-channel type MO8 field effect transistors. complementary f
In the iMO8 field effect transistor, the breakdown voltage of each MO8 field effect transistor is determined by whether the breakdown voltage between the source 4.7 and the drains 5 and 8 is sufficiently large, or the breakdown voltage between the source 4.7 and the drain 5.8 and the channel stopper 6.9. In many cases, the breakdown voltage of each is small, and is determined by the breakdown voltage of the source or drain and the channel stopper.However, in the conventional manufacturing method, P (or N)
When forming an impurity that imparts a transparent conductivity type by a diffusion method or an ion implantation method, a silicon oxide film or a photosensitive resin thin film is formed as a protective mask in areas where the impurity should not be diffused or implanted. Furthermore, when diffusing or implanting KP-type impurities and when diffusing or implanting N-type impurities, the first
Separately source regions as shown in Figures (b) and (e),
Open a window to be diffused into the drain region and channel stopper region. Therefore, it is very important to always maintain a constant distance between the source or drain region and the channel stopper region! However, the withstand voltage of the PN junction between the source or drain region and the channel region exhibits large variations and is often lower than the power supply voltage used.

The present invention has been made to eliminate the above-mentioned drawbacks and improve the withstand voltage of MO8 field effect transistors, and its characteristics include Hiro, PJ impurities, and N! 1! At the same time, open a window in the region where impurities are to be diffused or ion-implanted, and then when diffusing or implanting P-type impurities, cover with a protective mask to prevent Nil impurities from being diffused or implanted, and then diffuse or implant N-type impurities. In some cases, the manufacturing method uses a protective mask to prevent P-type impurities from being diffused or implanted, and since the positions of the source region, drain region, and channel region are formed at the same time, the source region or drain region and the channel stopper region are formed at the same time. A complementary MO8 field effect transistor can be obtained in which the breakdown voltage between the source region or drain region and the channel stopper region has a desired value with little variation.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

As shown in FIG. 2(a)K, an N (or P) type semiconductor substrate 1
A P (or N) type limited region, that is, a well 2, is formed on the surface of the semiconductor substrate 1, and a silicon oxide film is formed on the surface of the semiconductor substrate 1.

Next, as shown in FIG. 2(b), a window is simultaneously opened for implanting an impurity giving an N-type conductivity type and an impurity giving a P-type conductivity into the semiconductor substrate 1 and a part of the well 2. Next, as shown in FIG. 2(C), only the region where the impurity imparting N (or P) conductivity type is to be implanted is covered with a photosensitive resin film 14.
The photosensitive resin film 14 may cover at least a part of the surface of the silicon oxide film surrounding the window, and may cover the other part. It is already a well-known fact that a photosensitive resin film or a silicon oxide film can be used as a protective mask against ion implantation. - For ions accelerated at a certain acceleration voltage, a silicon oxide film with a large thickness can be used as a protective mask for ion implantation. It is a well-known fact that oxidation and photosensitive resin films are effective in preventing ions from passing through.

As shown in Figure 2(d), the next VC fi
A limited P-type source region 4, drain region 5, and channel stopper region 6 are formed by implanting an impurity that imparts P-type conductivity and performing heat treatment at a high temperature. Next, as shown in FIG. 2(e)K, the area other than the window for implanting the N-type impurity is covered with a photosensitive resin film 14. Next, as shown in FIG. 2(f), an impurity giving fiN type conductivity is implanted by ion implantation, and an N-type source region 7 and drain region are formed by heat treatment at high temperature. 8. A channel stopper region 9 is formed. Thereafter, the entire surface is covered with a silicon oxide film, a gate insulating film is formed by thermal oxidation, and electrodes are formed to form a complementary MO8 field effect transistor as shown in FIG. The breakdown voltage of each MO8 field effect transistor of the complementary MO8 field effect transistor obtained by the manufacturing method of the present invention is a new value with little variation. Next, embodiments of the present invention will be described. do.

In FIG. 2(a), a part of a semiconductor substrate 1 of N type with impurity degree of 1014 to 10" CR-3 is used as a semiconductor substrate, and impurity degree of Pi!!! is contained in a part of the semiconductor substrate 1 of 1011s to 1017cW.
The limited area of L-3, that is, the well 2, is connected to the semiconductor substrate 1.
A silicon oxide film with a thickness of 0.5 to 1.5
〃Form. Next, in FIG. 2(b), a window is prepared by removing the silicon oxide film in the portions where impurities of P type and Np conductivity type are to be implanted using a photosensitive resin film. Next, in FIG. 2(e), the surfaces of the semiconductor substrate 1, the P well 2, and the silicon oxide film 80 other than the window where the impurity that gives the photosensitive resin film a P-type conductivity type should be implanted are 1 to 8 μm thick. Cover with thickness.

Next, in FIG. 2(d), boron is implanted as an impurity giving P-type conductivity in an amount of 1X1014 to 1X10 (Ill-") by ion implantation and accelerated at 20 to 100 Kv.

After that, 10 to 80℃ at 900℃ to 1100℃ or high temperature.
A heat treatment is performed for a minute to activate the boron and form a P-type region. Next, in FIG. 20, the surfaces of the semiconductor substrate 1, P well 2, and silicon oxide film 8 other than the window in the region where the impurity giving NW conductivity type is to be implanted are
Cover with a thickness of 8μ. Next, in FIG. 2(f), phosphorus is ion-implanted as an impurity giving the conductivity type of Nll, and is accelerated at 40 to 150 V to give IX 10" to IX
Lu Seo's he who injects the amount of 10"Ca1-"700~t
Heat treatment is performed at a high temperature of 00° C. for 10 to 80 minutes to activate phosphorus and form a N region.

The silicon oxide film 2 is formed by thermal oxidation or chemical reaction vapor phase growth at a high temperature of 900 to 1100°C.
A gate insulating film is formed on the surface of the semiconductor substrate in the channel region between each source region and drain region, covering the entire substrate surface with a thickness of 25 μm, and then is removed! In the manufacturing method described above in which a complementary MO8 field effect transistor as shown in FIG. The semiconductor substrate may be exposed through a limited window on the surface.

For example, it is possible to implant impurities after covering with a silicon oxide film of 200 to xooooX.

Next, other embodiments will be described.

In the first embodiment, an ion implantation method is used, but in other embodiments, a doped oxide film is used. FIGS. 2(a) to 2(b) are the same steps. Next, as shown in FIG. 3(a), silicon oxide [1B] containing boron is formed to a thickness of 1500 to 5000 Å over the entire surface of the substrate by vapor phase growth, so that at least the boron is diffused. Leave it only in the window where it should be. Next, as shown in FIG. 3(b), a silicon oxide film 16 containing K I
It is formed to a thickness of ~5000 Å over the entire surface of the substrate (2) by vapor phase epitaxy, leaving at least only the windows in the regions where phosphorus is to be diffused.

Next, as shown in Figure 3 (C), 1000 to 1200 IC
A heat treatment is performed at a high temperature of 100 nm to diffuse P-type and Nw impurities into the semiconductor substrate as doped oxide.

Thereafter, a complementary MO8 field effect transistor is formed as shown in FIG. 2(g) through step 1 of forming a gate insulating film and step 1 of forming an electrode.

A third embodiment will be described next.

#! Figures 2(a) and 2(b) are similar to the previous example, but in Figure 2(b), phosphorus is accelerated by 50 to 100 KeVK by ion implantation to the entire surface of the semiconductor substrate to 1014 to 1011
When only 1cIL''2 is implanted, an N-type semiconductor region 17 is formed as shown in FIG. 4(a). Next, as shown in FIG. 4(b), the area other than the window on the semiconductor substrate 1 in the region to be the KP type semiconductor region is covered with a photosensitive resin film 14 with a thickness of 1 to 8 μm, similar to FIG. 2(). cormorant. Next, as shown in Figure 4(C), boron was accelerated at 20~gQKeV using the ion implantation method.
Ions are implanted by o1S~10"CIL-", and the nine N-type semiconductor regions 17 formed by the ion implantation are changed into PM semiconductor regions 18, and the source regions 4. A drain region 5 and a channel stopper region 6 are formed. After that, a high-temperature heat treatment is performed at 900 to 1100°C for 10 to 30 minutes to activate the implanted impurities, a gate insulating film is formed, and an electrode is formed. A complementary fiMO8 field effect transistor is obtained. This third embodiment has fewer steps for forming the photosensitive resin film than the first embodiment, and is effective in shortening the manufacturing process. a step of including it in a silicon oxide film and forming it in a required part,
A step of forming an impurity that gives another conductivity type by ion implantation, and a rounding high temperature heat treatment to activate the implanted impurity.
00 to 1100' (:!) for 30 to 60 minutes to diffuse the impurity-containing silicon oxide film into the semiconductor substrate to form each source region, drain region, and channel region. There are also methods for manufacturing effect transistors.

The complementary MO8 field effect transistor obtained by the manufacturing method according to the present invention as described above has the characteristics of a desired breakdown voltage with little variation, can shorten the process, and has a high yield. You can get something. Furthermore, the present invention is not just a single element, but an integrated circuit. Needless to say, it is used as a raw material.

Brief explanation of the drawings □ Figures 1 (a), (b), (c) and (d) are cross-sectional views of the manufacturing process according to the conventional manufacturing method, and Figures 2 (a) and (b). ).

(c) t (d) , (e) , (f) and (g
) are cross-sectional views during the manufacturing process according to the present invention;
(b) and (C) are cross-sectional views in the manufacturing process of the example, 1... - conductive type semiconductor substrate, 2...
A limited region of conductivity 1 [which is opposite to the substrate, 3...Silicon oxide film, 4.7...Source region, 5.8
......Drain region, 6,9...Channel stopper region, lO...Gate insulating film,
11.11'...Gate electrode, 12, 12'
...... Source electrode, 13.13'... Drain electrode, 14... Photosensitive resin film, 15.16
...Silicon oxide film containing impurities, 17...
. . . N type region, 18 . . . P type region.

7' Engraving of drawings (8 dimensions ξ no changes) S / Figure Z Z Figure 2 Figure Z 4 Figure 6, subject of amendment (1) Full text of specification (2) Drawings (3) Document certifying authority of agency 7 , Contents of the amendment (1) Engraving of the entire specification and drawings (no change in content) (2) Seal registration certificate 1975 Patent Application No. 23182
We hereby certify that the applicant of this patent is the same as the applicant of this case who filed the application pursuant to the provisions of Article 44, Paragraph 1 of the Patent Law.

& Attached document (1) Full text of specification (engraved) (2) Figure surface (engraving) (3) Seal certificate □ −222=

Claims (1)

[Claims] A first step of simultaneously introducing impurities of one conductivity type into the semiconductor substrate into the channel stopper region of the P-channel transistor and the source and drain regions of the N-channel transistor, and the channel stopper 1 of the N-channel transistor [,! Complementary 11 characterized in that it includes a second step of simultaneously introducing other conductive impurities into the source and drain regions of the P-channel transistor.
A method for manufacturing an MO8 field effect transistor.