JPS5836006A - Operational amplifier - Google Patents

Abstract

PURPOSE:To facilitate IC-implementation by constituting an operational amplifier without including a driving and amplifying circuit which includes a phase compensating capacitor, and to decrease the number of parts by connecting a differential amplifying circuit to an output circuit directly. CONSTITUTION:When the voltage level of an input signal attains to a high level, the collector current IC1of a transistor (TR) Q1 is reduced and at the same time, the collector current of a TRQ2 is to increase. Since, however, a load is a contant current loading circuit 10, the emitter-collector voltage VCE2 of a Q10 decreases. Therefore, the collector voltage of the Q2 and the base voltage of the Q10 rise. Then, the VCE10 of the Q10 falls and the base voltage of a Q13 rises. When the base voltage of the Q2 rises, on the other hand, a base current from a constant current circuit 14 to a Q12 increases and the emitter voltages of the Q12 and Q13 rise, thereby increasing a current from an output capacitor C0 to a load RL. When the voltage level of the input signal drops, the base voltage of the Q2 drops in level and the Q11, Q12 and Q13 operate reversely to said states, thereby decreasing the current flowing to the RL through the capacitor C0.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operational amplifier suitable for use in various electronic devices such as tape recorders, audio amplifiers, and television receivers.

In electronic devices such as those mentioned above, operational amplifiers have conventionally been widely used. To outline its configuration and operation, an input signal is supplied to a differential amplification circuit, and the output signal is amplified by δ by a drive amplification circuit. ) The K supply is drying up. However, in the above-mentioned configuration, between the input end and the output end of the drive amplification circuit, there is a power of 10PF.
It is necessary to provide a phase compensation capacitor to prevent oscillation of about D.

By the way, it is known that when integrating the above-mentioned operational amplifier into an integrated circuit (zero-chip design), it is difficult to configure the capacity within the integrated circuit. It is also desirable that the number of circuit components be small.

The present invention has been made from this point of view, and its purpose is to provide an operational amplifier that can be easily integrated into an integrated circuit by omitting a drive amplifier circuit including a phase compensation capacitor. .

Next, an arithmetic amplifier that has not been studied prior to the present invention will be explained with reference to FIG.

First, let's talk about the circuit configuration: PNP) transistor (L+
% Qs K Therefore, the current mirror circuit 2 is constructed by differential increase [1] times 1lI211 (gai, NPN) transistor Qs, Q<K. And PNP
The base and collector of the transistor Q are directly connected so that 100% of the output signal of the differential amplifier circuit 1 is negatively fed back. Further, the NPN transistor Q5 is configured as an emitter follower, and is directly connected to the sonobase transistor Q, the nobase and the collector. Furthermore, 3 is an input terminal, 4 is a bypass power supply, 5 is a constant current source,
6 is an output terminal.

Next, the circuit operation will be described. In addition, regarding voltage level changes, the earth line gold standard is used, which is the reference potential of all authentic single-unit devices. First, the voltage level of the input signal supplied to the input terminal 3 and the circuit operation when the voltage level becomes AIC will be described. When the input signal is supplied through the capacitor C, the collector current C1 of the transistor 01 decreases, and since the collector current C1 of the transistor GLs is connected to the collector C3 of the transistor GLs, the voltage between the base and the emitter of the transistor Qs decreases. Voltage VB:at3 also decreases. on the other hand,
The base of transistor Q4 is connected to the base of transistor Q3. Therefore, the base-to-emitter voltage VB□ of the transistor Q4 decreases in response to the aforementioned fc change of the transistor Q3. As a result, the voltage between the collector and emitter of transistor Q4 is 1 V. 84 will be more. As a result, the collector voltage of transistor Q4 and the base voltages of transistors Q2 and Ql become higher than the ground line.

Therefore, at the base of transistor Q5, as shown by arrow A,
'FUN will flow and this amount of current will increase. Since the transistor Q5 is an NPN transistor, as the above-mentioned current, that is, the base current increases,
its collector current. Increase by 5. Therefore, the load resistance R
1 becomes high, and an output signal corresponding to the level change of the input signal is obtained from the output terminal 6.

Next, when the voltage level of the input signal supplied to the input terminal 31C becomes low level, the circuit operation side transfer E;# is as follows.
Contrary to the above case, since the base voltage of each of the transistors Q* and Qs decreases, the current value of the current flowing in the direction of the arrow, in other words, the transistor Q5
base current decreases. And the amount of collector current of transistor Q5. 5 decreases, and the voltage across the load resistor RL also decreases. Therefore, an output signal corresponding to the level change of the human input signal is obtained from the output terminal 6.

As described above, the output signal of the differential amplification circuit 1 is negatively fed back by 100'x through two current mirror circuits. Furthermore, extremely stable circuit operation can be obtained without providing a phase compensation capacitor, a drive amplification circuit, etc.

Next, 7'1., which was studied prior to the present invention. Another operational amplifier will be explained with reference to FIG. It should be noted that the same reference numerals are used for subordinate parts that perform the same operations as in the first embodiment, and a complete explanation thereof will be omitted.

First, the circuit operation can be improved when the voltage level of the input signal becomes high. In this case, the amount of collector current. 1 also decreases. At the same time, the amount of collector current of transistor Qt. 2 is about to increase. However, since the load consists of a constant current load circuit IO, the transistor Q
2 collector-emitter voltage V. 0 decreases. Therefore, the collector voltage of the transistor Qa, in other words, the base voltage of the transistor Q2 and the base voltage of the transistor Q5 become high. This means that the base-emitter voltage vBBli of the transistor Q5 has increased, so the transistor Q5 flows as shown by arrow A.
The base current of increases. Therefore, the collector voltage of transistor Q5. 5 also increases, and the voltage across the load resistor RL increases. Therefore, an output signal corresponding to a change in the voltage level of the input terminal is obtained from the output terminal 6.

Next, the circuit operation when the voltage level of the input signal becomes low level can be improved. In this case, the collector current of transistor Q5. 5 decreases, and the voltage across the load resistor RL decreases. Therefore, an output signal corresponding to a change in the voltage level of the input signal is obtained from the output terminal 6. Next, an embodiment of the present invention will be explained in detail in FIG. 3. Note that the difference between this embodiment and the first and second circuit examples described above is that a buffer circuit 11 and an smpp circuit (single-entity push-pull circuit IM) 12 are provided after the booster circuit IM 1. The point is that Therefore, the same parts as in the first and second embodiments are designated by the same reference numerals, and their explanation will be omitted.

First, the operation when the voltage level of the input signal changes to a high level will be described. In this case, changes in the collector voltage and base voltage of the transistor Q1 are similar to those described above. Therefore, the collector-emitter voltage V of the NPN transistor Q+o forming the buffer circuit 11. 8. . decreases, and the base voltage of transistor Q+3 increases.

On the other hand, transistor Q! When the base voltage of transistor GL+z increases, the base current flowing from constant current circuit 14 to transistor GL+z increases as shown by arrow B. And transistor Q
The emitter voltage of +aQ+a increases, and the current flowing from output capacitor C6 to load RL increases. Therefore, a current corresponding to a change in the voltage level of the input signal flows through the load RLvc.

Next, the circuit operation when the voltage level of the input (, 1) decreases will be described.

In this case, the level of the base voltage of transistor Q2 decreases. Therefore, transistor QII%QI□, CIL
13 operates in the opposite way to the previous case, transistor Q12
, the Q-th emitter voltage decreases. and,
The current flowing through the load resistor RL via the output conching O8 decreases. Therefore, a current corresponding to the voltage level of the input signal often flows through the load resistor EL.

Next, another embodiment of the present invention will be described with reference to FIG. The difference between this embodiment and the embodiments described above is that the negative feedback of the output signal of the differential amplification port 1112il is provided by the resistor "f+s".
Rfzk is used, and this amplifier is implemented as an integrated circuit.

When an input signal is supplied to the input terminal 3 via the external capacitor Oi, the differential amplifier circuit 1 operates as described above. Note that the amount of negative feedback from the collector to the base of the transistor Q2 is determined by the resistance Rfr. Although the voltage difference between the collector voltage and the base voltage of the transistors Q and g is completely eliminated, the voltage level changes at the same rate. Therefore, the operation of the differential amplifier circuit 1 corresponding to the input signal and the change in the output signal are the same as in the above case.

Further, even when the voltage level of the input signal supplied to the input terminal 3 decreases, the output signal of the differential amplification port #51 appears in the same manner as in the above case. Below, phase inversion circuit 11.1
The 3EPP circuit 12 also operates in the same manner as described above, and an output signal corresponding to a change in the voltage level of the input signal is obtained from the output terminal 6.

Further, the operational amplifiers shown in any of the embodiments do not have a full phase rectification capacity in their circuits, and the differential amplifier circuit and the output circuit are so-called directly connected.

Therefore, not only is it easy to integrate the circuit, but the number of parts is small, so a significant cost reduction can be expected. It also has the advantage of stable circuit operation.

The actual Mi example of the present invention shown in FIG. 3 and FIG.
Compared with the circuit example of FIG. 2 and FIG. 2, the following advantages are obtained.

(1) Since the output circuit IW12 is constituted by a push-pull circuit, the driving ability for the load RL is improved.

(2) Since the buffer circuit 11 is arranged, the input impedance when the load RL is generated from the base of the transistor Qz is the same as above.

(3) In the buffer circuit 11 and the output circuit 12, the temperature changes in the voltage between the base and emitter of the Q-th transistor cancel each other out, and the
Temperature changes in the pace-emitter voltage of 1 cancel each other out, so the emitter output DC potential of the output transistors Q, +z + Q, +z is the same as that of the transistor Q! of the differential amplifier circuit l. It becomes almost equal to the collector output current potential of .

(4) The positive cycle of the output signal is connected to the inverted Darlington connected PNPi transistor Q++ and NP.
The N transistor Q+2 performs the entire amplification operation, and the negative cycle of the output signal is the inverted Darlington connected HPM transistor Q+o and the PNP transistor Q performs the amplification operation, so the N of the output circuit 12
It was possible to reduce the distorted sound based on the difference between the current amplification factor of the PN output transistor Q+g and the current amplification factor of the PNP output transistor Q+3.

[Brief explanation of drawings]

FIGS. 1 and 2 are circuit diagrams showing operational amplifiers that have been studied prior to the present invention, and FIGS. 3 and 4 are circuit diagrams showing operational amplifiers according to embodiments of the present invention. ■... Differential amplifier circuit, 11... Buffer circuit, 12
...Push-pull output circuit.

Claims (1)

[Claims] 1. A first transistor (QI) to which an input signal is applied to its base and a second transistor (Q, snow) to which a load (10) is connected to its collector;
and a second transistor (a differential amplifier circuit (1) in which the emitters of Q and IIQ are connected in common) and a power supply (vo
. ) and the output point, the first output transistor of the first conductivity type (GL+t
) and a second output transistor (QI3) of a second conductivity type whose collector-emitter path is connected between the output point and the base potential, and the load ( a push-pull output circuit (12)'e configured such that the first and second output transistors (QIz, QCs) perform push-pull operation based on a signal of lO);
The operational amplifier includes a buffer circuit (1) having a first buffer transistor (Q+◎) of the first conductivity type and a second buffer transistor (Qz) of the second conductivity type.
1)? The signal of the load (10) of the differential amplifier circuit (1) is supplied to the first buffer transistor (Q).
Io) to the base of the second output transistor (QCs) through the base-emitter junction of the second output transistor (Q++); An operational amplifier with all features that is transmitted to the base.