JPS5835976A - Insulated gate type field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower the resistance of gate electrode itself and the wiring of the gate electrode in the gate electrode by stacking a poly Si layer onto a high-melting metallic layer, and to form an electrode through a self-alignment method. CONSTITUTION:An Mo 6 is attached onto a field oxide film 2 and the gate oxide film 5 of P type Si 1 through a CVD method, and Mo is crystallized and its resistance is lowered through treatment for thirty min. at 1,000 deg.C in N2. When the Mo oxide film 12 generated at that time is sufficiently removed through etching and P added poly Si 7 deposited onto the whole surface through a CVD method, there is no oxide film on an interface between the layers 6 and 7, and contact resistance is sufficiently lowered. The layers 7, 6 are selectively etched to shape the gate electrode having double layer structure, and an N<+> source 3 and a drain 4 are formed in self-alignment shape through ion implantation. The surface is coated with PSG 8, an opening 14 is bored, and an Al electrode is attached. According to this constitution, the high-melting point metallic layer is annealed, a surface oxide is removed and the poly Si can be laminated, and a metallic gate which can effectively prevent the increase of the contact resistance by the oxide generated through annealing is obtained.

Description

[Detailed description of the invention]

The present invention is based on M engineering 8 IF ET (Metal In
sulBtOr8emic Conductor Field
This article relates to an insulated gate field effect conductor device, such as a metal gate dynamic RAM (MIB type memory II), which is the representative of this conference, and its manufacturing method. In a semiconductor integrated circuit device (Engineer C) consisting of a highly integrated, high-speed MIEi type memory +1, a gate electrode is formed of polycrystalline silicon (hereinafter referred to as BoI+81). However, in order to achieve higher speeds, it is desirable to have a gate electrode material with a lower resistivity than Bo II Ql, and such a material is poly 81 layer (first layer) and ill! ll11!
A two-layer structure with a metal layer (second layer) at the l1 point is considered. In this case, the polysilicon layer is doped with 11 nm to lower its resistance, and the upper layer of high melting point metal is made of, for example, MO. However, as a result of the inventor's study of the gate electrode having this stacked layer structure, it has been found that the following problems exist. That is, in the process of creating this gate electrode, first, the VoI+ 817 chemical vapor deposition technique (OVN) is used.
After forming the high-melting point metal layer t-Wi on top of it by sputtering or CvD, the high-melting point metal layer is further heat-treated (annealed) at a high temperature to lower the resistance. During the formation of the layer, oxygen is incorporated into the
It precipitates at the interface between the 181 layer and the high melting point metal layer. This undesirably increases the contact resistance between the 1 layer and the high melting point metal layer. On the other hand, instead of the high melting point metal in the upper layer, its silicide, e.g. Mg811

[When used, it was hoped that C would reduce the contact resistance mentioned above, but it turned out that the electrical resistance as a gate electrode or wiring did not decrease as much as expected. In any case, a structure in which the high melting point metal or 711 side is the upper layer and the poly 8111 side is the lower layer does not lower the resistance by 1 or less, and the access time cannot be reduced that much, so it is difficult to meet the demand for higher speeds. It can be said that it is impossible. Therefore, an object of the present invention is to sufficiently reduce the electrical resistance r of the gate electrode and its wiring to achieve high speed. The object of the present invention is to provide a device with a gate structure that can be implemented using the self-line method, and to provide a manufacturing method that can produce such a device with good reproducibility. Below, Honkaji Meikai, for example, M18F for dynamic RAM
An embodiment applied to ICT will be described in detail with reference to the drawings. Figure 1 shows an example of a V-type EIIFKTt that includes a memory cell r. One principal surface K of the P-type silicon 11-con board 1
An N+ type source region 3 and a drain region 4 are formed in one element region by the selectively grown field sto1g2, which covers each element, by the self-line method described later. What should be noted here is that the gate oxidation g
5 Gate electrode provided on soil (and 7 gate wiring #j) or 1
It has a two-layer structure consisting of a molybdenum layer 6 as the first layer and a poly 81 layer 7 as the second layer. Molybdenum layer 6 is Cv
This is a result of the formation of the rhinoceros oxide in D, and its resistance has been lowered by crystallization using 7-neel crystallization, which will be described later. When annealing C, the O taken in during growth by 0vDK precipitates on the surface and forms a thin oxide field.
This oxide has already been sufficiently removed by etching. The bottom 1381 layer 7 may also be formed by CvD to a thickness of about 2000λ, and serves as a master during ion implantation for the source and drain regions while preserving the underlying cylindrical layer 6! +-i. In addition, in the figure, 8 is a link 11, a glass gland, and 9 is an aluminum cable. In this way, game) 1[1jj and its wiring (word line)
If it is formed with a two-layer structure of TBo11S1-MoIIPden,
The lower molybdenum layer is annealed to lower the resistance.
During this annealing, the acid precipitated on the surface of the
Since the upper layer Bo II 81 can be formed with the compounds (Moon, Mo5s, etc.) removed in advance, Bo II 81-
Gate structure with sufficiently low contact resistance between molybdenum,
I can do something called Tospup. The resistance of the poly S1 layer 7 can also be lowered by subjecting it to the well-known 11-layer treatment after CvD, so the overall distribution resistance is as low as 100%. , it becomes possible to improve the performance of BX. Moreover, the upper polyB1 layer 7 has a masking effect during ion implantation, and if it is processed into the same pattern as the molybdenum layer 6 to form the gate electrode shape, the gate electrode itself can be
Ion implantation is performed as a mask, and the source and drain regions can be formed using the self-line method. Therefore, the gate structure of this embodiment can be applied to the conventional manufacturing process for poly B1 gates as is, and is advantageous in that it is compatible with existing processes. In addition,
Since the semiconductor layer 6 is formed by OVD, it has good adhesion to the underlying gate oxide film 5. Next, we will mainly discuss the method for manufacturing the memory of this embodiment! Figure 1 o
The mzsyxr section will be explained. first! As shown in FIG. 2A, a field E110malif2 is selectively grown on the main surface of the P-type silicon substrate 1 using a known selective oxidation technique using silicon nitride as a lot mask. Next, as shown in Figure 112B, the mask 10 and the underlying Si
o. After removing the film 111r by etching, a gate oxide film 5 is grown by heat treatment in an oxidizing atmosphere, and then O
A molybdenum layer 6 is coated on the entire surface using VD. And N.I.
By performing heat treatment at 1000° C. for 30 minutes in the inside, the molybdenum layer 6'kif is crystallized and reduced in resistance. At this time, the O snow incorporated into the molybdenum layer 6 in OvD# is deposited on its surface, and the surface oxide film (MoO snow, 11
go01 etc.) is generated. Next, as shown in FIG. 20, the surface oxide film 12 is lightly etched using an H1 etchant. As a result, molybdenum oxide on the surface of the molybdenum layer 6 is sufficiently removed. Next, as shown in the llZD diagram, a poly 81 layer 7 is grown on the entire surface by OvD. This board 1) 81 layer 7 may be subjected to a known II treatment to lower the resistance, or may be treated with 0VDK.
During growth, phosphorus is simultaneously topped to form a low-resistance polys
It is also possible to use a precipitated product. Bo II 81 layer 7 is grown at a low temperature (590 to 600°C) on the surface oxide layer 6 from which the surface oxide film has already been removed, and the annealing of the layer 6 has already been completed. Therefore, no oxygen precipitation (formation of oxide film) occurs at the interface between both layers 6-7IvI, and the contact resistance is extremely low. Then #! As shown in Fig. 2E, the bottom 1181 layer 7 and the bottom layer 62 are 1! The same pattern is sequentially etched to form a two-layer gate electrode and its arrangement 1i1. Next, as shown in Figure 1i2F, the entire surface is irradiated with an arsenic ion beam 13'l (irradiated with poly 81 layer 7 and field 8
1011js2@gate oxidation 1115 between these as a mask? One row of ion implantation is performed with l- missed to selectively form an LKkl+ type source region 3 and a drain region 4 on the silicon substrate. These inner areas are poly 81 layer 7
It is formed in a self-aligned manner (self-aligned K) by the mask action of . Therefore, the protective effect of the poly 81 layer 7 prevents arsenic ions from penetrating through the molybdenum layer 6, and compatibility with the existing self-line type ion implantation process can be maintained. Next, as shown in Fig. 2G, a link 11 gate glass film 8 is grown on the entire surface by OVD, and predetermined portions of this glass 8 and gate oxide 5 are removed by known photoetching to form a contact hole 14. . Next, aluminum was applied to the entire surface using the well-known vacuum evaporation 5I technique, and this was patterned using the well-known photoetching method to form the aluminum layout shown in the tliL1 diagram.
Forms equal hair. As mentioned above, by the manufacturing process of this example, R
The device shown in Figure #11 can be produced with good reproducibility without substantially changing the existing process. Moreover, since the Bo II El 1 layer is provided after light etching of the oxide film on the surface of the molybdenum layer during the process, the contact resistance thereof can be reduced by 7 to ensure the iII+ motion operation of the Vb8I memory. FIG. 3 shows a method of manufacturing a memo 11 according to a 112th embodiment of the present invention. In this example, as shown in the diagram 1113, first, the gate oxide 1145 formed in FIG. 2B is patterned by known photoetching, leaving only the gate position, and then a molybdenum layer 6 is formed in the same manner as described above. Next, as shown in FIG. 3B, a molybdenum layer 6 is formed in the same manner as described above.
After annealing, the molybdenum oxide deposited on the surface was removed by light etching, and then
1st layer 711 - 0 next layer #30 As shown in the diagram,
1) S1 layer 71 and 1) Budden layer 6 are sequentially patterned into the same shape using known photoetching to form the gate electrode and the arrangement shown in FIG. Next, as shown in FIG. 113D, the C-type non-stop region 3 and the de-V47% region &'t self-finishing line method are formed by known ion implantation, respectively, in the same manner as described above. Note that if the oxide film 1511 is not formed, the source and drain regions may be formed by known thermal diffusion. Next, as shown in FIG. 51131, a 11 insilicate glass [8] is formed on the entire surface by OvD, and a contact hole 14 [8] is further formed by known photoetching. After this, aluminum is steamed and processed into each aluminum wiring by etching in the same manner as described above. Although the present invention has been illustrated above, the embodiments described above can be further modified based on the technical idea of the present invention. For example, instead of molybdic acid in the first layer of the gate, another high melting point metal layer, such as tungsten, tantalum or titanium, can be provided. Also, is it possible to use the above-mentioned laminate structure of high melting point metal for the gate electrode as well as for the 7th wiring?Is it desirable to use it only for the gate electrode?
The trim can also be made of aluminum or the like. Also,
The above-mentioned method 1) the buten layer may be formed by sputtering instead of OVD. Note that the present invention is a dynamic RAM.
' and other M-worker 8 type memo 11, l! [ijm I
8 type 1: It is widely applicable to insulated gate type field effect conductor devices such as I-thick L8 type. As described above, according to the present invention, at least in the gate electrode, the high melting point metal layer is the t-1 layer, and since the structure is such that polycrystalline silicon is laminated thereon, the surface of the high melting point metal layer is not oxidized after annealing. After removing the material, polycrystalline silicon I
It is possible to provide a metal gate board that can be laminated with an I-contact board and can effectively prevent an increase in contact resistance due to oxides that are damaged by annealing. Therefore, by adding up the demand for higher speed by 9% of the light, an insulated gate type device can be obtained. Moreover, since the first high-melting point metal layer is protected by a polycrystalline silicon layer that is resistant to ion implantation, the gate with this stacked structure allows the source and drain regions to be formed using the self-line method by ion implantation. Compatibility with manufacturing process? Can be retained. In addition, the gate of the upper layer structure was removed by light etching of the surface plate after 7 years of the first high melting point metal layer, and then the polycrystalline silicon layer was removed by light etching. Since the above oxide "4" is created by
can be reliably removed, and a connected device can be created with good reproducibility.

[Brief explanation of drawings]

The drawings show an embodiment in which the present invention is applied to the MIS type memo I+. Each wr side view showing the manufacturing method in order of production, Figures 3A to 3
FIG. E is a cross-sectional view showing the method of manufacturing the memory cell part according to the second embodiment in the order of steps. In addition, in the symbols shown in the drawings, 5 is a gate oxide film,
6 is molybdic acid, 7 is the Bo11B i layer, and 12 is molybdenum oxide. Figure 1 Figure 2A Figure 25 Figure 2C Figure 2E Figure 2F Figure 3A Figure 3B Figure 3D

Claims (1)

[Claims] 1. In an insulated gate field effect conductor device in which a gate electrode is provided between a source and a drain region via an insulating Mk, at least the gate electrode or a lower layer made of a high melting point metal and a polycrystalline This device is characterized by its leakage due to its laminated structure with a soil layer made of silicon. λ A step of forming an insulator J1gt- on the semiconductor substrate, a step of forming #ICaI & melting point metal layer on this insulating film,
A step of heat-treating the high melting point metal layer and then etching the entire surface thereof, a step of laminating a polycrystalline silicon layer on the high melting point metal layer after this etching, and a step of stacking the polycrystalline silicon layer and the high melting point metal. A step of processing each layer into at least a gate electrode shape, and after this processing, the multilayer M1
A method for manufacturing an insulated gate field effect semiconductor device, comprising selectively introducing predetermined impurities into the semiconductor substrate as a silicon layer mask (thus forming north and drain regions, respectively).