JPS5834973A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve integration density by miniaturization of a subcontact region and, in addition, to shorten etching time by settling an interface between a metallic layer for an electrode of a subcontact region and a semiconductor substrate shallower than an interface between the field oxide film and semiconductor substrate. CONSTITUTION:An SiO2 film and Si2N4 film are deposited on a P type silicon substrate 21 and patterning is made by PEP to form a field oxide film 26 by thermal oxidation. Then, an element forming region 27 and the subcontact region 28 are produced. N type impurities are diffused into the element forming region 27 to form N<+> regions 31, 32. After an SiO2 film 33 is formed over the entire face of the substrate by CVD, the source, drain and subcontact regions are provided by PEP and a contact hole 34 is formed. Next, electrodes and interconnection are produced by evaporation and patterning of a metallic layer 36. This permits the interface between the metallic layer 36 of the subcontact region 28 and the substrate 21 to be shallower than the interface between the field oxide film 26 and the substrate 21 so as to be able to shorten the etching time and to improve integration density by miniaturization of the subcontact region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having sub-contacts and a method for manufacturing the same.

MU8 (Metal!
For example, semiconductor devices have been manufactured through the steps shown in FIGS. 1(1) to 1(h).

In other words, as shown in Figure (a), a separate layer of sllbe 3 was deposited on the P-type silicon base 411.
After patterning the Nhjl 3, boron ions are implanted to prevent inversion using the resist film 5 covering the opening 4 in the field F region as a mask.

Next, as shown in FIG. 1, after peeling off the resist film 5, thermal oxidation is performed using the patterned 84N film 3 as a mask to form field oxidation M6, and devices are formed in a predetermined area of the silicon substrate l. 0th order 4131 to provide formation electric field
As shown in Figure (C), the film 3 and 8i (4 film 2
After removing by etching, gate oxidation M481' is applied to the entire surface.
Then, polycrystalline silicon patterns for gate electrodes and wiring are formed. Then, using the patterned polycrystalline silicon film 9 as a mask, a gate oxide film 8 is formed.
After etching, N is applied to the exposed silicon substrate 1 surface.
tJI! Diffusion of impurities such as phosphorus is performed to form N''!III regions 10°11 which will serve as sources and drains.
Next, as shown in FIG. 1(f), the pseudomembrane 12 is formed.
VD8i0. J[72f)'')-S#)' A contact hole 13 is formed in the sub-contact region and the sub-contact region by PH1P.After that, as shown in FIG. A sub-contact hole 14 is formed.Finally, as shown in Figure 1 (
As shown in the figure, a metal layer 15 of, for example, At (aluminum) is deposited on the entire surface and then patterned to form electrodes and wiring.
t-forming.

However, in such a conventional semiconductor device, (1) In order to form the sub-contact hole 14, CV
D8i0. After etching the film 12, it is necessary to etch an even thicker field oxide film 6, which takes a long time.

■ Since it is necessary to form a contact hole in films that are truly hostile to etching speed, such as the field oxide film 6 by thermal oxidation and the CVD 84 pseudo film 12, it is appropriate to provide an appropriate taper (see Figure 1). As shown by ■, At
It is easy for the metal layer 15 to break off.

■ Due to the reasons for ■ and ■, the pattern conversion difference becomes large.
A large area is required to form the sub-contact region, and the degree of integration is reduced.

There were other drawbacks.

This invention was made in view of the above-mentioned circumstances, and the 17th purpose is to shorten the etching time and prevent breakage of the metal layer of the cutout electrode. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same.

Hereinafter, one embodiment of the present invention will be described with reference to the inner surface.
First, as shown in FIG. 82 (A/2), PtJCltBI is deposited on a silicon substrate 21 in 84 to 84 mN+ 11jtJJ with a thickness of aNA, and 81m N+ 11jtJJ is patterned by PfjP. After that, an opening 2 is made in the field area.
Using the resist film 25 having No. 4 as a mask, boroshi ions are implanted to prevent reversal.

Next, 1n21N (5hN41123 was patterned after peeling off the resist film 25 as shown in Figure 2).
A field oxide film 26 is formed by thermal oxidation using as a mask. As a result, an element formation region 27 is formed in a predetermined region of the silicon substrate 21. At this time, in this embodiment, the sub-contact region 28 is also formed at the same time.

(As shown in 2nd □□□ (C), 84.N, after etching and removing the film 23 and the SiO film 22, a gate oxide film 29 with a thickness of several hundred is formed on the entire surface, Furthermore, several thousand polycrystalline silicon films 30 are deposited on this gate oxide film 29. As shown in FIG.
A polycrystalline silicon pattern for the gate electrode and wiring is formed by this process, and at the same time, a polycrystalline silicon pattern is also formed in the sub-contact region 28. Then, the gate oxide M29 is etched using the patterned polycrystalline silicon 1 as a mask. Next, an N-type impurity such as phosphorus is diffused into the surface of the repaired silicon substrate 21 (source-drain region). Then, a 5Nlli filling region J7.JJ is formed.At this time, since the polycrystalline silicon film 30 and the gate oxide film 2# are present in the % sub-contact region 28, N1 dispersion is not performed.

Next, as shown in FIG. 2(C), Cv tax 8i0.
Film JJ is formed using an IP machine.

Next, as shown in FIG. 2(f), the above CVD8iL)
.

Contact holes S4 are formed in the source, drain and sub-contact regions of M33 by PEP. In this case, the polycrystalline silicon film 3 is in the sub-contact region 2B.
0, the substrate 21 is never exposed because of the 0th order (=
, FIG. 2-), the polycrystalline silicon MIJo of the sub-contact region 28 and the gate oxide film 29 thereunder are removed by etching from ζ2 and P'FJPi2 to form one sub-contact hole al'Ik-. As shown in FIG. 2(h), three metal layers of AA, for example, are deposited over the entire surface and patterned to form electrodes and interconnections.

In the semiconductor device manufactured in this way, it is not necessary to etch a thick oxide film as in the conventional method to form the contact hole 35, so that the time required for etching is shorter than in the conventional method. Furthermore, the interface between the metal layer 36 and the silicon substrate 2) in the sub-contact region 28 is shallower than in the past - that is, the field oxide film 2
Since it is shallower than the interface between the silicon substrate 21 and the silicon substrate 21,
The difference in level of the metal layer 36 is reduced, and breakage of one level can be prevented. Also, the pattern conversion difference becomes smaller and the 1 sub-contact bond area is L! The area of tsumugi can be small.

In the above embodiment, the sub-contact mounting 28 is formed within the chip, but if it cannot be formed within the chip, the sub-contact and GND ( Figure 4 is a partially enlarged view of Figure 3, Il! Figure 5 is A-A' in Figure 184.
It is a sectional view along the line. # In J51N, sit is silicon substrate % U is sub-contact region, 53 is N@ area as dicing line % 54 is field oxide film, 55 is polycrystalline silicon % 56 is CVD9 O8 film % 5r is as GND line It is an AA metal layer.

As described above, according to the present invention, the interface between the extraction electrode metal layer and the conductor plate in the sub-contact region is located at a shallower position than the interface between the field oxide film and the semiconductor substrate in one field region. As a result, the etching time can be shortened and the removal distance is only 1 m! It is possible to prevent discontinuous metal step breakage, thereby reducing the area required for the sub-contact region and improving the degree of integration.

[Brief explanation of the drawing]

Figure 1 (Xu ~ (h) is a cross-sectional view showing the manufacturing process of a conventional semiconductor device, Figure 2 (1!!1 (13 ~ (h) is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, Figures 1lIIa to 511I show other embodiments of this fifth invention, in which Figure 3 is a plan view of the semiconductor cube, Figure 4 is a partially enlarged view of the above-mentioned sea urchin, and Figure 5 is a partial enlarged view of the above-mentioned sea urchin. It is a sectional view taken along the line A- in the figure. z t---P pear silicon substrate, 22...84tJ
,・Membrane, 2J...81MN No. Lzs...Field oxide film, 1! ? "-kg shadow forming region U...sub-contact region b j #"-gate oxide film, 10...
Polycrystalline silicon film% 81.81...N1 area, 11
...CVD81υ. g%J14-・Conduct hole% 35-f Bucondaketohole, 36...Metal layer. Patent Attorney Takehiko E Takehiko Figure 1 Figure 1rIl Figure 2

Claims (1)

[Claims] (1) In a semiconductor device having a field region and a sub-contact region on one main surface of a semiconductor i-board, the interface between the lead electrode metal layer and the semiconductor substrate in the sub-contact region is formed between the field oxide film and the semiconductor substrate in the front and field regions. (2) - Sequentially depositing oxide A and a blurring-resistant film on a conductive semiconductor substrate, and selectively removing at least the field formation area except for the sub-contact formation area 3 of the Ilt oxidation film. , a step of forming a field oxide film by performing thermal oxidation using this oxidation-resistant film as a mask, and a step of depositing polycrystalline silicon M on the entire surface after removing the oxidation-resistant film and the oxide film. , a step of patterning the polycrystalline silicon film to selectively leave it in the area where the sub-contact is to be formed, and forming an insulating film over the entire area after patterning the polycrystalline silicon film, and forming a contact layer on which the insulating film is disposed. , forming a contact ball in the region where the sub-contact shape is to be formed, and forming the contact hole in the sub-contact shape region.
ii! By removing the polycrystalline silicon film in the region
1. A method of manufacturing a semiconductor device comprising the steps of forming a chip contact mark such as an LR wiring board, and forming an electrode lead metal layer in the sub-contact hole.