JPH05259451A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device, which can lighten the difference in level between a semiconductor substrate and an isolating oxide film, and its manufacture thereof. CONSTITUTION:An isolating oxide film 3 is made on the surface of a semiconductor substrate 4, and has a difference in level to the main surface of the semiconductor substrate 4. A MOS transistor is composed of source and drain regions 7, a gate oxide film 5, a polycrystalline silicon film 1, and a high melting point metal or a silicide layer 2. This MOS transistor is made in an element formation area. This element formation area is surrounded by the isolating oxide film 3. Moreover, the gate electrode wiring layer of the MOS transistor is made to extend above the oxide film 3 from the element formation area. The thickness of the gate electrode wiring layer on the isolating oxide layer 3 is smaller than the thickness of the gate electrode wiring layer on the element formation area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art First, a semiconductor device having a conventional field effect transistor will be described.

FIG. 19A is a plan view showing a schematic structure of a conventional semiconductor device, FIG. 19B is a sectional view taken along the line qq of FIG. 19A, and FIG. It is sectional drawing which follows the rr line of a).

Referring to these figures, semiconductor substrate 104
An isolation oxide film 103 is formed on the surface of the so as to isolate the element formation region. In the element formation region surrounded by the isolation oxide film 103, a MOS (Metal Oxide Semiconducer) is formed.
tor) A transistor is formed.

This MOS transistor includes a pair of source / drain diffusion regions 107, a gate oxide film 105, a polycrystalline silicon film 101 and a gate electrode wiring layer made of a refractory metal or its silicide layer 102. 1
The pair of source / drain diffusion regions 107 are separated oxide film 1
It is formed on the surface of the semiconductor substrate 104 separated by 03 with a predetermined distance. The source / drain diffusion region 107 is an L layer composed of two layers of high concentration and low concentration.
It has a DD (Lightly Doped Drain) structure. A polycrystalline silicon film 101 is formed on the surface of a region sandwiched by a pair of source / drain diffusion regions 107 with a gate oxide film 105 interposed. This polycrystalline silicon film 101
A refractory metal or its silicide layer 102 is formed on the surface of the. The gate electrode wiring layer composed of the polycrystalline silicon film 101 and the refractory metal or its silicide layer 102 is formed so as to vertically cross the region (element formation region) surrounded by the isolation oxide film 103. In addition, the polycrystalline silicon film 101 and the refractory metal or its silicide layer 1
02 is formed with a uniform thickness on both the isolation oxide film 103 and the element formation region. Thus, the polycrystalline silicon film 101 and the refractory metal or its silicide layer 102 are formed.
Gate sidewall oxide film 106 is formed so as to cover the sidewall of the gate electrode wiring layer made of. In this way, the MOS transistor is formed on the semiconductor substrate 104.

An element isolation diffusion region 108 is formed in the semiconductor substrate 104 below the isolation oxide film 103 to enhance the effect of electrically isolating the MOS transistor from other elements.

Next, a method of manufacturing the conventional semiconductor device shown in FIG. 19 will be described. 20 to 24 are schematic cross-sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps.
First, referring to FIG. 20, a thin oxide film 115 and a polycrystalline silicon film 111 are sequentially formed on the entire surface of the semiconductor substrate 104. A nitride film 109 is formed on the entire surface of the polycrystalline silicon film 111. A photoresist 110 is applied to the entire surface of the nitride film 109 and patterned by an exposure process or the like. Using the patterned photoresist 110 as a mask, the nitride film 109 is formed.
Are removed by etching, and the nitride film 109 is patterned into a desired shape. Impurities such as boron ions are implanted into the surface of the semiconductor substrate 104 using the patterned photoresist 110 as a mask. Then, the photoresist 110 is removed. Next, using the patterned nitride film 109 as a mask, the portion exposed from the nitride film 109 is selectively oxidized.

Referring to FIG. 21, this selective oxidation results in
An isolation oxide film 103 is formed on the surface of the semiconductor substrate 104. The surface of the isolation oxide film 103 becomes higher than the surface of the semiconductor substrate 104 because the volume increases due to oxidation. Therefore, a step is formed on the surface of the semiconductor substrate 104 and the isolation oxide film 103. Also, the element isolation diffusion region 108 is formed in the semiconductor substrate 104 below the isolation oxide film 103 by selective oxidation. After that, the nitride film 109, the polycrystalline silicon film 111 and the thin oxide film 1 are formed.
15 is etched away.

Referring to FIG. 22, a thin oxide film 105a is formed on the surface of semiconductor substrate 104. A polycrystalline silicon film 101a having a uniform resistance is formed on the entire surface of the semiconductor substrate 104 by introducing impurities at a high concentration to reduce the resistance. On the entire surface of the polycrystalline silicon film 101,
The refractory metal or its silicide layer 102a (for example, a WSi film) is formed with a uniform thickness.

Referring to FIG. 23, refractory metal or its silicide layer 1 is formed by photolithography and etching techniques.
02a and the polycrystalline silicon film 101a are sequentially removed by etching. By this etching removal, a gate electrode wiring layer composed of the polycrystalline silicon film 101 and the refractory metal or its silicide layer 102 is formed. The gate electrode wiring layer is formed so as to vertically cross the element formation region, and is formed with a uniform thickness along a step formed by the semiconductor substrate 104 and the isolation oxide film 103.

Referring to FIG. 24, impurities are implanted into semiconductor substrate 104 using refractory metal or its silicide layer 102, polycrystalline silicon film 101 and isolation oxide film 103 as a mask. As a result, low-concentration source / drain diffusion regions forming the LDD structure are formed on the surface of the semiconductor substrate 104. After that, an oxide film is formed on the entire surface of the semiconductor substrate 104. By anisotropically etching this oxide film, gate sidewall oxide film 106 is formed so as to cover the sidewalls of polycrystalline silicon film 101 and refractory metal or its silicide layer 102. By this anisotropic etching, the oxide film 105a is removed except for the lower side of the polycrystalline silicon film 101, and the gate oxide film 105 is removed.
Becomes Moreover, the surface of the semiconductor substrate 104 in the element formation region is exposed by this etching. Impurities are implanted into the surface of the semiconductor substrate 104 using the isolation oxide film 103, the gate sidewall oxide film 106, the polycrystalline silicon film 101, and the refractory metal or its silicide layer 102 as a mask. As a result, the high concentration source / drain diffusion regions forming the LDD structure are formed on the surface of the semiconductor substrate 104 with the low concentration source / drain regions.
It is formed so as to be in contact with the drain diffusion region. This low concentration and high concentration source / drain diffusion regions allow LDD
Source / drain diffusion regions 107 having a structure are formed.

The conventional semiconductor device is constructed and manufactured as described above.

[0013]

In the conventional semiconductor device as described above, as shown in FIG. 22, the polycrystalline silicon film 101a is composed of the semiconductor substrate 104 and the isolation oxide film 10.
It is formed on the surface of No. 3 with a uniform thickness. Further, a refractory metal or its silicide layer 102a is formed on the surface of the polycrystalline silicon film 101a with a uniform thickness. Therefore, a surface step A corresponding to the step between the isolation oxide film 103 and the semiconductor substrate 104 is formed in the refractory metal or the silicide layer 102a thereof. In this way, if there is a step on the surface of the refractory metal or its silicide layer 102a, these 2
When the gate electrode wiring layer is formed by etching away the layer, the following problems occur.

22 and 23, in order to form gate electrode wiring layers 101 and 102, a photoresist is first applied on the surface of refractory metal or its silicide layer 102a. This photoresist is patterned by exposing it to light. However,
A step is formed on the surface of the refractory metal or its silicide layer 102a under the photoresist. If there is a step in the lower layer of the photoresist, the behavior such as light reflection on the surface of the refractory metal or the silicide layer 102a thereof under the photoresist becomes complicated when the photoresist is exposed. This exposes the photoresist except the desired portion. Further, since the resist film thickness varies depending on the level difference of the lower layer, the actual exposure amount changes and the unevenness due to the exposure increases. Thus, if there is a step in the lower layer of the photoresist, it becomes difficult to expose the photoresist to a desired shape when the photoresist is finely patterned. Therefore, there is a problem that it is difficult to perform fine processing of the gate electrode wiring layer with high accuracy.

Further, as shown in FIG. 19C, a surface step A occurs in the refractory metal or its silicide layer 102, and the gate electrode wiring layer 10 on the isolation oxide film 103.
When the film thicknesses of 1 and 102 increase, the gate electrode wiring layer 1
A large surface step is also generated in the insulating layer formed above 01 and 102. Therefore, there is also a problem that it becomes difficult to reflow (flatten) the surface of the insulating layer.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the surface step of the gate electrode wiring layer is small, and a manufacturing method thereof.

[0017]

A semiconductor device according to the present invention according to claim 1 comprises a semiconductor substrate, an isolation oxide film,
And a field effect transistor. The semiconductor substrate has a main surface. The isolation oxide film is formed on the main surface of the semiconductor substrate and has a step with respect to the main surface of the semiconductor substrate. The field effect transistor is formed in an element formation region surrounded by an isolation oxide film. Further, this field effect transistor includes a gate wiring layer formed so as to extend from the element formation region onto the isolation oxide film. The film thickness of the gate wiring layer on the isolation oxide film is smaller than the film thickness of the gate wiring layer on the element formation region.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the oxide film is formed on the main surface of the semiconductor substrate, and the polycrystalline silicon film is formed on the oxide film. The semiconductor substrate and the polycrystalline silicon film are selectively oxidized, and an isolation oxide film is formed so as to surround the polycrystalline silicon film and increase the thickness of the oxide film. Impurities are introduced into the polycrystalline silicon film surrounded by the isolation oxide film to form a first conductive layer. Separate oxide film and first
A second conductive layer is formed on the conductive layer of. The first conductive layer and the second conductive layer are selectively removed to form a gate wiring layer.

According to a preferred aspect of the method for manufacturing a semiconductor device of the present invention described in claim 3, in the step of forming the first conductive layer, the height from the main surface of the semiconductor substrate is substantially equal to that of the isolation oxide film. A step of selectively forming a second polycrystalline silicon film only on the polycrystalline silicon film so as to have the same height, and a step of introducing impurities into the polycrystalline silicon film and the second polycrystalline silicon film. Is included.

[0020]

According to the semiconductor device of the first aspect, the gate wiring layer is formed so as to extend from the element forming region onto the isolation oxide film. Further, the film thickness of the gate wiring layer on the isolation oxide film is smaller than the film thickness of the gate wiring layer on the element formation region. Therefore, the gate wiring layer alleviates the step formed by the semiconductor substrate and the isolation oxide film. In this way, the film thickness of the gate wiring layer on the isolation oxide film can be made thinner than that on the element formation region, and the step at the boundary portion between the semiconductor substrate and the isolation oxide film of the gate wiring layer is relaxed, Even in the insulating layer formed on the gate wiring layer, the surface step difference is small. Therefore, reflow becomes easy.

According to the semiconductor device manufacturing method of the second aspect, first, the isolation oxide film is formed so as to surround the polycrystalline silicon film and increase the thickness of the oxide film. Impurities are introduced into this polycrystalline silicon film to form a first conductive layer. In this state, the isolation oxide film has a step with respect to the main surface of the semiconductor substrate. However, in the region surrounded by the isolation oxide film, the first conductive layer is formed on the main surface of the semiconductor substrate. The first conductive layer alleviates the step between the isolation oxide film and the main surface of the semiconductor substrate, and reduces the surface step. As a result, the surface step difference between the first conductive layer and the second conductive layer formed on the isolation oxide film is also reduced. In this way, since the surface level difference of the second conductive layer becomes small, when the photoresist coated on the surface of the second conductive layer is exposed to light, the behavior such as light reflection in the photoresist becomes complicated. Can be suppressed. Therefore, the photoresist can be finely patterned, and the gate wiring layer can be finely processed with high precision.

Further, the step of removing the polycrystalline silicon film and the oxide film after forming the isolation oxide film by the selective oxidation can be omitted. Therefore, the manufacturing process can be simplified.

According to a preferred method of manufacturing a semiconductor device of the present invention as defined in claim 3, the polycrystalline silicon film is formed on the polycrystalline silicon film so that the height from the main surface of the semiconductor substrate is substantially the same as that of the isolation oxide film. The second polycrystalline silicon film is selectively formed only on the. Therefore, almost no step is formed on the surface formed by the isolation oxide film and the first conductive layer.
As a result, there is almost no surface step even on the second conductive layer formed on the first conductive layer and the isolation oxide film. Therefore, when a photoresist is applied on the surface of the second conductive layer and exposed to light, complication of behavior such as reflection of light in the photoresist is suppressed. Therefore, fine patterning of the photoresist becomes possible, and fine processing of the gate wiring with high precision becomes possible.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A is a plan view schematically showing the structure of a semiconductor device according to the first embodiment of the present invention, FIG.
1A is a sectional view taken along the line mm of FIG. 1A, and FIG. 1C is a sectional view taken along the line nn of FIG. Referring to these drawings, isolation oxide film 3 is formed on the surface of semiconductor substrate 4 so as to surround the element formation region. A MOS transistor is formed in an element forming region surrounded by the isolation oxide film 3.

This MOS transistor includes a pair of source / drain diffusion regions 7, a gate oxide film 5, a polycrystalline silicon film 1 and a gate electrode wiring layer made of a refractory metal or its silicide layer 2. The pair of source / drain diffusion regions 7 are formed on the surface of the semiconductor substrate 4 separated by the separation oxide film 3 with a predetermined distance therebetween. The source / drain diffusion region 7 has an LDD structure having a two-layer structure of low concentration and high concentration. This one
A polycrystalline silicon film 1 is formed on the surface of a region sandwiched by a pair of source / drain diffusion regions 7 with a gate oxide film 5 interposed. The polycrystalline silicon film 1 is formed only in a region (element forming region) surrounded by the isolation oxide film 3. A refractory metal or its silicide layer 2 is formed on the surface of the polycrystalline silicon film 1.
The refractory metal or its silicide layer 2 is formed with a uniform thickness on both the element formation region and the isolation oxide film 3. The gate electrode wiring layer including the polycrystalline silicon film 1 and the refractory metal or the silicide layer 2 thereof has a relatively large thickness on the element formation region and a relatively thin film thickness on the isolation oxide film 3. Gate sidewall oxide film 6 is formed so as to cover the sidewalls of gate electrode wiring layers 1 and 2. The MOS transistor is configured in this way.

Element isolation diffusion regions 8 are formed in the semiconductor substrate 4 below the isolation oxide film 3 to enhance the effect of electrically isolating the MOS transistor from other elements.

Next, a method of manufacturing the semiconductor substrate according to the first embodiment of the present invention will be described.

2 to 6 are schematic sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps. First, referring to FIG. 2, thin oxide film 5a and polycrystalline silicon film 1 are sequentially formed on the entire surface of semiconductor substrate 4. A nitride film 9 is formed on the entire surface of this polycrystalline silicon film 1. A photoresist 1 is formed on the surface of the nitride film 9.
0 is applied and patterned into a desired shape by exposure processing or the like. Using the patterned photoresist 10 as a mask, the nitride film 9 is removed by etching into a desired shape. By this etching, the nitride film 9 is patterned into a desired shape. Then, boron ions or the like are implanted into the surface of the semiconductor substrate 4 using the patterned photoresist 10 as a mask. Then, the photoresist 10 is removed. Next, the patterned nitride film 9 is used as a mask to selectively oxidize the region not covered with the nitride film 9.

Referring to FIG. 3, isolation oxide film 3 is formed on the surface of semiconductor substrate 4 by this selective oxidation. The surface of the isolation oxide film 3 is higher than the surface of the semiconductor substrate 4 because the volume increases due to oxidation. After this, the nitride film 9
Are removed. In this state, polycrystalline silicon film 1 is distributed only in the region surrounded by isolation oxide film 3 (element forming region).

Referring to FIG. 4, high concentration impurities are introduced into polycrystalline silicon film 1. The introduction of this impurity lowers the resistance of the polycrystalline silicon film 1. WSi is formed on the entire surfaces of the polycrystalline silicon film 1 and the isolation oxide film 3.
A refractory metal such as a film or its silicide 2 is formed with a substantially uniform thickness. At this time, since the step formed by the semiconductor substrate 4 and the isolation oxide film 3 is relaxed by the polycrystalline silicon film 1, the refractory metal or its silicide layer 2 is formed.
The surface level difference B is relatively small.

Referring to FIG. 5, the refractory metal or its silicide layer 2 is formed by photolithography and etching techniques.
Polycrystalline silicon film 1 and thin oxide film 5a are sequentially patterned. By this patterning, the gate electrode wiring layer made of the polycrystalline silicon film 1 and the refractory metal or its silicide layer 2 and the gate oxide film 5 are formed. In the above photolithography process, the photoresist applied on the surface of the refractory metal or its silicide layer 2 is exposed to light with a relatively small surface step B of the lower refractory metal or its silicide layer 2. Therefore, it can be applied relatively accurately.

Referring to FIG. 6, impurities are introduced into the surface of semiconductor substrate 4 using refractory metal or its silicide layer 2, polycrystalline silicon film 1, three layers of gate oxide film 5 and isolation oxide film 3 as a mask. To be done. By introducing this impurity or the like, low-concentration source / drain diffusion regions forming the LDD structure are formed on the surface of the semiconductor substrate 4. next,
An oxide film is formed on the entire surface of the semiconductor substrate 4, and this oxide film is anisotropically etched. As a result, the gate sidewall oxide film 6 is formed so as to cover the sidewall of the gate electrode wiring layer formed of the polycrystalline silicon film 1 and the refractory metal or the silicide layer 2 thereof. Refractory metal or its silicide layer 2, polycrystalline silicon film 1, and gate oxide film 3
Impurities are introduced into the surface of the semiconductor substrate 4 using the layer, the isolation oxide film 3 and the gate sidewall oxide film 6 as a mask. Due to the introduction of the impurities, LDD is formed on the surface of the semiconductor substrate 4.
The high-concentration source / drain diffusion regions forming the structure are formed in contact with the low-concentration source / drain diffusion regions. The high-concentration and low-concentration source / drain diffusion regions form source / drain diffusion regions 7 having an LDD structure.

The semiconductor device according to the first embodiment of the present invention is constructed and manufactured as described above.

In the semiconductor device according to the first embodiment described above, as shown in FIG. 1, the gate electrode wiring layer has a relatively large film thickness on the element forming region, and the isolation oxide film 3 is formed.
Above it is relatively thin. Therefore, it is possible to reduce the thickness of the gate electrode wiring layer on the element isolation oxide film 3. Therefore, even in the insulating layer formed on the gate electrode wiring layer, the surface step can be reduced. Therefore, it becomes easy to reflow the insulating layer formed on the upper layer.

In the method of manufacturing a semiconductor device according to the first embodiment described above, polycrystalline silicon film 1 is formed only in a region surrounded by isolation oxide film 3 as shown in FIG. Therefore, the step formed by semiconductor substrate 4 and isolation oxide film 3 is relaxed by polycrystalline silicon film 1. Therefore, as shown in FIG. 4, the surface step B of the refractory metal or its silicide layer 2 formed on the entire surfaces of the polycrystalline silicon film 1 and the isolation oxide film 3 is also small. Since the surface step B of this refractory metal or its silicide layer 2 becomes small, when the photoresist applied on the surface of this refractory metal or its silicide layer 2 is exposed to light, reflection of light in the photoresist, etc. The behavior of the photoresist is suppressed from becoming complicated, which facilitates accurate patterning of the photoresist.

Next, a second embodiment of the present invention will be described. FIG. 7 is a diagram schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention, which corresponds to a cross section taken along line MM of FIG. FIG. 8 is a schematic diagram showing the configuration of a semiconductor device according to the second embodiment of the present invention, which is shown in FIG.
It is a figure corresponding to the cross section along the nn line of. With reference to these drawings, in the semiconductor device according to the second embodiment,
The second polycrystalline silicon film 1a is formed below the refractory metal or the silicide layer 2 of the refractory metal of the embodiment. This second polycrystalline silicon film 1
The a is formed on the isolation oxide film 3 and the polycrystalline silicon film 1 with a uniform thickness. The rest of the configuration is the same as that of the first embodiment of the present invention, so its explanation is omitted.

Next, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described. After the steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention shown in FIG. 3, on the surfaces of isolation oxide film 3 and polycrystalline silicon film 1,
Second polycrystalline silicon film 1a is formed with a substantially uniform thickness. Since the subsequent steps are substantially the same as those in the first embodiment of the present invention, the description thereof will be omitted.

Generally, the adhesion between the oxide film and the metal film is poor. However, in the semiconductor device according to the second embodiment, the second polycrystalline silicon film 1a is interposed between the isolation oxide film 3 and the refractory metal or its silicide layer 2. Therefore, the adhesion between the films can be improved.

Furthermore, in the second embodiment of the present invention, the thickness of the polycrystalline silicon film is the same as that of the first polycrystalline silicon film 1 and the second polycrystalline silicon film.
Can be controlled by two layers of the polycrystalline silicon film 1a. Therefore, in the step shown in FIG. 3, the polycrystalline silicon film 1 is formed to have an optimum film thickness for selective oxidation, and the second polycrystalline silicon film 1a is formed to have an optimum film thickness for the gate electrode wiring layer. You can Therefore, the degree of freedom in structural design is increased.

In addition, in the semiconductor device according to the second embodiment of the present invention described above, the second polycrystalline silicon film 1a is formed.
After forming, the refractory metal or its silicide layer 2 is formed. However, it is also possible to form the gate electrode wiring layer of only the polycrystalline silicon films 1 and 1a without forming the refractory metal or the silicide layer 2 thereof.

In the method of manufacturing a semiconductor device according to the second embodiment of the present invention, after forming the second polycrystalline silicon film 1a, the gate electrode wiring layer of only the polycrystalline silicon films 1 and 1a is formed. After the processing of the gate electrode wiring layer, the formation of the gate sidewall oxide film 6 or the formation of the source / drain diffusion regions 7, the entire surface of the semiconductor substrate 4 is
A refractory metal such as Ti is deposited. Thereafter, heat treatment may be applied to form a silicide structure in the polycrystalline silicon films 1 and 1a of the gate electrode wiring layer and the silicon surface layer of the source / drain diffusion regions 7.

Next, a third embodiment of the present invention will be described. FIG. 9A is a plan view schematically showing the structure of a semiconductor device according to the third embodiment of the present invention, and FIG.
FIG. 9A is a cross-sectional view taken along line o-o of FIG.
3 is a cross-sectional view taken along line pp of FIG. Referring to these drawings, isolation oxide film 3 is formed on the surface of semiconductor substrate 54 so as to surround the element formation region. A MOS transistor is formed in an element formation region surrounded by the isolation oxide film 3.

This MOS transistor includes a pair of source / drain diffusion regions 57, a gate oxide film 55 and a first
Polycrystalline silicon film 51 and second polycrystalline silicon film 61
And a gate electrode wiring layer made of a refractory metal or a silicide layer 52 thereof. A pair of source / drain diffusion regions 57 are formed in the element formation region with a predetermined distance. This source / drain diffusion region 57
Has an LDD structure consisting of a low-concentration and high-concentration two-layer structure. A first polycrystalline silicon film 51 and a second polycrystalline silicon film 61 are formed on the surface of the region sandwiched by the pair of source / drain diffusion regions 57 with a gate oxide film 55 interposed. .. The first polycrystalline silicon film 51 and the second polycrystalline silicon film 61 are separated by the isolation oxide film 53.
Are formed only in the region surrounded by the element, that is, in the element formation region. The heights of the second polycrystalline silicon film 61 and the isolation oxide film 53 from the semiconductor substrate 54 are almost the same. Therefore, the isolation oxide film 53 and the second polycrystalline silicon film 61 are formed.
Almost no surface step is formed on the surface constituted by. A refractory metal or its silicide layer 52 is formed with a uniform thickness on the surfaces of the second polycrystalline silicon film 61 and the isolation oxide film 53 having almost no surface step. A gate sidewall oxide film 56 is formed so as to cover the sidewalls of the gate electrode wiring layer formed of the first and second polycrystalline silicon films 51 and 61 and the refractory metal or the silicide layer 52 thereof.
Are formed. The MOS transistor is formed in this way.

An element isolation diffusion region 58 is formed in the semiconductor substrate 54 below the isolation oxide film 53 to enhance the effect of electrically isolating the MOS transistor from other elements.

Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described.

10 to 15 are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention in the order of steps. First, referring to FIG. 10, a thin oxide film 55a and a first polycrystalline silicon film 51 are sequentially formed on the entire surface of the semiconductor substrate 54. A nitride film 59 is formed on the entire surface of the polycrystalline silicon film 51. A photoresist 60 is applied on the surface of the nitride film 59 and patterned into a desired shape by exposure processing or the like. Using the patterned photoresist 60 as a mask, the nitride film 59 is removed by etching. By this etching,
The nitride film 59 is patterned into a desired shape. Boron ions or the like are implanted into the surface of the semiconductor substrate 54 using the patterned photoresist 60 as a mask. Then, the photoresist 60 is removed. Using the patterned nitride film 59 as a mask, the region not covered with the nitride film 59 is selectively oxidized.

With reference to FIG. 11, by this selective oxidation,
An isolation oxide film 53 is formed on the surface of the semiconductor substrate 54. The surface of the isolation oxide film 53 is higher than the surface of the semiconductor substrate 104 because the volume increases due to oxidation. After that, the nitride film 59 is removed.

Referring to FIG. 12, second polycrystalline silicon film 61 is selectively grown only on the surface of first polycrystalline silicon film 51 by the selective CVD method. This choice C
In the VD method, for example, silane (SiH
₄ ) System gas is used. In this selective CVD method, the conditions for growing the second polycrystalline silicon film 61 are selected so that the height from the semiconductor substrate 54 is almost the same as that of the isolation oxide film 53. As a result, the surface formed by the isolation oxide film 53 and the second polycrystalline silicon film 61 has a shape having almost no surface step. High-concentration impurities are introduced into both the first polycrystalline silicon film 51 and the second polycrystalline silicon film 61. By introducing this impurity, the resistance of the first and second polycrystalline silicon films 51 and 61 is lowered.

Referring to FIG. 13, isolation oxide film 53 and second polycrystalline silicon film 6 having almost no surface step are formed.
A refractory metal such as a WSi film or a silicide layer 52 thereof is formed on the entire surface formed by 1. On the surface of the refractory metal or the silicide layer 52 thereof, there is no step on the surface formed of the lower isolation oxide film 53 and the second polycrystalline silicon film 61, so that there is almost no step.

Referring to FIG. 14, refractory metal or its silicide layer 5 is formed by photolithography and etching techniques.
2. The second and first polycrystalline silicon films 61 and 51 are sequentially patterned. By this patterning, a gate electrode wiring layer composed of the first and second polycrystalline silicon films 51 and 61 and the refractory metal or the silicide layer 52 thereof is formed.

Referring to FIG. 15, first and second polycrystalline silicon films 51 and 61, refractory metal or its three silicide layers 52, and isolation oxide film 53 are used as a mask on the surface of semiconductor substrate 4. Impurities are introduced. By introducing this impurity, low-concentration source / drain diffusion regions forming the LDD structure are formed on the surface of the semiconductor substrate 4. Next, an oxide film is formed on the entire surface of the semiconductor substrate 54, and this oxide film is anisotropically etched. By this etching, the gate sidewall oxide film 56 is formed so as to cover the sidewalls of the gate electrode wiring layer formed of the first and second polycrystalline silicon films 51 and 61 and the refractory metal or the silicide layer 2 thereof. In addition, the oxide film 55a is formed by this etching.
Becomes a gate oxide film 55. Gate oxide film 55, first and second polycrystalline silicon films 51 and 61, four layers of refractory metal or its silicide layer 52, isolation oxide film 53 and gate sidewall oxide film 56 are used as masks on the surface of semiconductor substrate 54. Impurities are introduced. By introducing this impurity, the high-concentration source / drain diffusion regions forming the LDD structure are formed on the surface of the semiconductor substrate 4 so as to be in contact with the low-concentration source / drain diffusion regions. The high-concentration and low-concentration source / drain diffusion regions form source / drain diffusion regions 57 having an LDD structure.

The semiconductor device according to the third embodiment of the present invention is constructed and manufactured as described above.

In the semiconductor device according to the third embodiment of the present invention, as in the first embodiment, the gate electrode wiring layer has a large thickness on the element formation region and a thickness on the isolation oxide film 53. Has a relatively thin configuration.
Therefore, the same effect as that of the first embodiment is exhibited. That is, the reflow of the insulating layer formed on the gate electrode wiring layer can be easily performed.

Further, in the method of manufacturing the semiconductor device according to the third embodiment, as shown in FIG.
The second polycrystalline silicon films 51 and 61 are formed only in the region surrounded by the isolation oxide film 3, and the second polycrystalline silicon film 61 has a height almost equal to that of the isolation oxide film 53. There is. As described above, since the heights of the surfaces of the isolation oxide film 53 and the second polycrystalline silicon film 61 are almost the same, the surfaces formed by the isolation oxide film 53 and the second polycrystalline silicon film 61 are almost the same. No surface step occurs. Therefore, FIG.
As shown in FIG. 7, the refractory metal or its silicide layer 2 formed on the entire surfaces of the isolation oxide film 53 and the second polycrystalline silicon film 61 has almost no surface step, and a substantially flat surface is obtained. .. Therefore, when a photoresist is applied onto the surface of the second polycrystalline silicon film 61 and exposed to light, the behavior such as reflection of light in the photoresist can be prevented from becoming complicated. Therefore, the photoresist can be finely patterned, and the fine processing of the gate wiring can be performed with high precision.

Next, a fourth embodiment of the present invention will be described. FIG. 16 is a diagram schematically showing the configuration of the semiconductor device according to the fourth exemplary embodiment of the present invention, which corresponds to the cross section taken along line o--o of FIG. Further, FIG. 17 shows a fourth embodiment of the present invention.
9 schematically shows a configuration of a semiconductor device in the embodiment of FIG.
It is a figure corresponding to the cross section which follows the pp line of (a). With reference to these figures, in the semiconductor device according to the fourth embodiment, a third polycrystalline silicon film 61a is formed under the refractory metal or the silicide layer 52 of the semiconductor device according to the third embodiment. Has become. The fourth polycrystalline silicon film 61a is formed with a uniform thickness on the isolation oxide film 53 and the element forming region. The rest of the configuration is almost the same as that of the first embodiment of the present invention, and therefore its explanation is omitted.

Next, a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described.

After the step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention shown in FIG. 12, a third oxide film 53 and a second polycrystalline silicon film 61 are formed on the entire surface of the third oxide film 53.
The polycrystalline silicon film 61a is formed with a substantially uniform thickness. W is formed on the entire surface of the third polycrystalline silicon film 61a.
A refractory metal such as a Si film or a silicide layer 52 thereof is formed. The refractory metal or its silicide layer 52 and the third, second, and first polycrystalline silicon films 61a, 61, 51 are sequentially etched and removed by photolithography and etching techniques, and the state shown in FIG. 18 is obtained. Since the subsequent steps are substantially the same as those in the third embodiment of the present invention, the description thereof will be omitted.

Generally, the adhesion between the oxide film and the metal film is poor. However, in the semiconductor device according to the fourth embodiment, the third polycrystalline silicon film 61a is interposed between the isolation oxide film 53 and the refractory metal or its silicide layer 52. Therefore, the adhesion between the films can be improved.

Further, in the semiconductor device according to the fourth embodiment of the present invention, the refractory metal or its silicide layer 52 is formed after forming the third polycrystalline silicon film 61a. However, without forming the refractory metal or the silicide layer 52 thereof, the gate electrode wiring layer may be formed of only the polycrystalline silicon film including the first, second and third polycrystalline silicon films 51, 61 and 61a. It is possible.

In addition, in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, after forming the third polycrystalline silicon film 61a, the gate electrode wiring layer including only the polycrystalline silicon film is formed. After the processing of the gate electrode wiring layer or the formation of the gate sidewall oxide film 56 or the source.
After forming the drain diffusion region 57, a refractory metal such as Ti is deposited on the entire surface of the semiconductor substrate 54. After this,
By performing heat treatment, a silicide structure may be formed in the polycrystalline silicon films 61a, 60, 51 of the gate electrode wiring layer and the silicon surface layer of the source / drain diffusion region 57.

[0062]

According to the semiconductor device of the first aspect,
The gate wiring layer of the field effect transistor is formed so as to extend from the element formation region onto the isolation oxide film. Further, the film thickness of the gate wiring layer on the isolation oxide film is smaller than the film thickness of the gate wiring layer in the element formation region. Therefore, the step of the isolation oxide film with respect to the main surface of the semiconductor substrate is relaxed. Therefore, when the insulating layer is formed on the upper layer, the surface step difference of the insulating layer is also reduced. Therefore, reflow can be easily performed.

According to the method of manufacturing a semiconductor device of the second aspect, first, the isolation oxide film is formed so as to surround the polycrystalline silicon film and increase the thickness of the oxide film. Therefore, when processing the gate wiring layer, the step difference in the lower layer of the photoresist applied is reduced. Therefore,
The photoresist can be finely patterned, and the gate wiring layer can be finely processed with high precision.

Further, there is no need for a step of removing the polycrystalline silicon film and the oxide film after forming the isolation oxide film. Therefore, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a plan view (a) schematically showing a configuration of a semiconductor device according to a first embodiment of the present invention, a cross-sectional view (b) taken along line mm of FIG. 1 (a), and FIG. (B) is a cross-sectional view (c) taken along line nn in FIG.

FIG. 2 is a schematic cross-sectional view taken along line mm of FIG. 1A, showing a first step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view taken along the line MM of FIG. 1A, showing a second step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view taken along line mm of FIG. 1A, showing a third step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view taken along line mm of FIG. 1A, showing a fourth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view taken along line mm of FIG. 1A, showing a fifth step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a diagram schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention, which corresponds to a cross section taken along line MM of FIG.

FIG. 8 is a diagram schematically showing a configuration of a semiconductor device according to a second embodiment of the present invention, which corresponds to a cross section taken along line nn of FIG.

FIG. 9 is a plan view (a) schematically showing a configuration of a semiconductor device according to a third embodiment of the present invention, a sectional view (b) taken along line oo of FIG. 9 (a), and FIG. FIG. 4C is a sectional view (c) taken along the line pp of FIG.

FIG. 10 is a schematic cross-sectional view taken along the line oo of FIG. 9A, showing a first step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view taken along the line oo of FIG. 9A, showing a second step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view taken along the line oo of FIG. 9A, showing a third step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view taken along the line oo of FIG. 9A, showing a fourth step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view taken along the line oo of FIG. 9A, showing a fifth step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view taken along the line o-o of FIG. 9A, showing a sixth step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a diagram schematically showing a configuration of a semiconductor device according to a fourth embodiment of the present invention, which corresponds to a cross section taken along line o-o of FIG.

FIG. 17 is a diagram schematically showing a configuration of a semiconductor device according to a fourth exemplary embodiment of the present invention, which corresponds to a cross section taken along the line pp of FIG. 9A.

FIG. 18 is a diagram corresponding to a cross section taken along line o-o of FIG. 9A, which shows the characteristic steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 19 is a plan view (a) schematically showing the configuration of a conventional semiconductor device, a sectional view (b) taken along the line qq of FIG. 19 (a), and a line r-r of FIG. 19 (a). It is sectional drawing (c) which follows.

FIG. 20 is a sectional view taken along the line qq of FIG. 19A, showing a first step of the conventional method for manufacturing a semiconductor device.

FIG. 21 is a sectional view taken along the line qq of FIG. 19A, showing a second step of the conventional method for manufacturing a semiconductor device.

FIG. 22 is a sectional view taken along the line qq of FIG. 19A, showing a third step of the conventional method for manufacturing a semiconductor device.

FIG. 23 is a sectional view taken along the line qq of FIG. 19A, showing a fourth step of the conventional method for manufacturing a semiconductor device.

FIG. 24 is a sectional view taken along the line qq of FIG. 19A, showing a fifth step of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Polycrystalline Silicon Film 1a Second Polycrystalline Silicon Film 2,52 Refractory Metal or its Silicide Layer 3,53 Separation Oxide Film 4,54 Semiconductor Substrate 5,55 Gate Oxide Film 7,57 Source / Drain Diffusion Region 51 First polycrystalline silicon film 61 Second polycrystalline silicon film 61a Third polycrystalline silicon film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 7377-4M 29/78 301 X

Claims (3)

[Claims] 1. A semiconductor substrate having a main surface, an isolation oxide film formed on the main surface of the semiconductor substrate and having a step with respect to the main surface of the semiconductor substrate, and an element surrounded by the isolation oxide film. A field effect transistor formed in a formation region, wherein the field effect transistor includes a gate wiring layer formed to extend from the element formation region onto the isolation oxide film, In the semiconductor device, the film thickness of the gate wiring layer is smaller than the film thickness of the gate wiring layer on the element formation region. 2. A step of forming an oxide film on a main surface of a semiconductor substrate and forming a polycrystalline silicon film on the oxide film; and selectively oxidizing the semiconductor substrate and the polycrystalline silicon film. A step of forming an isolation oxide film so as to surround the polycrystalline silicon film and increase the thickness of the oxide film, and impurities are added to the polycrystalline silicon film surrounded by the isolation oxide film. Forming the first conductive layer, forming a second conductive layer on the isolation oxide film and the first conductive layer, and forming the first conductive layer and the second conductive layer And a step of selectively removing the layer to form a gate wiring layer. 3. The step of forming the first conductive layer is performed only on the polycrystalline silicon film so that the height from the main surface of the semiconductor substrate is substantially the same as the isolation oxide film. 3. The manufacturing of a semiconductor device according to claim 2, including a step of selectively forming a second polycrystalline silicon film, and a step of introducing impurities into the polycrystalline silicon film and the second polycrystalline silicon film. Method.