JPS5831554A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5831554A JPS5831554A JP12996181A JP12996181A JPS5831554A JP S5831554 A JPS5831554 A JP S5831554A JP 12996181 A JP12996181 A JP 12996181A JP 12996181 A JP12996181 A JP 12996181A JP S5831554 A JPS5831554 A JP S5831554A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- etched
- semiconductor device
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置を構成する各素子間の絶縁分離の
形成方法に関するものであり、絶縁分離形成時に半導体
基板に誘起される欠陥が少なく、低消費電力で高密度か
つ高速な半導体装置を製造することに適した絶縁分離形
成方法を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming insulation separation between each element constituting a semiconductor device, and the present invention relates to a method for forming insulation separation between each element constituting a semiconductor device. The present invention also provides an insulation isolation formation method suitable for manufacturing high-speed semiconductor devices.
従来、バイポーラ形半導体装置の各素子間の分離には一
般的にPN接合分離が用いられている。Conventionally, PN junction isolation has generally been used to isolate each element of a bipolar semiconductor device.
しかし、PN接合分離では、接合リーク電流、接合容量
、および、深い分離層を形成するときの拡散不純物の横
方内拡がりのため、低消費電力化・高速化および高密度
化のさまたげとなっていた。However, in PN junction isolation, junction leakage current, junction capacitance, and lateral inward spread of diffused impurities when forming a deep isolation layer impede lower power consumption, higher speed, and higher density. Ta.
そこで、PN接合分離にかわって絶縁分離が用いられる
ようになってきた。第1図に゛従って従来考案されてい
る絶縁分離の方法を説明する。半導体基板1に素子分離
領域に相当する部分である凹部2を選択的に形成しく第
1図a)、しかる後、凹部を絶縁物、例えば二酸化硅素
(S 102 )で埋めるものである。Sio2で凹部
を埋める場合、通常、基板シリコンを熱酸化する方法が
とられ、第1図すのごと(51023を形成し、絶縁分
離がおこなわれる。しかし、この方法によると熱酸化に
よる体積膨張のため、分離された領域に大きな応力が加
わり欠陥が多数発生し、素子特性が劣化する。Therefore, insulation isolation has come to be used instead of PN junction isolation. A conventional insulation isolation method will be explained with reference to FIG. A recess 2 corresponding to an element isolation region is selectively formed in a semiconductor substrate 1 (FIG. 1a), and then the recess is filled with an insulating material, such as silicon dioxide (S 102 ). When filling the recess with Sio2, a method is usually used to thermally oxidize the substrate silicon, forming a layer 51023 as shown in Figure 1 (51023) and performing insulation isolation. However, with this method, the volume expansion due to thermal oxidation Therefore, large stress is applied to the separated regions, many defects occur, and device characteristics deteriorate.
また、熱酸化膜の厚さ分だけ素子形成領域が狭くなるの
で、厚い熱酸化膜の必要な場合には、半導体装置の高密
度化に適さない方法となる。Furthermore, since the element formation region becomes narrower by the thickness of the thermal oxide film, this method is not suitable for increasing the density of semiconductor devices when a thick thermal oxide film is required.
熱酸化膜による絶縁分離の上記欠点を無くするため凹部
をシリカフィルムで埋める方法が考えられる。しかしシ
リカフィルムを通常行なわれているスピンオン法で塗布
する場合、凹部が微細パター7T:深すの深い時は、シ
リカフィルムが凹部ノ底部にまで到達せず気泡がたまる
ということが起こ9やスイ。また、凹部の幅が広い場合
には、凹部全体を埋めかつ平坦なシリカフィルムの膜を
得るには、1度のスピンオンでは困難であり、複数回塗
布を行なう必要がある。In order to eliminate the above-mentioned drawbacks of insulation isolation using a thermal oxide film, a method of filling the recesses with a silica film can be considered. However, when applying a silica film using the commonly used spin-on method, if the recesses are deep, the silica film may not reach the bottom of the recesses and air bubbles may accumulate. . Further, when the width of the recess is wide, it is difficult to fill the entire recess and obtain a flat silica film by one spin-on operation, and it is necessary to apply the silica film multiple times.
本発明は以上の様な従来法の欠点を無くした低消費室゛
力で高密度かつ高速な半導体装置の製造に適した絶縁分
離形成方法を提供するものである。The present invention provides an insulating isolation forming method which eliminates the above-mentioned drawbacks of the conventional method and is suitable for manufacturing high-density, high-speed semiconductor devices with low consumption space and energy.
本発明は以下に述べる様な工程より成り立っている。The present invention consists of the steps described below.
半導体基板に選択的に感光性樹脂パターンを形成し、反
応性スパッタエツチング法あるいはイオンミリング等に
より、前記半導体基板を食刻し、凹部を形成する。感光
性樹脂を除去した後、有機溶媒に溶かしたシリコン有機
化合物の溶液中に外部より超音波を加えながら基板を浸
し、基板全面にシリカフィルムを塗布する。その後高温
酸素雰囲気中で熱処理を行ないシリカフィルムを二酸化
硅素膜とする。次に前記半導体基板凸部に形成された二
酸化硅素膜を除去した後、通常の方法により半導体素子
を製造する。A photosensitive resin pattern is selectively formed on a semiconductor substrate, and the semiconductor substrate is etched by reactive sputter etching or ion milling to form recesses. After removing the photosensitive resin, the substrate is immersed in a solution of a silicon organic compound dissolved in an organic solvent while applying ultrasonic waves from the outside, and a silica film is applied to the entire surface of the substrate. Thereafter, heat treatment is performed in a high temperature oxygen atmosphere to convert the silica film into a silicon dioxide film. Next, after removing the silicon dioxide film formed on the convex portion of the semiconductor substrate, a semiconductor element is manufactured by a conventional method.
本発明の特徴は、半導体基板に選択的に食刻形成された
凹部をおおって、シリカフィルムを全面に塗布する方法
にある。すなわちシリコン有機化合物の溶液中に半導体
基板を浸し、外部より超音波を加える方法により、シリ
カフィルムを基板全面に塗布すれば、基板に食刻された
凹部をすべて埋めつくし、しかも平坦にシリカフィルム
が塗布されるというものである。The present invention is characterized by a method of applying a silica film to the entire surface of the semiconductor substrate, covering the recesses selectively etched into the semiconductor substrate. In other words, if a semiconductor substrate is immersed in a silicon organic compound solution and a silica film is applied to the entire surface of the substrate by applying ultrasonic waves from the outside, it will fill all the recesses etched into the substrate and the silica film will be flat. It is applied.
以下に本発明の実施例について第2図を用いて説明する
。Examples of the present invention will be described below with reference to FIG.
一導電形Si 半導体基板11上に選択的に反対導電形
不純物層12を形成する。全面に前記半導体基板と反対
導電形のSi 半導体13をエピタキシャル成長させる
。感光性樹脂パターン14を選択的に形成した後、CF
4ガス雰囲気でのスパッタエツチング法により前記エピ
タキシャル層を食刻し凹部16を形成する。次に感光性
樹脂膜14を除去し、高温酸素雰囲気中で二酸化硅素膜
16を薄く、例えば6oO〜3000Aの膜厚に形成す
る。An impurity layer 12 of an opposite conductivity type is selectively formed on a Si semiconductor substrate 11 of one conductivity type. A Si semiconductor 13 having a conductivity type opposite to that of the semiconductor substrate is epitaxially grown on the entire surface. After selectively forming the photosensitive resin pattern 14, CF
The epitaxial layer is etched by sputter etching in a four-gas atmosphere to form a recess 16. Next, the photosensitive resin film 14 is removed, and a thin silicon dioxide film 16 is formed in a high temperature oxygen atmosphere to a thickness of, for example, 600 to 3000 Å.
しかる後、有機溶媒に溶かしたシリコン有機化合物の溶
液中に外部より超音波振動を加えながら基板を浸した後
、水平な乾燥台にて溶媒を揮発し、基板全面にシリカフ
ィルムを被着1了する。その後、高温酸素雰囲気中で熱
処理を行ないシリカフィルムを二酸化硅素膜に変換する
。次に二酸化硅素膜を食刻し前記半導体基板の凸部表面
を露出し、通常方法で、ベース18、エミッタ19、お
よび金属配線2oを形成し、バイポーラ半導体装置を形
成する。After that, the substrate is immersed in a solution of a silicon organic compound dissolved in an organic solvent while applying ultrasonic vibration from the outside, and then the solvent is evaporated on a horizontal drying table, and a silica film is coated on the entire surface of the substrate. do. Thereafter, heat treatment is performed in a high-temperature oxygen atmosphere to convert the silica film into a silicon dioxide film. Next, the silicon dioxide film is etched to expose the surface of the convex portion of the semiconductor substrate, and a base 18, an emitter 19, and a metal wiring 2o are formed using a conventional method to form a bipolar semiconductor device.
本発明による方法では、半導体基板に形成した凹部をシ
リカフィルムによる二酸化硅素膜で埋めるので、従来の
熱酸化による二酸化硅素を用いる場合と異なり、素子形
成がなされる領域に応力歪にもとづく欠陥の発生がなく
高性能の半導体装置を製造できる。また、シリカフィル
ムは半導体基板をシリコン有機化合物の溶液中に外部か
ら超音波振動を加えながら含浸することにより基板に塗
布されるので、幅が狭く深い凹部が形成されていてもス
ピンオン法による場合の様にシリカフィルムで凹部を完
全に埋めつくせないというような事がおこらない。また
、蛎の広い凹部が形成されていても、1回の含浸塗布に
より凹部をシリカフィルムで埋めつくすことができると
いう特長がある。In the method according to the present invention, the recesses formed in the semiconductor substrate are filled with a silicon dioxide film made of silica film, so unlike the conventional case where silicon dioxide is used by thermal oxidation, defects occur due to stress strain in the region where elements are formed. It is possible to manufacture high-performance semiconductor devices without any problems. In addition, since silica film is applied to a semiconductor substrate by impregnating it in a silicon organic compound solution while applying ultrasonic vibration from the outside, even if narrow and deep recesses are formed, it is possible to This prevents the situation where the recesses cannot be completely filled with silica film. Another advantage is that even if a large concave portion is formed in the larvae, the concave portion can be completely filled with silica film by a single application of impregnation.
第1図は従来例を説明するための半導体装置の構造断面
図、第2図は本発明の詳細な説明するための半導体装置
の構造断面図である。
11・・・・・・St・半導体基板、12・・・・・・
反対導電形不純物層、13・・・・・・エピタキシャル
成長層、14・・・・・・感光性樹脂パターン、16・
・・・・・凹部、16二・・・・二酸化硅素膜、17・
・拳・・・シリカフィルム。FIG. 1 is a structural sectional view of a semiconductor device for explaining a conventional example, and FIG. 2 is a structural sectional view of a semiconductor device for explaining the present invention in detail. 11...St/semiconductor substrate, 12...
Opposite conductivity type impurity layer, 13...Epitaxial growth layer, 14...Photosensitive resin pattern, 16.
...Concavity, 162...Silicon dioxide film, 17.
・Fist: Silica film.
Claims (1)
機溶媒に溶かしたシリコン有機化合物の板金面にシリカ
フィルムを塗布する工程とを含むことを特徴とする半導
体装置の製造方法。1. A method for manufacturing a semiconductor device, comprising the steps of selectively etching a semiconductor substrate to form recesses, and applying a silica film to a sheet metal surface of a silicon-organic compound dissolved in an organic solvent.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12996181A JPS5831554A (en) | 1981-08-19 | 1981-08-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12996181A JPS5831554A (en) | 1981-08-19 | 1981-08-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5831554A true JPS5831554A (en) | 1983-02-24 |
Family
ID=15022708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12996181A Pending JPS5831554A (en) | 1981-08-19 | 1981-08-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5831554A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63213941A (en) * | 1987-03-02 | 1988-09-06 | Hoxan Corp | Manufacture of dielectric isolation substrate |
-
1981
- 1981-08-19 JP JP12996181A patent/JPS5831554A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63213941A (en) * | 1987-03-02 | 1988-09-06 | Hoxan Corp | Manufacture of dielectric isolation substrate |
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