JPS60257541A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPS60257541A JPS60257541A JP11588584A JP11588584A JPS60257541A JP S60257541 A JPS60257541 A JP S60257541A JP 11588584 A JP11588584 A JP 11588584A JP 11588584 A JP11588584 A JP 11588584A JP S60257541 A JPS60257541 A JP S60257541A
- Authority
- JP
- Japan
- Prior art keywords
- aperture
- film
- opening
- insulating film
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の製造方法、特に素子間分離幅を
小さくするために垂直な壁面の分離酸化膜で囲まれた活
性領域構造を得る方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for obtaining an active region structure surrounded by an isolation oxide film with vertical walls in order to reduce the isolation width between elements. It is something.
半導体装置の集積化が進むにつれて、素子間分離幅はま
すます狭くする要請がある。第1図A〜Cはこのような
要請に応じて開発された従来の方法の主要段階における
状態を示す断面図で、まず第1図Aに示すように、シリ
コン(8i)基板(1)の上に酸化シリコン(S 10
2 )膜(2)を形成し、その一部に開孔(3)を形成
する。つづいて、第1図Bに示すように、開孔(3)の
部分に選択的にエピタキシャル成長Si層(4)を形成
し、次に第1図Cに示すように研磨によってエピタキシ
ャル成長Si層(4)の凸部を除去して上面を平坦化し
て活性領域(4a)を得るものである。As the integration of semiconductor devices progresses, there is a demand for increasingly narrower isolation widths between elements. Figures 1A to 1C are cross-sectional views showing the main stages of a conventional method developed in response to such demands.First, as shown in Figure 1A, a silicon (8i) substrate (1) is Silicon oxide (S 10
2) Form a membrane (2) and form an opening (3) in a part of it. Subsequently, as shown in FIG. 1B, an epitaxially grown Si layer (4) is selectively formed in the opening (3), and then, as shown in FIG. 1C, an epitaxially grown Si layer (4) is formed by polishing. ) is removed to flatten the upper surface to obtain an active region (4a).
素子間分離幅を狭くするには分離酸化膜の壁面は垂直で
あることが望ましく、上記従来の方法でも、第1図Aの
段階では開孔(3)の形成に異方性ドライエツチング法
や、イオンビームエツチング法を用いて図示のように8
1基板(1)の表面に垂直な壁面を得ているが、第1図
Bの段階でSi層(4)のエピタキシャル成長時にS
io 2膜(2)がエツチングを受ける。すなわち、例
えば、1000℃以上の高温でモノシラン(S1a 4
) 、 )リクロルシラン(siHc13)。In order to narrow the isolation width between elements, it is desirable that the walls of the isolation oxide film be vertical, and even with the conventional method described above, an anisotropic dry etching method or anisotropic dry etching method is used to form the opening (3) at the stage shown in FIG. 1A. 8 using ion beam etching method as shown in the figure.
1 A wall surface perpendicular to the surface of the substrate (1) has been obtained, but at the stage shown in FIG.
The io2 film (2) undergoes etching. That is, for example, monosilane (S1a 4
) , ) Lichlorosilane (siHc13).
ジクロル7ラン(SiH2C70) +モノクロルシラ
ン(S 1H3CZ) 、四塩化ケイ素(S I C7
0)などのSiを含む気体または液体を分解するために
水素(H2)ガスを多量に流す。従って、S10□と8
1とが反応して一酸化シリコンSiOとなる。8i0は
気化して排出される。第1図Bの場合には、エピタキシ
ャル成長の初期には、S10□が微かにエツチングされ
ながらSiがデポジットされる。このS iO2のSi
O化f によるエツチングと81のエピタキシャル成長
とが同時に進行するので、SiO3膜(2)の底部から
上部に到るに従ってS iO2のエツチング量が増加し
、垂直であったS iO2膜(2)の壁面は次第に丸み
をおびるようになり、これが素子間分離幅低減の支障と
なる。また、上記SiOガスは完全に除去きれる訳では
なく、近傍のSi中に取シ込まれるので、高温熱処理に
よって酸素析出核が形成され成長して、Slとの格子定
数の違いによって欠陥密度が増加する。従って、開孔(
3)の周辺には1μm程度の幅の欠陥層を生じるので、
pn接合を形成した際、接合リークを生じ易いという問
題もあった。Dichlorosilane (SiH2C70) + monochlorosilane (S 1H3CZ), silicon tetrachloride (S I C7
A large amount of hydrogen (H2) gas is flowed to decompose Si-containing gases or liquids such as 0). Therefore, S10□ and 8
1 reacts with silicon monoxide to form silicon monoxide (SiO). 8i0 is vaporized and discharged. In the case of FIG. 1B, at the initial stage of epitaxial growth, Si is deposited while S10□ is slightly etched. This SiO2 Si
Since the etching by O oxide and the epitaxial growth of 81 proceed simultaneously, the amount of etching of SiO2 increases from the bottom to the top of the SiO3 film (2), and the vertical wall surface of the SiO2 film (2) increases. gradually becomes rounded, which becomes an obstacle to reducing the isolation width between elements. In addition, the above SiO gas cannot be completely removed, but is taken into the nearby Si, so oxygen precipitation nuclei are formed and grown by high-temperature heat treatment, and the defect density increases due to the difference in lattice constant from Sl. do. Therefore, the aperture (
Since a defect layer with a width of about 1 μm is generated around 3),
When a pn junction is formed, there is also the problem that junction leakage tends to occur.
この発明は以上のような点に鑑みてなされたもので、分
離層を構成する8 x O2膜に活性領域をエピタキシ
ャル成長させるべき開孔を形成した後に1その開孔内壁
面および上記S io 2膜の上面に酸素を含まない絶
縁膜を薄く形成した上で、Siをエピタキシャル成長さ
せて活性領域を形成することによって、エピタキシャル
成長時のS iO2膜のエツチングを防止し、刑直な壁
面の分離酸化膜で囲まれ周縁部にも欠陥の少ない活性領
域構造を得る方法を提供するものである。This invention has been made in view of the above points, and after forming an opening in which an active region is to be epitaxially grown in an 8 x O2 film constituting a separation layer, 1. By forming a thin insulating film that does not contain oxygen on the top surface and then epitaxially growing Si to form an active region, etching of the SiO2 film during epitaxial growth is prevented, and an isolation oxide film on the straight wall surface is formed. The present invention provides a method for obtaining an active region structure with fewer defects even in the surrounded peripheral portion.
第2図A −Dはこの発明の一実施例方法の主要段階で
の状態を示す断面図で、従来例と同一符号は同等部分を
示す。まず、第2図Aに示すように、従来と同様に、S
i基板(1)の上1csio。膜(2)を形成に、酸素
を含まない絶縁膜、例えば窒化シリコン(813N4)
膜(5)でSiO3膜(2)の上面および開孔(3)の
内側壁面を覆い、その内側に第2の開孔(6)を残し、
その底面にはEfi基板(1)の一部を露出させておく
。FIGS. 2A to 2D are cross-sectional views showing the main stages of a method according to an embodiment of the present invention, and the same reference numerals as in the conventional example indicate equivalent parts. First, as shown in FIG. 2A, S
1 csio on the i board (1). To form the film (2), an insulating film that does not contain oxygen, such as silicon nitride (813N4), is used.
Covering the top surface of the SiO3 film (2) and the inner wall surface of the opening (3) with the membrane (5), leaving a second opening (6) inside thereof,
A part of the Efi substrate (1) is exposed on the bottom surface.
その後に第2図Cに示すように、この第2の開孔(6)
の部分に選択的にエピタキシャル成長Si層(4)を形
成し、つづいて、第2図りに示すように、研磨((よっ
てエピタキシャル成長S1層(4)の凸部およびS 1
02膜(2)の上面の513N4膜(5)を除去して上
面を平坦化して活性領域(4a)を得る。This second aperture (6) is then opened as shown in Figure 2C.
An epitaxially grown Si layer (4) is selectively formed on the portion of
The 513N4 film (5) on the upper surface of the 02 film (2) is removed to flatten the upper surface to obtain an active region (4a).
この実施例の方法において、$2図Cの段階でエピタキ
シャル成長S1層(4)を形成する以前にその開孔(3
)の周辺のSiO□膜(2)の表面にSi3N4膜(5
)が形成されており、これには酸素が含まれておらず、
しかも5102膜(2)をエピタキシャル成長用の気体
または液体に触れるのを防ぐので従来のよりなSiO3
+81がH2によって反応してSi層化することがなく
、第2の開孔(6)の壁面の垂直性を維持できる。また
、この部分に形成されるエピタキシャル成長S1層(4
)はエツジ部で酸素のオートディフュージョンがないの
で、欠陥が少ない高品位のものとなる。従って、このよ
うにして得た活性領域では、pn接合を形成してもリー
ク電流が生じることなく、すぐれた接合の形成が可能で
ある。In the method of this embodiment, before forming the epitaxially grown S1 layer (4) at the stage of FIG.
) is coated on the surface of the SiO□ film (2) around the Si3N4 film (5
) is formed, which does not contain oxygen,
Moreover, it prevents the 5102 film (2) from coming into contact with the gas or liquid for epitaxial growth, making it easier to use than conventional SiO3.
+81 does not react with H2 to form a Si layer, and the verticality of the wall surface of the second opening (6) can be maintained. In addition, the epitaxial growth S1 layer (4
) has no oxygen auto-diffusion at the edges, resulting in high quality with few defects. Therefore, in the active region thus obtained, even when a pn junction is formed, leakage current does not occur, and an excellent junction can be formed.
このようにして、バイポーラ素子の場合特に問題になシ
やすいエミッタ・コレクタ・パイピング現象が防がれる
ばかシでなく、MO3素子においてもリークの少ない優
れた分離@域が得られる。In this way, the emitter-collector piping phenomenon, which is particularly problematic in bipolar devices, is not only prevented, but also an excellent isolation zone with low leakage is obtained even in MO3 devices.
更に、メモリ素子を構成する場合、特にメモリ容量を増
加させる目的で、従来「溝堀り分離方式」が用いられて
いたが、これはSiの一部を垂直に狭くエツチングして
酸化膜などの絶縁膜を埋め込むことによってキャパシタ
ーを構成するものであるが、Slのエツチングは原理的
に高速に行うことが困難な上に、そのエツチングの形状
も底部まで十分に垂直に仕上げることは困難であった。Furthermore, when configuring memory elements, the "groove isolation method" has traditionally been used, especially for the purpose of increasing memory capacity, but this method involves etching a portion of Si vertically and narrowly to form an oxide film or other layer. A capacitor is constructed by embedding an insulating film, but in principle it is difficult to perform high-speed etching of Sl, and it is also difficult to finish the etched shape sufficiently vertically to the bottom. .
そこて、この場合にもこの発明を適用すれば、従来得ら
れなかった垂直な壁面を有する高品質の絶縁膜が得られ
ることから、優れたキャパシターを構成でき、小さなチ
ップサイズで大容量メモリが実現できる。Therefore, if the present invention is applied to this case, a high-quality insulating film with vertical walls, which could not be obtained conventionally, can be obtained, making it possible to construct an excellent capacitor and create a large-capacity memory with a small chip size. realizable.
以上説明したようにこの発明の方法ではS iO2膜に
形成した開孔の内側壁面および5102膜上面を、酸素
を含まない絶縁膜で覆った後に、開孔内にSiをエピタ
キシャル成長させるようにしたので、エピタキシャル成
長時に開孔壁面にエツチングが生じることなく、垂直性
が保持でき、バイポーラ、MO3両構造とも集積度の向
上が期待できf) る。As explained above, in the method of the present invention, the inner wall surface of the opening formed in the SiO2 film and the upper surface of the 5102 film are covered with an oxygen-free insulating film, and then Si is epitaxially grown inside the opening. During epitaxial growth, verticality can be maintained without etching on the wall surfaces of the openings, and an improvement in the degree of integration can be expected for both bipolar and MO3 structures.
1′ なお、全絶縁膜を酸素を含まない絶縁膜で形成し
てもよい訳であるが、これでは開孔エツチング速度、開
孔仕上り形状の上で問題があり、上述のSiO□膜を用
いることによってこの問題も解決される。1' It is also possible to form the entire insulating film with an insulating film that does not contain oxygen, but this poses problems in terms of opening etching speed and opening finish shape. This also solves this problem.
第1図A−Cは従来の方法の主要段階における状態を示
す断面図、第2図A −Dはこの発明の一実施例方法の
主要段階忙おける状態を示す断面図である。
図において、(1)はシリコン(半導体)基板、(2)
は酸化シリコン膜、(3)は開孔、(4L (4a)は
エピタキシャル成長シリコン層、(5)、 (5a)は
窒化シリコン膜である。
なお、図中同一符号は同一または相当部分を示す。
代理人大岩増雄
第1図
第2図1A to 1C are sectional views showing the main steps of a conventional method, and FIGS. 2A to 2D are sectional views showing the main steps of a method according to an embodiment of the present invention. In the figure, (1) is a silicon (semiconductor) substrate, (2)
(3) is a silicon oxide film, (3) is an opening, (4L (4a) is an epitaxially grown silicon layer, and (5) and (5a) are silicon nitride films. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 Figure 2
Claims (3)
し、この酸化シリコン膜の所望部分に開孔を形成しその
底面に上記半導体基体を露出させ、上記開孔の内側壁面
上と上記酸化シリコン膜の上とを酸素を含まない絶縁膜
で覆った後に、この絶縁膜の上からシリコンを上記開孔
の深さ以上の厚さにエピタキシャル成長させ、更にその
上面を研磨して平坦化して、上記酸化シリコン膜および
上記開孔の内側壁面上の上記絶縁膜を上記開孔内にエピ
タキシャル成長させたシリコン層の分離絶縁膜として構
成することを特徴とする半導体装置の製造方法。(1) A silicon oxide film is formed on the entire surface of a semiconductor substrate, an opening is formed in a desired portion of the silicon oxide film, the semiconductor substrate is exposed on the bottom surface of the opening, and the silicon oxide film is formed on the inner wall surface of the opening and After covering the silicon film with an oxygen-free insulating film, silicon is epitaxially grown on the insulating film to a thickness equal to or greater than the depth of the opening, and the upper surface is further polished to planarize it. A method for manufacturing a semiconductor device, characterized in that the silicon oxide film and the insulating film on the inner wall surface of the opening are formed as an isolation insulating film of a silicon layer epitaxially grown in the opening.
法を用いることを特徴とする特許請求の範囲第1項記載
の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein an anisotropic etching method is used to form the openings in the silicon oxide film.
ことを特徴とする特許請求の範囲第1項または第2項記
載の半導体装置の製造方法。(3) A method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that a silicon nitride film is used as the oxygen-free insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11588584A JPS60257541A (en) | 1984-06-04 | 1984-06-04 | Production of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11588584A JPS60257541A (en) | 1984-06-04 | 1984-06-04 | Production of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60257541A true JPS60257541A (en) | 1985-12-19 |
Family
ID=14673590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11588584A Pending JPS60257541A (en) | 1984-06-04 | 1984-06-04 | Production of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60257541A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143253A (en) * | 1987-11-27 | 1989-06-05 | Nec Corp | Semiconductor device and manufacture thereof |
JPH01187977A (en) * | 1988-01-22 | 1989-07-27 | Nec Corp | Insulated-gate field-effect transistor and manufacture thereof |
US5188987A (en) * | 1989-04-10 | 1993-02-23 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device using a polishing step prior to a selective vapor growth step |
US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
JPH09283615A (en) * | 1996-04-12 | 1997-10-31 | Lg Semicon Co Ltd | Structure of isolation film of semiconductor element and formation of the film |
KR100400287B1 (en) * | 1996-12-31 | 2003-12-24 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
US6989316B2 (en) | 1999-06-30 | 2006-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing |
JP2008506271A (en) * | 2004-07-15 | 2008-02-28 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Formation of active region using semiconductor growth process without STI integration |
US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
-
1984
- 1984-06-04 JP JP11588584A patent/JPS60257541A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01143253A (en) * | 1987-11-27 | 1989-06-05 | Nec Corp | Semiconductor device and manufacture thereof |
JPH01187977A (en) * | 1988-01-22 | 1989-07-27 | Nec Corp | Insulated-gate field-effect transistor and manufacture thereof |
US5188987A (en) * | 1989-04-10 | 1993-02-23 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device using a polishing step prior to a selective vapor growth step |
US5202284A (en) * | 1989-12-01 | 1993-04-13 | Hewlett-Packard Company | Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2 |
JPH09283615A (en) * | 1996-04-12 | 1997-10-31 | Lg Semicon Co Ltd | Structure of isolation film of semiconductor element and formation of the film |
KR100400287B1 (en) * | 1996-12-31 | 2003-12-24 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
US6989316B2 (en) | 1999-06-30 | 2006-01-24 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing |
US7772671B2 (en) | 1999-06-30 | 2010-08-10 | Kabushiki Kaisha Toshiba | Semiconductor device having an element isolating insulating film |
JP2008506271A (en) * | 2004-07-15 | 2008-02-28 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Formation of active region using semiconductor growth process without STI integration |
US7985642B2 (en) | 2004-07-15 | 2011-07-26 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
US8173502B2 (en) | 2004-07-15 | 2012-05-08 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
US8530355B2 (en) | 2005-12-23 | 2013-09-10 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
US9607986B2 (en) | 2005-12-23 | 2017-03-28 | Infineon Technologies Ag | Mixed orientation semiconductor device and method |
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