JPS5830789B2 - Information signal receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to means for generating a reception clock in an information receiving device such as a device that receives teletext signals that are multiplexed and transmitted during the vertical retrace period of a television signal. The object of the present invention is to provide a device that can create a reception clock synchronized with the .

Recently, systems have been developed that multiplex and transmit various information signals during the vertical retrace period of television signals. and the 283rd H), pattern signals such as character images are multiplexed and transmitted line by line, received by the receiver, stored in memory for one screen in sequence, and read out in synchronization with the scanning of the cathode ray tube. 1 to 8 on the screen.
Devices that display character images on the order of lines have been developed.

Hereinafter, the present invention will be described in detail with reference to an embodiment implemented in a receiving device used in a system in which such character image information is multiplexed and transmitted.

FIG. 1 shows a multiplexed television signal used in such a case.
During the horizontal scanning period of 3H (the explanation is omitted),
Text information signals in the form of binary signals are multiplexed and transmitted.

This information signal includes a reference phase signal STX of 8 to 16 bits (4 to 8 cycles) indicating the reference phase and reference frequency of each signal, and a reference phase signal STX indicating that the multiplexed information is a character image and indicating that the multiplexed information is a character image. 8-bit framing code signal FC1 of a specific code (for example, "11100101") indicating the beginning of the signal 4-bit program code lower signal PC indicating the program of the character information concerned The data signal multiplexed in the relevant horizontal scanning period is the character information A data signal consisting of an 8-bit line number code signal LM indicating whether the first line of the image is selected, and a binary signal for one horizontal line (for example, 256 bits) extracted from the character image to be transmitted. It is composed of.

H8 is a horizontal synchronization signal, and CB is a color burst signal.

In order to multiplex binary signals of approximately 300 bits in this way, the clock frequency (data rate) of the data signal (2) is normally selected to be 8fsc15, and the clock frequency (data rate) of the other signals is set to 2. It is set to 1/2.

Such information signals are transmitted using a television receiver,
An additional circuit for multiplexed information processing is added thereto, and then the signal is received.

FIG. 2 is a block diagram showing a schematic configuration of an example of the receiving device, where 1 is a receiving circuit for receiving television signals, and includes a tuner 2, a VIF circuit 3, and a video detection circuit 4. .

Further, 5 is a display circuit for displaying television images, and includes a video processing circuit 6 and a cathode ray tube 7.

On the other hand, 8 extracts the information signal of the character image sent after being multiplexed with the television signal using the method explained in FIG. This is an information signal processing circuit for reproduction.

In this circuit 8, 9 is a waveform shaping circuit that shapes the waveform of the television signal including the information signal received by the receiving circuit 1 into a binary signal, 10 is a synchronous separation circuit,
11 is a horizontal/vertical oscillation circuit synchronized with horizontal/vertical synchronizing signals.

12 extracts the information signal superimposed on the 20th H (and the 283rd H; hereinafter both will be referred to as the 20th H and the 283rd H will be omitted) based on the horizontal and vertical signals. Therefore, this is a gate pulse generation circuit that generates a sampling gate pulse during this 20th H period.

In the gate circuit 13 for signal extraction, each signal STX of the 20th H from the output of the waveform shaping circuit 9 is generated by the gate pulse from the gate pulse generating circuit 12.

FC, PC, LN, V, etc. are extracted and supplied to the input gate circuit 14, etc.

On the other hand, the program code signal extraction circuit 15 extracts the program code signal PC using the clock signal from the reception clock generation circuit 16 and holds it for one field period.

Then, the comparison circuit 17 compares the program designation signal from the program designation circuit 18 and the sampled program code signal PC, and when the two match, a match output is generated, and the input gate circuit 14 is opened to output one line. The image signal {circle around (2)} is written and stored in a buffer memory 19 having a storage capacity for one line.

In addition, the line number signal extraction circuit 20 uses the clock signal from the reception clock generation circuit 16 to generate the line number signal L.
Remove N.

Then, the line number comparison circuit 21 compares the count output from the line counter 22 indicating the line being scanned with the extracted line number signal LN, and when the two match, the transfer gate 23 is opened and the signal is transferred to the buffer memory 19. The stored data signal for one line is stored in the main memory 24.
is written and stored in the storage position of the corresponding line.

This main memory 24 is a storage circuit that normally has a storage capacity for one page of still images, and is driven by a clock from a main clock generation circuit 25.

By repeating such receiving and storing operations, the received data signals (2) can be stored one after another in the main memory 24.

Then, for example, from the 42nd H to the 2nd H in the cathode ray tube.
245 every H during the scanning period of 200 lines up to the 41st H.
The read clock is input to the main memory 2 at a rate of bit by bit.
4 and reads out the stored data signal, and generates an image signal via a buffer amplifier 26 in place of a video signal during normal television reception.

By applying this to the cathode ray tube 7 via the coupling circuit 27, a character image can be projected on the cathode ray tube 7.

In this way, this device can receive and display character image information, but in order to accurately receive such information signals, it is necessary to accurately create a reception clock for signal reception. It becomes necessary.

Therefore, it is an object of the present invention to provide a means for accurately creating such a reception clock, in which a counter that creates a reception clock by dividing a basic clock is divided into multiple bits. The clock run-in signal is reset and synchronized each time at the leading edge, trailing edge, or both of the clock run-in signals.

Hereinafter, one embodiment of the receiving clock generating circuit 16 will be described in detail in FIG. 3 and with reference to the waveform diagram in FIG. 4.

In FIG. 3, 28 is an oscillation circuit that generates a color subcarrier synchronized with the color burst signal in the received television signal, and the one in the video processing circuit 6 can be used as this circuit.

This color subcarrier is multiplied multiple times by a multiplier circuit 29 and mf
sc (m: positive integer), here multiplied by 8 and shown in Figure 4B.
Create a basic clock of 8fsc like this.

Furthermore, this basic clock B is added to the frequency division counter 30, where the frequency is divided into 1 for a plurality of valves to obtain -fSC (n: a positive integer), here -fsc as shown in Fig. 4C. A reception clock for data signal sampling and a reception clock for -0 fsc control code signal sampling as shown in the fourth diagram are created.

30A to 30D are flip-flops forming the counter 30, and 30E is a gate for determining the frequency division ratio.

mfs taken out from the Q terminal of flipflop 0 tube 30B
The pulse c is gated by the gate 31 using the gate pulse generated only at the 20th H obtained from the line counter 22, is extracted only at the 20th H, and is outputted from the terminal 32 as the reception clock B for data signal sampling. .

In addition, the flip-flop 30D has a 20H terminal connected to J-.
By adding the second gate pulse, a pulse of -f sc is extracted from the Q terminal only at the 20th H, and is outputted from the terminal 033 as the reception clock C for sampling the control code signal.

Next, the part for resetting this counter 30 and synchronizing the reception clock will be explained.

First, two monostable multi-by breaks 34 and 35 are triggered by the 20th pulse as shown in Figure 4, and from the monostable multi-by breaks 34, a signal is generated slightly before the clock line signal CR as shown in Figure 4 E. From the monostable multi-bi break 35, a gate pulse that becomes high level is generated from the clock run-in signal CR, and a gate pulse that becomes low level a little after the clock run-in signal CR is generated as shown in FIG. 4F.

On the other hand, the reception clock taken out from the flip-flop 30D is taken out only in the period before the Fleming code by the gate 36, and the shift register 3 for Fleming code detection
7, the received information signal is sampled using this receiving clock and written to the shift register 37, and when a specific code, the Fleming code, is detected, a detection output is generated from the gate 38 as shown in FIG. 3
Set 9.

Since this flip-flop 39 is reset by the horizontal synchronizing signal, it generates an output only during the period until the framing code is detected as shown in FIG. 4H.

These outputs E, F, and H are then combined by a gate 40 to create a gate pulse as shown in FIG.

On the other hand, the received information signal taken out from the waveform shaping circuit 9 is differentiated by a capacitor 41 and a resistor 42, and a differential output is created by the leading edge and trailing edge of the pulse of each bit as shown in FIG. 4J. .

This differential output J is applied to the gate 4 by the aforementioned gate pulse ■.
3 to create a reset pulse for each leading edge of each bit of the clock run-in signal CR as shown in FIG. In addition to R, reset each time to match the phase.

In this way, in this device, the counter 30 is reset at the leading edge of each of the multiple-bit clock line signals CR, making it possible to synchronize the phases very accurately.

In particular, even when the electric field strength of the received television signal is weak and the signal waveform is easily distorted, by repeating the reset multiple times in this way, it is possible to ensure the accuracy of phase synchronization. It is something.

Note that the gate 45 inverts the Q output of the flip-flop 39 when the Fleming code is detected;
This is integrated by a resistor 46 and a capacitor 47, and the inverted value is gated, and the output is used to reset the counter 30 again to make the subsequent phase even more accurate.

In this way, the phase of the receive clock created by resetting the counter at each leading edge of the multi-bit clock run-in signal is accurately controlled, and this can be used to accurately control the information signal. It is something that can be received.

In the above embodiment, the leading edge of a plurality of bits of a reference phase signal such as a clock run-in signal is used to reset the frequency dividing counter and perform phase control, but the trailing edge is used to reset the counter. Alternatively, both the leading edge and the trailing edge may be used for resetting.

Thus, according to the present invention, m/n of color subcarrier frequencies are multiplexed in the vertical retrace interval of a television signal.
In a device that receives a binary information signal transmitted at twice the clock rate, the receiving side multiplies the color subcarrier by m to generate a basic clock, and uses a counter to generate a basic clock.
A reception clock for sampling the information signal is created by dividing the frequency by n, and a reference phase signal of multiple bits transmitted prior to the specific code signal and data signal in the information signal is used. After shaping the reference phase signal, a plurality of reset pulses are created using the leading edge and/or trailing edge of each of the multiple bits, and these reset pulses are used to control the frequency division counter of the multiple bits. The device is characterized in that the phase of the received clock is controlled to be synchronized with the phase of the information signal by repeatedly resetting the clock over a period of time. Since it can be controlled repeatedly by reset pulses for multiple bits in the phase signal, if the electric field strength of the received television signal is poor, the received signal will be unstable or part of the signal will be deleted. Even in such cases, there are few negative effects caused by multiple resets, the phase can always be controlled accurately, and multiplexed information can be received stably and accurately, which is an excellent effect. .

In particular, the present invention is particularly effective for use in a receiving apparatus for television multiplexed information signals whose reception conditions tend to deteriorate.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram of an example of an information signal received by an information receiving device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of the device, and FIG. 3 is a diagram showing the main parts of the device. The circuit diagram and FIG. 4 are waveform diagrams of various parts of the device. 28...Color subcarrier oscillation circuit, 29...
・Multiplier circuit, 30...Counter, 31.36,
38,40°43.44.45...Gate, 3
2.33... Output terminal, 34, 35...
・Monostable multi-by-break, 37...shift register, 39...flip-flop, 41...
... Capacitor, 42 ... Resistor.

Claims (1)

[Claims] 1. A binary data signal that is multiplexed and transmitted during the vertical retrace period of a television signal at a clock rate that is rn/n times the color subcarrier frequency (where m and n are positive integers); An apparatus for receiving an information signal including a code signal of a predetermined code indicating the start of the data signal, and a multi-bit reference phase signal preceding the data signal and the code signal and indicating their reference phase, the apparatus comprising: a basic clock generating means for generating a basic clock having a frequency m times the subcarrier frequency;
a counter that divides the frequency by n to create a reception clock for sampling the code signal and data signal; and a counter that shapes the received reference phase signal and uses the leading edge and/or trailing edge of each of the plurality of bits. a reset means that generates a plurality of reset pulses and synchronizes the phase of the reception clock by resetting the frequency division counter each time the plurality of reset pulses are generated, and after receiving the code signal; An information signal receiving apparatus comprising: a stopping means for stopping resetting of the counter; and a sampling means for sampling the code signal and data signal using a reception clock output from the counter.