JPH05183543A - Data transmitter-receiver - Google Patents

Abstract

PURPOSE:To send receive lots of data at a high speed by providing a synchronization clock generating means generating a synchronization clock on when data are sent to a sender side so as to eliminate the need for communication procedure thereby discriminating head data in a data string. CONSTITUTION:A synchronization clock generating means 4 provided to a transmitter 1 generates a synchronization clock only when data are sent. A receiver 2 fetches data synchronously with the synchronization clock and data are written in a storage means 9 based on an address generated by an address generating means 10 depending on the synchronization clock. When the synchronization clock is not received, an address reset means 11 resets the address generating means 10 to inhibit data write to the storage means 9. That is, a slight interval time between picture data is effectively utilized and only when the picture data are sent from the transmitter 1, the synchronization clock is sent simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving device for transmitting / receiving a large amount of data at high speed.

[0002]

2. Description of the Related Art For example, in normal synchronous communication, data is transmitted and received while being synchronized at the rising edge (or falling edge) of a synchronizing clock (eg, horizontal synchronizing signal) as shown in FIG.

In this case, the time of the predetermined number of pulses of the synchronous clock (corresponding to 12 pulses in the figure) corresponds to the image data for one screen (TEXT), and the image data has a predetermined interval for each screen. After that, the transmission side and the synchronous clock are sequentially transmitted to the reception side.

And, when such an operation is performed,
As a series of image data is transmitted from the transmitting side, in order to display the image data for one screen on the display screen without disturbing the image on the receiving side, in order to display the image data for one screen on the display screen, It was necessary to determine the data.

[0005]

[Problems to be Solved by the Invention] By the way, RS-23
In TEXT serial communication such as 2C, data is synchronized by inserting a character indicating the beginning of TEXT or a character indicating the end of TEXT into TEXT having a certain length as data. However, in this type of communication, when a large amount of data or high-speed communication is performed, not only is it time-consuming to perform communication procedures and is inconvenient to handle, but also a control IC such as a CPU is indispensable.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to eliminate the need for a communication procedure and to judge a head data in a data string to speed up a large amount of data. It is to provide a data transmitting / receiving device capable of transmitting / receiving.

[0007]

In order to achieve the above object, the data transmitting / receiving apparatus according to the present invention is provided with a synchronous clock generating means 4 for generating a synchronous clock only at the time of transmitting data, and the synchronous clock generating means 4 is provided at the transmitting apparatus 1 side. Address generation means 10 for generating an address for writing the data in the storage means 9 based on a clock, and writing the data in the storage means by resetting the address generation means when the synchronous clock is not received. The address resetting means 11 for prohibiting is provided on the receiving device 2 side.

[0008]

The synchronous clock generating means 4 provided on the transmitter 1 side generates the synchronous clock only when transmitting data. On the receiving device 2 side, the data is taken in in synchronization with the synchronous clock, and the data is written in the storage means 9 by the address generated by the address generating means 10 based on the synchronous clock. The address resetting means 11 resets the address generating means 10 to prohibit writing of data to the storage means 9 when the synchronous clock is not received.

[0009]

1 is a circuit diagram showing an embodiment of a data transmitting / receiving apparatus according to the present invention. The data transmission / reception device according to this embodiment is roughly configured to include a transmission device 1 and a reception device 2.

The transmitter 1 comprises a data transmitter 3 and a synchronous clock generator 4. As shown in FIG. 2A, the data transmission unit 3 sets image data corresponding to one screen at predetermined intervals (for example, 256 ×).
256 pixels) are transmitted to the receiving device 2 side via the buffer 5.

The synchronous clock generation means 4 comprises a synchronous clock generation permission circuit 6 and an AND circuit 7.
The synchronous clock generation permitting circuit 6 outputs a "0" signal to one input terminal 7a of the AND circuit 7 for a time t corresponding to the interval of the data transmitting means 3, and the AND circuit 7
The synchronous clock is input to the other input terminal 7b. Then, the synchronizing clock is output to the receiving device 2 side only while the image data is transmitted from the AND circuit 7 by the data transmitting means 3 (FIG. 2).
(See (b)).

The receiving device 2 comprises a shift register 8, a memory 9 as a storage means, an address generating means 10, and an address resetting means 11. In the shift register 8, the buffer 5 and 1 from the data transmitting means 3 are connected to the D terminal.
The image data received via 2 is input, and the buffer 13 from the synchronous clock generating means 4 is input to the clock terminal.
The synchronous clock received via 14 is input.
The shift register 8 captures the received image data in synchronization with the rising (or falling) timing of the sync signal, and when the predetermined number of bits is reached, the captured image data is written in the memory 9. There is.

The address generator 10 has a clock terminal to which the sync clock received from the sync clock generator 4 via the buffers 13 and 14 is input, and the sync clock is a predetermined bit (corresponding to image data for one screen). ) Each time it counts, it increments by 1 to generate the address of the memory 9 corresponding to each pixel of the image data.

The address reset means 11 comprises a reset circuit 15 and a watch dock timer circuit (hereinafter abbreviated as WDT circuit) 16. The reset circuit 15 receives the synchronous clock received from the synchronous clock generating means 4 via the buffers 13 and 14 at the clock terminal similarly to the address generating means 10, and while the synchronous clock is being received, FIG. W as shown in (e)
The clear signal C1 is output to the DT circuit 16.
That is, the operation of the WDT circuit 16 is prohibited while receiving the image data and the synchronous clock.

The WDT circuit 16 counts the WDT clock input to the clock terminal from the outside as shown in FIG. 2 (d), and during the timer time T set and set shorter than the interval time t in advance. The state where the synchronous clock is not received, that is, the state of the interval continues and W
When the DT clock is counted up, FIG.
As shown in, the clear signal C2 is output to the address generating means 10 to set the address to "0".

Therefore, in the data transmitting / receiving apparatus configured as described above, the synchronous clock is output from the synchronous clock generating means 4 only when the image data is transmitted from the transmitting apparatus 1, and the image data is not transmitted. Are controlled so that a synchronous clock is not generated (Fig. 2 (a),
(See (b)). Then, the image data is stored in the buffers 5 and 12.
Is input to the shift register 8 via. Similarly, the synchronous clock is also input to the clock terminal of the shift register 8 via the buffers 13 and 14, and the synchronous clock is also input to the address generating means 10 and the clock terminal of the reset circuit 15 at the same time. The shift register 8 takes in the image data in synchronization with the rising (or falling) timing of the synchronous clock while receiving the synchronous clock. When the shift register 8 counts a predetermined number of bits corresponding to one screen, the image data is written in the memory 9 by the address of the address generating means 10 generated based on the synchronous clock (see FIG. 2C). Although not shown, the image data written in the memory 9 is output to the outside for each screen by, for example, the FIFO method. In the above operation, the count value of the WDT circuit 16 is cleared by the clear signal C1 of the reset circuit 15 while the synchronous clock is being received.
The address is never set to "0" by the above (see FIG. 2 (e)).

On the other hand, when the interval time t continues and the synchronous clock is not received (FIG. 2 (a),
In (b), the clear signal C1 is not input from the reset circuit 15 to the WDT circuit 16 (see FIG. 2).
(See (e)), the WDT circuit 16 counts the WDT clock, and when it counts up over a preset timer time T, the clear signal C is sent to the address generating means 10.
2 is input and the address becomes "0" (see FIG. 2F), and writing of image data to the memory 9 is prohibited.

Therefore, in the above-described embodiment, the time t, which is a small interval between image data, is effectively used, and the synchronous clock is transmitted at the same time only when the image data is transmitted from the transmitter 1, and the receiver 2 receives it. Then, the address generation means 1 for recognizing that the synchronous clock is not received and generating an address for writing the image data in the memory 9.
Since the configuration is reset to 0, the conventional communication procedure is not required, high-speed data transmission can be performed by a few signals of the image data and the synchronization clock, and the leading data in the image data string is determined and a large amount of data is determined. The data of can be transmitted and received at high speed.

[0019]

As described above, according to the data transmission / reception apparatus of the present invention, a communication procedure is not required, and a large amount of data can be transmitted / received at high speed by discriminating the head data in the data string. it can.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a data transmission / reception device according to the present invention.

FIG. 2 is a timing chart of the data transmitting / receiving device.

FIG. 3 is a timing chart diagram of conventional synchronous communication.

[Explanation of symbols]

 1 transmitter 2 receiver 3 data transmitter 4 synchronous clock generator 9 memory (memory) 10 address generator 11 address reset means T timer time t interval time

[Procedure amendment]

[Submission date] October 26, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title of data transmission / reception device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting / receiving device for transmitting / receiving a large amount of data at high speed.

[0002]

BACKGROUND OF THE INVENTION For example typical synchronous communication, Example
And transmitting or receiving data while synchronizing with the rising (or falling) of the example, if the synchronous clock (e.g. horizontal synchronizing signal).

In this case, 256 pixels vertically, 256 pixels horizontally, and 1 pixel
If a 12-bit image is transmitted or received, the time of the predetermined number of pulses of the synchronization clock (equivalent to 256 × 256 × 12 pulses) corresponds to the image data for one screen (TEXT), and the image data is for one screen. At a predetermined interval every minute, the transmitting side sequentially transmits the synchronous clock to the receiving side.

And, when such an operation is performed,
As a series of image data is transmitted from the transmitting side, in order to display the image data for one screen on the display screen without disturbing the image on the receiving side, in order to display the image data for one screen on the display screen, It was necessary to determine the data.

[0005]

[Problems to be Solved by the Invention] By the way, RS-23
In TEXT serial communication such as 2C, data is synchronized by inserting a character indicating the beginning of TEXT or a character indicating the end of TEXT into TEXT having a certain length as data. However, in this type of communication, when a large amount of data or high-speed communication is performed, not only is it time-consuming to perform communication procedures and is inconvenient to handle, but also a control IC such as a CPU is indispensable.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to eliminate the need for a communication procedure and to judge a head data in a data string to speed up a large amount of data. It is to provide a data transmitting / receiving device capable of transmitting / receiving.

[0007]

In order to achieve the above object, the data transmitting / receiving apparatus according to the present invention is provided with a synchronous clock generating means 4 for generating a synchronous clock only at the time of transmitting data, and the synchronous clock generating means 4 is provided at the transmitting apparatus 1 side. Address generation means 10 for generating an address for writing the data in the storage means 9 based on a clock, and writing the data in the storage means by resetting the address generation means when the synchronous clock is not received. The address resetting means 11 for prohibiting is provided on the receiving device 2 side.

[0008]

The synchronous clock generating means 4 provided on the transmitter 1 side generates the synchronous clock only when transmitting data. On the receiving device 2 side, the data is taken in in synchronization with the synchronous clock, and the data is written in the storage means 9 by the address generated by the address generating means 10 based on the synchronous clock. The address resetting means 11 resets the address generating means 10 to prohibit writing of data to the storage means 9 when the synchronous clock is not received.

[0009]

1 is a circuit diagram showing an embodiment of a data transmitting / receiving apparatus according to the present invention. The data transmission / reception device according to this embodiment is roughly configured to include a transmission device 1 and a reception device 2.

The transmitter 1 comprises a data transmitter 3 and a synchronous clock generator 4. As shown in FIG. 2A, the data transmission unit 3 sets image data corresponding to one screen at predetermined intervals (for example, 256 ×).
256 pixels) are transmitted to the receiving device 2 side via the buffer 5.

The synchronous clock generation means 4 comprises a synchronous clock generation permission circuit 6 and an AND circuit 7.
The synchronous clock generation permitting circuit 6 outputs a "0" signal to one input terminal 7a of the AND circuit 7 for a time t corresponding to the interval of the data transmitting means 3, and the AND circuit 7
The synchronous clock is input to the other input terminal 7b. Then, the synchronizing clock is output to the receiving device 2 side only while the image data is transmitted from the AND circuit 7 by the data transmitting means 3 (FIG. 2).
(See (b)).

The receiving device 2 comprises a shift register 8, a memory 9 as a storage means, an address generating means 10, and an address resetting means 11. In the shift register 8, the buffer 5 and 1 from the data transmitting means 3 are connected to the D terminal.
The image data received via 2 is input, and the buffer 13 from the synchronous clock generating means 4 is input to the clock terminal.
The synchronous clock received via 14 is input.
The shift register 8 captures the received image data in synchronization with the rising (or falling) timing of the sync signal, and when the predetermined number of bits is reached, the captured image data is written in the memory 9. There is.

[0013] address to the generating means 10 and synchronous clock received via the buffer 13, 14 from the synchronizing signal generating means 4 is inputted to a clock terminal, a synchronous clock to the image data of a predetermined bit (1 stroke fiber of (Equivalent) Each time it counts, it increments by one to generate the address of the memory 9 corresponding to each pixel of the image data.

The address reset means 11 comprises a reset circuit 15 and a watch dock timer circuit (hereinafter abbreviated as WDT circuit) 16. The reset circuit 15 receives the synchronous clock received from the synchronous clock generating means 4 via the buffers 13 and 14 at the clock terminal similarly to the address generating means 10, and while the synchronous clock is being received, FIG. W as shown in (e)
The clear signal C1 is output to the DT circuit 16.
That is, the operation of the WDT circuit 16 is prohibited while receiving the image data and the synchronous clock.

The WDT circuit 16 counts the WDT clock input to the clock terminal from the outside as shown in FIG. 2 (d), and during the timer time T set and set shorter than the interval time t in advance. The state where the synchronous clock is not received, that is, the state of the interval continues and W
When the DT clock is counted up, FIG.
As shown in, the clear signal C2 is output to the address generating means 10 to set the address to "0".

Therefore, in the data transmitting / receiving apparatus configured as described above, the synchronous clock is output from the synchronous clock generating means 4 only when the image data is transmitted from the transmitting apparatus 1, and the image data is not transmitted. Are controlled so that a synchronous clock is not generated (Fig. 2 (a),
(See (b)). Then, the image data is stored in the buffers 5 and 12.
Is input to the shift register 8 via. Similarly, the synchronous clock is also input to the clock terminal of the shift register 8 via the buffers 13 and 14, and the synchronous clock is also input to the address generating means 10 and the clock terminal of the reset circuit 15 at the same time. The shift register 8 takes in the image data in synchronization with the rising (or falling) timing of the synchronous clock while receiving the synchronous clock. The address generating means 10 counts a predetermined number of bits (e.g. 12 bits) corresponding to one screen element, the contents of the shift register 8 address generator 10
Is written as image data in the memory 9 by the addressing and write pulses that occur simultaneously (FIG. 2
(See (c)). This operation is repeated 256 × 256 times, for example.
Although not shown, the image data returned and written in the memory 9 is, for example, a FIFO method or a shared memo for each screen.
It is designed to be output to the outside by the re-method .
In the above-described operation, while the synchronous clock is being received, the count value of the WDT circuit 16 is cleared by the clear signal C1 of the reset circuit 15, so that the address generator 10 sets the address to "0". This is not the case (see FIG. 2 (e)).

On the other hand, when the interval time t continues and the synchronous clock is not received (FIG. 2 (a),
In (b), the clear signal C1 is not input from the reset circuit 15 to the WDT circuit 16 (see FIG. 2).
(See (e)), the WDT circuit 16 counts the WDT clock, and when it counts up over a preset timer time T, the clear signal C is sent to the address generating means 10.
2 is input and the address becomes "0" (see FIG. 2F), and writing of image data to the memory 9 is prohibited.

Therefore, in the above-described embodiment, the time t, which is a small interval between image data, is effectively used, and the synchronous clock is transmitted at the same time only when the image data is transmitted from the transmitter 1, and the receiver 2 receives it. Then, the address generation means 1 for recognizing that the synchronous clock is not received and generating an address for writing the image data in the memory 9.
Since the configuration is reset to 0, the conventional communication procedure is not required, high-speed data transmission can be performed by a few signals of the image data and the synchronization clock, and the leading data in the image data string is determined and a large amount of data is determined. The data of can be transmitted and received at high speed.

[0019]

As described above, according to the data transmission / reception apparatus of the present invention, a communication procedure is not required, and a large amount of data can be transmitted / received at high speed by discriminating the head data in the data string. it can.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a data transmission / reception device according to the present invention.

FIG. 2 is a timing chart of the data transmitting / receiving device .

[Description of Codes] 1 transmitter 2 receiver 3 data transmitter 4 synchronous clock generator 9 memory (memory) 10 address generator 11 address reset means T timer time t interval time

Claims (1)

[Claims] 1. A transmitter (1) comprising synchronous clock generating means (4) for generating a synchronous clock only when transmitting data.
An address generating means (10) provided on the side for generating an address for writing the data in the storage means (9) based on the synchronous clock; and resetting the address generating means when the synchronous clock is not received. An address resetting means (11) for prohibiting the writing of the data to the storage means is provided on the receiving device (2) side.