JPS5830144A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5830144A JPS5830144A JP12893381A JP12893381A JPS5830144A JP S5830144 A JPS5830144 A JP S5830144A JP 12893381 A JP12893381 A JP 12893381A JP 12893381 A JP12893381 A JP 12893381A JP S5830144 A JPS5830144 A JP S5830144A
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- Japan
- Prior art keywords
- region
- layer
- crystal defects
- ions
- formation
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は結晶欠陥に起因する歩留低下を防ぐことのでき
る半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device that can prevent a decrease in yield due to crystal defects.
従来から半導体素子の製造工程において、電気的に活性
な領駿存在する結晶欠陥は素子特性の劣化をもたらし、
歩留り低下の原因であった。すなわち、活性領域の微小
な結晶欠陥は、少数キャリアの寿命を短かくすること、
p −n接合のリーク電流を増加させること等によって
素子特性を劣化させる。例えば、バイポーラ半導体素子
においては、エミッタパイプによるエミッタとコレクタ
間のリーク電流や、エミッタとべ一文間のリーク電流に
よる電流増幅率(hyxという)の低下を引き起こす。Conventionally, in the manufacturing process of semiconductor devices, crystal defects that exist in electrically active regions lead to deterioration of device characteristics.
This caused a decrease in yield. In other words, minute crystal defects in the active region shorten the lifetime of minority carriers.
The device characteristics are deteriorated by increasing the leakage current of the p-n junction. For example, in a bipolar semiconductor device, a leakage current between an emitter and a collector due to an emitter pipe or a leakage current between an emitter and a base causes a reduction in the current amplification factor (referred to as hyx).
MO8型半導体素子においても結晶欠陥はIJ =り電
流による相互コンダクタンスの低下等の悪影響を及ぼし
、歩留り低下の原因となる。一方、最近になって半導体
集積回路中の素子寸法が小さくなり、かつ、半導体集積
回路を構成する素子数が多くなると、小さな結晶欠陥は
素子特性や集積回路の歩留〜りにも大きな影響を与える
。Even in MO8 type semiconductor devices, crystal defects have an adverse effect such as a decrease in mutual conductance due to IJ current, causing a decrease in yield. On the other hand, as the dimensions of elements in semiconductor integrated circuits have recently become smaller and the number of elements constituting semiconductor integrated circuits has increased, small crystal defects have a large impact on element characteristics and the yield of integrated circuits. give.
このような結晶欠陥の発生を防止するために、従来は半
導体基板の裏面に機械的損傷を与えたり、高濃度の不純
物を導入し、基板表面付近に生ずるの汚染を防ぐため、
製造工程の初期の段階で行なわれるので、この後に複雑
な熱処理が何度も施こされる。しかし、このような繰り
返し熱処理を受けると、裏面処理の効果が半減してしま
う。In order to prevent the occurrence of such crystal defects, conventional techniques have involved mechanically damaging the backside of the semiconductor substrate or introducing high-concentration impurities to prevent contamination near the surface of the substrate.
Since this is done at an early stage in the manufacturing process, complex heat treatments are performed many times after this. However, when subjected to such repeated heat treatment, the effect of back surface treatment is halved.
さらに基板裏面に導入された不純物が高温熱処理の際に
再蒸発して、基板表面を汚染することを防止するために
、特別の工程を付加しなければならないという欠点があ
った。次に、従来のイオン注入で素子間分離領域を形成
する方法を第1図に従って説明する。Furthermore, in order to prevent impurities introduced into the back surface of the substrate from reevaporating during high-temperature heat treatment and contaminating the surface of the substrate, a special process must be added. Next, a method of forming an element isolation region by conventional ion implantation will be explained with reference to FIG.
半導体基板(p型で比抵抗10〜20Ωcm 。Semiconductor substrate (p-type, specific resistance 10-20 Ωcm).
(111)の面指数をもつ)11に、シート抵抗約80
Ω/口のn型埋込領域12を砒素スピンオン拡散法によ
り形成する。(111) with a surface index of 11, the sheet resistance is about 80
An n-type buried region 12 of Ω/hole is formed by an arsenic spin-on diffusion method.
次に、上記半導体基板11上に第1の酸化膜13を形成
し、素子間分離領域に拡散を行なうための第1の開孔部
14を設け、イオン注入法を用いて高濃度(10〜10
ケΔm)のボロンを拡散し、シート抵抗60〜100
jQloの第1の分離領域15を形成する。この時上記
第1の分離領域15の内部に、イオン注入ダメージによ
る第1の結晶欠陥領域16が形成される。(第1図a)
。次に、上記第1の酸化膜13.を除去し、1050℃
のS iH4を用いたエピタキシャル法によって、厚さ
約4μmのn型で比抵抗1Ω−CIIlのエピタキシャ
ル層17を形成する。この時、前記第1の結晶欠陥領域
16の影響により、前記第1の結晶欠陥領域16上のエ
ピタキシャル層17に結晶欠陥が発生し、第2の結晶欠
陥領域18が形成される。(第1図b)しかし、上記方
法では前記第1の結晶欠陥領域16を形成するためには
イオン注入の条件を15 16
10〜1o と高濃度にボロンを注入しなくてはならず
、反面、高濃度にボロンを拡散すると、エピタキシャル
層17を形成する際にボロンのオートド−レンゲにより
、エピタキシャル層の比抵抗の制御が困難になる等の欠
点があった。Next, a first oxide film 13 is formed on the semiconductor substrate 11, a first opening 14 is provided for diffusion into the element isolation region, and a high concentration (10 to 10 10
Diffusion of boron of Δm) and sheet resistance of 60 to 100
A first isolation region 15 of jQlo is formed. At this time, a first crystal defect region 16 is formed inside the first isolation region 15 due to ion implantation damage. (Figure 1a)
. Next, the first oxide film 13. removed and heated to 1050℃
An n-type epitaxial layer 17 with a thickness of about 4 μm and a specific resistance of 1 Ω-CIIl is formed by an epitaxial method using SiH4. At this time, due to the influence of the first crystal defect region 16, crystal defects occur in the epitaxial layer 17 on the first crystal defect region 16, and a second crystal defect region 18 is formed. (Fig. 1b) However, in the above method, in order to form the first crystal defect region 16, it is necessary to implant boron at a high concentration of 15 16 10 to 10 ion implantation conditions. However, when boron is diffused at a high concentration, auto-drainage of boron occurs when the epitaxial layer 17 is formed, making it difficult to control the resistivity of the epitaxial layer.
本発明はこのような従来の欠点を除去するものであり半
導体基板表面の電気的に不活性な領域にイオン注入法や
1000℃〜1200℃の窒素雰囲気中で熱処理を行な
い、Si膜をエピタキシャル成長させることによって活
性領域の結晶欠陥を不活性領域に吸収し、半導体装置の
製造工程における歩留りを向上することを目的とする。The present invention eliminates these conventional drawbacks and uses ion implantation or heat treatment in an electrically inactive region on the surface of a semiconductor substrate in a nitrogen atmosphere at 1000°C to 1200°C to epitaxially grow a Si film. The purpose of this is to absorb crystal defects in the active region into the inactive region and improve the yield in the manufacturing process of semiconductor devices.
本発明は不活性な領域のStのエピタキシャル成長膜に
発生した結晶欠陥により、半導体表面の電気的に活性な
領域の結晶欠陥を吸収しようというものである。The present invention attempts to absorb crystal defects in an electrically active region of a semiconductor surface by crystal defects generated in an epitaxially grown St film in an inactive region.
不活性領域としては、バイポーラ集積回路の素子間分離
領域やMO8型集積回路のフィールド領域等が使用可能
である。次に本発明の一実施例として、バイポーラ集積
回路の素子間分離領域に結晶欠陥を設け、活性領域内の
結晶欠陥を除去する方法について、第2図a % Cに
従りて説明する。As the inactive region, an element isolation region of a bipolar integrated circuit, a field region of an MO8 type integrated circuit, etc. can be used. Next, as an embodiment of the present invention, a method for providing crystal defects in the element isolation region of a bipolar integrated circuit and removing the crystal defects in the active region will be described with reference to FIG. 2A%C.
まず、第2図aに示すように、半導体基板(p型で比抵
抗10〜2oΩ−cm、(111)の面指数をもつ)2
1に、シート抵抗約80Ω沖のn型埋込領域22を砒素
スピンオン拡散法により形成する。次に、上記半導体基
板上に第1の酸化膜23を形成し、素子間分離領域に拡
散を行なうための第1の開孔部24を設け、B S G
(BaronSilicate Glass)を用い
た拡散あるいは、イオン注入法を用いてボロンを拡散し
、シート抵抗400Ω、bの第1の分離領域25を形成
する。次に、前記第1の酸化膜23をマスクにして前記
第1の分離領域25にムrまたはSi等を50〜160
Kevの注入エネルギーで、不純物注入量が約10外ω
以上でイオン注入を行ない、半導体基板表面に第1の結
晶欠陥領域26を形成する。またイオン注入のかわりに
前記半導体基板21を1200℃の高温窒素雰囲気中で
4〜6時間熱処理を行ない、上記第1の分離領域26の
半導体基板素面に第1の結晶欠陥領域26を形成する(
第2図a)。First, as shown in FIG.
1, an n-type buried region 22 with a sheet resistance of about 80Ω is formed by an arsenic spin-on diffusion method. Next, a first oxide film 23 is formed on the semiconductor substrate, a first opening 24 is provided for diffusion into the element isolation region, and the B S G
Boron is diffused using (Baron Silicate Glass) or ion implantation to form a first isolation region 25 having a sheet resistance of 400Ω, b. Next, using the first oxide film 23 as a mask, the first isolation region 25 is coated with 50 to 160 ml of silicon or the like.
With the implantation energy of Kev, the amount of impurity implanted is about 10Ω
Ion implantation is performed in the above manner to form a first crystal defect region 26 on the surface of the semiconductor substrate. Also, instead of ion implantation, the semiconductor substrate 21 is heat-treated in a high-temperature nitrogen atmosphere at 1200° C. for 4 to 6 hours to form a first crystal defect region 26 on the bare surface of the semiconductor substrate in the first isolation region 26 (
Figure 2 a).
次に、上記第1の酸化膜23を除去し、1050℃の5
iHn を用いたエピタキシャル法によって、厚さ約4
μmのn型で比抵抗1Ω−cmのエピタキシャル層す了
を形成する。この時、前記第1の結晶欠陥領域26の影
響により、前記第1の結晶欠陥領域26上のエピタキシ
ャル層27に結晶欠陥が発生し、第2の結晶欠陥領域2
8が形成される(第2図b)。Next, the first oxide film 23 is removed, and
By epitaxial method using iHn, the thickness of about 4
An n-type epitaxial layer with a resistivity of 1 Ω-cm is formed. At this time, due to the influence of the first crystal defect region 26, crystal defects occur in the epitaxial layer 27 on the first crystal defect region 26, and the second crystal defect region 2
8 is formed (FIG. 2b).
次に前記エピタキシャル層17上に第2の酸化膜2eを
形成し、素子間分離領域に拡散を行なうための第2の開
孔部3oを設けBSGを用いた拡散により40Ω沖の第
2の分離領域31を形成する。Next, a second oxide film 2e is formed on the epitaxial layer 17, a second opening 3o is provided for diffusion into the element isolation region, and a second isolation region of 40Ω is formed by diffusion using BSG. Form 31.
この際に、上記第2の分離領域31は横方向にも拡散す
るため、上記第2の結晶欠陥領域28よりも外側に広が
って形成される(第1図C)。At this time, the second isolation region 31 is also diffused in the lateral direction, so that it is formed to extend outward from the second crystal defect region 28 (FIG. 1C).
このあとの上記エピタキシャル層27の第1゜2の分離
領域25.31で囲まれた活性領域27′にコレクタ、
ベース、エミッタを形成スる際に、拡散あるいは熱処理
等を行なうが、その際に発生した結晶欠陥を上記第2の
結晶欠陥28で吸収し、活性領域27′内の結晶欠陥発
生を防止することができる。After this, a collector,
When forming the base and emitter, diffusion or heat treatment is performed, and the crystal defects generated at that time are absorbed by the second crystal defects 28 to prevent the generation of crystal defects in the active region 27'. I can do it.
しかも、前記第2の結晶欠陥領域28が第1゜2の分離
領域25,31内に含まれるため、活性領域27′と第
1,2の分離領域25.31の接合表面には結晶欠陥は
存在せず、コレクタと基板間のリーク電流の発生はなく
、耐圧は低下しない。Moreover, since the second crystal defect region 28 is included in the first and second isolation regions 25 and 31, there are no crystal defects on the bonding surface between the active region 27' and the first and second isolation regions 25 and 31. There is no leakage current between the collector and the substrate, and the withstand voltage does not decrease.
さらに第2の実施例として、結晶欠陥領域を分離領域の
内部に確実に形成する方法を第3図に従って説明する。Further, as a second embodiment, a method for reliably forming a crystal defect region inside a separation region will be described with reference to FIG.
半導体基板(p型で比抵抗10〜2oΩ−cm 。Semiconductor substrate (p-type, specific resistance 10-2oΩ-cm).
(111)の面指数をもつ)40K、シート抵抗約80
Ω沖のn型埋込領域41を砒素スピンオン拡散法により
形成する。(111) surface index) 40K, sheet resistance approximately 80
An n-type buried region 41 outside Ω is formed by an arsenic spin-on diffusion method.
次に上記半導体基板4o上に第1の酸化膜42を形成し
、さらに上記第1の酸化膜42上にホトレジスト膜イ3
を形成し、素子間分離領域内の所定の位置に素子間分離
領域より所定距離だけせまい、第1の開口部44を設け
る(第3図a)。Next, a first oxide film 42 is formed on the semiconductor substrate 4o, and a photoresist film 3 is further formed on the first oxide film 42.
A first opening 44 is provided at a predetermined position within the element isolation region, a predetermined distance smaller than the element isolation region (FIG. 3a).
次に、前記ホトレジスト膜43をエツチングマスクとし
て、HF及びNH4I系の混合液を用いて、前記第1の
酸化膜42をオーバーエツチングし、上記第′1の開口
部44より所定の距離だけ広くした第2の開孔部46を
一形成する。さらに、上記ホトレジスト膜43をマスク
にし、ムrまたはSt等を50〜150に@Vの注入エ
ネルギーで不純物注入量が約10ケ々以上でイオン注入
を行ない、?導体基板表面に第1の結晶欠陥領域46を
形成する(第3図b)、
次に、上記ホトレジスト膜43を除去し、前記第2の開
孔部46にBSG膜47を形成し、熱処理することによ
り、シート抵抗400Ω7んの第1の分離領域48を形
成する(第3図C)。Next, using the photoresist film 43 as an etching mask, the first oxide film 42 was over-etched using a mixed solution of HF and NH4I to make it wider than the '1st opening 44 by a predetermined distance. A second opening 46 is formed. Furthermore, using the photoresist film 43 as a mask, ion implantation is performed with an impurity implantation amount of about 10 or more at an implantation energy of 50 to 150 and @V using the photoresist film 43 as a mask. A first crystal defect region 46 is formed on the surface of the conductor substrate (FIG. 3b). Next, the photoresist film 43 is removed, a BSG film 47 is formed in the second opening 46, and heat treatment is performed. As a result, a first isolation region 48 having a sheet resistance of 400Ω7 is formed (FIG. 3C).
次に、上記BSG膜47及び第1の酸化膜42を除去し
、1060℃SiH4を用いたエピタキシャル法によっ
て、厚さ4μmのn型で比抵抗12−印のエピタキシャ
ル層49を形成する。この時、前記第1の結晶欠陥領域
46の影響により、上記第1の結晶欠陥領域46上のエ
ピタキシャル層49に結晶欠陥が発生し、第2の結晶欠
陥領域6oが形成される(第3図d)。Next, the BSG film 47 and the first oxide film 42 are removed, and an n-type epitaxial layer 49 having a thickness of 4 μm and having a resistivity of 12 − is formed by an epitaxial method using SiH 4 at 1060° C. At this time, due to the influence of the first crystal defect region 46, crystal defects occur in the epitaxial layer 49 on the first crystal defect region 46, and a second crystal defect region 6o is formed (Fig. 3). d).
次に、前記エピタキシャル層49上に、第2の酸化膜6
1を形成し、素子間分離領域に拡散を行なうための前記
第1の開孔部44より、所定の距離だけ広い第3の開孔
部52を設け、BSGを用いた拡散により4oΩ2んの
第2の分離領域63を形成する、
上記工程により、前記第2の結晶欠陥領域51は、上記
第2の分離領域63内に含まれるため、活性領域49′
と第2の分離領域63の接合表面には結晶欠陥は存在せ
ず、コレクタと基板間のリーク電流の発生はなく、さら
に耐圧も低下しない。Next, a second oxide film 6 is formed on the epitaxial layer 49.
A third opening 52 is provided which is wider by a predetermined distance than the first opening 44 for diffusion into the element isolation region. By the above step of forming the second isolation region 63, the second crystal defect region 51 is included in the second isolation region 63, so that the active region 49'
There are no crystal defects on the bonding surface between the first isolation region 63 and the second isolation region 63, no leakage current occurs between the collector and the substrate, and furthermore, the withstand voltage does not decrease.
以上のように、本発明は、基板の裏面処理に比べて、短
かい工程で行なうことができ、しかも、基板裏面に不純
物を高濃度に拡散して、結晶欠陥を裏面に吸収する方法
と比較して、本発明のように、不活性領域にて吸収する
方が活性領域と距離的に近いので、欠陥吸収効果も大き
い。また、上記第2の結晶欠陥61は、エピタキシャル
成長の際に、結晶のズレが発生しt9ためにできたもの
で、以後熱処理を繰りかえしても、成長することはなく
、活性領域に悪影響を及ぼさず、リーク電流の増大、耐
圧が低下することはない。さらに、従来のよ51C、ボ
ロン等を高濃度に注入して欠陥部分を形成すると、オー
トドーピングによりエピタキシャル層の比抵抗に悪影響
を及ぼすが、本発明のように、ムrまたはSi等の不活
性な不純物をイオなく、エピタキシャル層の比抵抗に悪
影響は及ぼさない。以上のように本発明は活性領域の結
晶欠陥を不活性領域に吸収し、半導体装置の製造工程に
おける歩留りを向上することができる。As described above, the present invention can be performed in a shorter process time than processing the back side of a substrate, and is also compared to a method in which impurities are diffused at a high concentration on the back side of the substrate and crystal defects are absorbed into the back side. Therefore, as in the present invention, absorption in the inactive region is closer to the active region in terms of distance, so the defect absorption effect is greater. Furthermore, the second crystal defect 61 was created due to crystal misalignment occurring at t9 during epitaxial growth, and even if heat treatment is repeated thereafter, it will not grow and will not have an adverse effect on the active region. , there is no increase in leakage current and no decrease in breakdown voltage. Furthermore, when defective parts are formed by implanting 51C, boron, etc. at a high concentration as in the conventional method, autodoping adversely affects the resistivity of the epitaxial layer. It does not contain ions of impurities and does not adversely affect the resistivity of the epitaxial layer. As described above, the present invention can absorb crystal defects in the active region into the inactive region, thereby improving the yield in the manufacturing process of semiconductor devices.
第1図a、bは従来の分離領域形成方法を説明するため
の半導体装置の断面図、第2図a ”’−aは本発明の
第1の実施例を説明するための半導体装置の断面図、第
3図a % eは本発明の第2の実施例を説明するため
の半導体装置の断面図である。
21.40・・・・・・Sl基板、27,49・・・・
・・エピタキシャル層、25.48・・・・・・第1の
分離領域、26゜46・・・・・・第1の結晶欠陥領域
、28,51・・・−・・第2の結晶欠陥領域、31,
53・・・・・・第2の分離領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名1A
2 図
蘂2図
易 3 図
蘂3図FIGS. 1a and 1b are cross-sectional views of a semiconductor device for explaining a conventional isolation region forming method, and FIG. 21.40...Sl substrate, 27,49...
...Epitaxial layer, 25.48...First isolation region, 26°46...First crystal defect region, 28,51...Second crystal defect area, 31,
53...Second separation area. Name of agent: Patent attorney Toshio Nakao and 1 other person 1A
2 Figure 2 Figure easy 3 Figure 3 Figure 3
Claims (1)
欠陥領域を形成する工程と、前記半導体基板主表面にエ
ピタキシャル層を形成し、前記第1の結晶欠陥領域上の
エピタキシャル層に第2の結晶欠陥領域を形成する工程
と、前記エピタキシャル層を貫通して前記−導電形の分
離領域を前記第2の結晶欠陥領域が前記分離領域に含ま
れるように形成する工程とよりなる半導体装置の製造方
法。forming a first crystal defect region in a part of the main surface of a semiconductor substrate of one conductivity type; forming an epitaxial layer on the main surface of the semiconductor substrate; and forming an epitaxial layer on the first crystal defect region. a step of forming a second crystal defect region; and a step of penetrating the epitaxial layer to form an isolation region of the − conductivity type such that the second crystal defect region is included in the isolation region. Method of manufacturing the device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12893381A JPS5830144A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12893381A JPS5830144A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5830144A true JPS5830144A (en) | 1983-02-22 |
Family
ID=14996985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12893381A Pending JPS5830144A (en) | 1981-08-18 | 1981-08-18 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5830144A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09232324A (en) * | 1996-02-23 | 1997-09-05 | Nec Corp | Semiconductor substrate and its manufacture |
-
1981
- 1981-08-18 JP JP12893381A patent/JPS5830144A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09232324A (en) * | 1996-02-23 | 1997-09-05 | Nec Corp | Semiconductor substrate and its manufacture |
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