JPS5829007B2 - Digital to analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter using a counter.

Various digital-to-analog converters are used depending on the purpose, and most of them are used to convert digital signals to analog signals.

Their use is, for example, in reproducing audio signals from digital data from digital transmission systems, and in reproducing analog display waveforms from stored or processed digital information.

Manufacturers of digital-to-analog converters as a specialty item in the electronics market intend to produce products for general use, but two important parameters considered by buyers of these items are the conversion rate, which indicates the performance of the device. and resolution.

Here, conversion rate is the speed at which a digital signal can be converted to an analog value, and resolution is the accuracy of the converted value relative to the digital input.

In general, the higher the conversion rate and resolution, the higher the digital
Analog converters are expensive.

A special use of digital-to-analog converters in electronic equipment controlled by computers or microprocessors is to set the operating or threshold voltages of various elements instead of potentiometers or voltage dividers.

For example, the reference voltage threshold of the input comparator is automatically set based on program control by a digital-to-analog converter.

High-resolution digital-to-analog converters are needed to set voltage levels with high precision and to make small incremental changes when adjusting voltage levels.

Available digital-to-analog converters with high resolution characteristics are generally expensive and complex.

Particularly when several digital-to-analog converters are required, cost and power consumption become an issue in their use.

Accordingly, one of the objects of the present invention is to provide a new digital-to-analog converter.

Another object of the present invention is to provide a high resolution digital-to-analog converter.

Still another object of the present invention is to provide a digital-to-analog converter that can be easily extended to a multi-channel converter.

Another object of the present invention is to provide a digital-to-analog converter that is inexpensive and consumes low power.

BRIEF DESCRIPTION OF THE DRAWINGS The subject matter of the invention will be particularly pointed out in the description that follows, and the structure and method of operation of the invention, as well as other advantages and objects of the invention, will be understood from the following description, taken in conjunction with the accompanying drawings.

According to the present invention, the high-resolution digital-to-analog converter has a reference counter (hereinafter referred to as R counter) as the first counter means and a presettable counter (hereinafter referred to as P counter) as the second counter means. , loads this P counter with a plurality of digital bits corresponding to the number to be converted to an analog voltage.

The R and P counters operate on the same clock signal and shift the output of the P counter relative to the output of the R counter by an amount proportional to the digital number loaded into the P counter.

The outputs of the two counters are applied to an exclusive OR gate (hereinafter simply referred to as an OR gate) serving as a pulse signal generating means to generate a pulse width modulated output signal.

This pulse width modulation signal is filtered by a low-pass filter serving as an analog signal generating means to generate an analog voltage.

One or more P counters operate in conjunction with a single R counter to provide a multi-channel digital-to-analog converter to set as many voltage levels as a particular system requires.

This configuration eliminates the need for an independent R counter for each channel, thereby further reducing the number of parts used.

The pulse width modulated output signal may be passed through a switching circuit before being filtered to bring it within predetermined upper and lower voltage limits.

Therefore, the accuracy of the subsequently generated analog voltage level can be increased.

In the accompanying drawings, FIG. 1 shows a basic principle diagram of a digital-to-analog converter according to the invention.

The output terminal of the clock generator 10 is connected to the clock input terminal CLK of a binary R counter 12 and a binary P counter 14.

The outputs of these two counters are connected to the inputs of an OR gate 160, and the output of this OR gate 16 is connected to a low pass filter 18.

This low pass filter 18 preferably consists of a series resistor 20 shunted by a capacitor 22.

The operation of the digital-to-analog converter shown in FIG. 1 will be explained with reference to the waveforms shown in FIG.

Parallel digital data representing the number to be converted to analog voltage is applied to digital input line 30.

For purposes of explanation, this digital input line 30 shows a 4-bit input of digital data.

It will be appreciated that the number of inputs can be increased and easily applied to any number of digital bits to improve conversion accuracy.

Time T.

, waveform A is logic “low” and reset terminal 3
2 to the clear input terminals CLR and P of the R counter 12.
It is applied to the load input terminal LOAD of the counter 14.

Therefore, the R counter 12 is reset to O and the digital data input on line 30 is loaded into the P counter 14.

At time T, a positive transition of waveform A is applied to terminal 32, disabling the counter and energizing the counter to count clock pulses.

At time T2 when the R counter 12 completes its counting up to a predetermined number of counts, the output of the R counter 12 changes from a "low" state to a "high" state as shown by the positive change in waveform B.

Similarly, when the R counter 12 completes counting at times T4 and T6, its output state changes.

For a 4-bit system, the count number is 15, so every 16th clock pulse resets the counter to O and starts counting again until the 15th clock pulse.

Therefore, the time intervals represented by T2-T1, T4-T2 and T6-T4 are equal.

The P counter 140 count factor is equal to the R counter 120 count factor, but the first count of the P counter 14 after time T1 is delayed according to the number preset with the digital input word.

Therefore, P counter 1 at times T3 and T5 of waveform C
The change in the output of R counter 12 is shifted relative to the change in the output of R counter 12.

The amount of shift in this example is any number between 0 and 150.

Of course, if counter 14 is preset to 0, the outputs of both counters 12 and 14 will change synchronously, i.e. waveform B.
and C are in phase.

Similarly, if counter 14 is preset to 8, the outputs of counters 12 and 14 will again vary synchronously, but 180 degrees out of phase.

When the counter outputs represented by waveforms B and C are applied to OR gate 16, the output of OR gate 16 changes to a logic "high" when only one counter output is a logic "high".

Thus, in the illustrated example, the output waveform of OR gate 16 is a logic "high" during periods T3-T2, T5-T4, etc.

From the above it can be easily seen that the output pulse width of the waveform is determined by the digital input being converted.

Therefore, the pulse width modulated PWM output from the OR gate 16 is P
Occurs depending on the value of the digital input that resets the counter 14.

Further, when the preset numerical value is 0 or 8, respectively, the output from the OR gate 16 is always "low" or "high".

The pulse width modulated output from OR gate 16 is filtered by low pass filter 18 to produce a voltage between upper and lower limit levels that is proportional to the numerical value of the input digital word.

This substantially direct current voltage level is available at analog output terminal 36.

In the 4-bit system example described above, the analog voltage can be any one of eight independent levels.

The system may be expanded to improve resolution.

For example, in an 8-bit system, the analog voltage ratio will be 128 independent levels within the same voltage limit.

FIG. 3 is a detailed circuit diagram of a preferred embodiment of the present invention;
One or more P counters work together with a single R counter to form a multi-channel digital-to-analog converter.

N (any number) channels may be provided to generate N voltage levels, which can be used, for example, as reference voltages for input comparators in permanent monitors and test systems.

Each channel may be independently loaded and preset by computer control.

Although the circuit operation of FIG. 3 is substantially the same as that described with respect to the block diagram of FIG. 1, similar elements as in FIG. .

Furthermore, all transducers for channels 1-N are of the same construction and will therefore be generally described below.

Clock generator 10 generates a suitable lock signal and applies this clock signal to one input of AND gate 50.

The output terminal of the AND gate 50 is connected to the clock input terminal C of the R counter 12 and the P counter 14.

The R counter 12 is constructed from three 4-bit counter circuits 52, 54 and 56 connected in series to form a 12-bit counter.

These counter circuits are preferably commercially available 74LS93
type integrated circuits are used.

Similarly, each of the P counters 14 is connected to three 4
Consisting of bit counter circuits 62, 64 and 66,
Each channel is a 12-bit P counter.

These P counter circuits are preferably commercially available. 74LS 197 type integrated circuit.

A control signal that clears the R counter 12 is applied to the input of each counter circuit 52, 54, and 56 via an input LR input terminal 70.

This control signal is further applied to the other input terminal of the AND gate 50 to clear and reset the R counter for a period AN
D-gate 50 is closed to inhibit the clock signal.

The control signal has substantially the same waveform as A in FIG. 2, and at time T1, the clock signal is activated and the counter starts operating.

As mentioned above, each of the P counters 14 may be independently loaded and preset.

1 12-bit digital input to be converted to analog signal
It is applied via two human power lines 72 to the data input terminals DATA of the P counter circuits 62, 64 and 66.

This human power line is arranged in a conventional manner, with the first line counting from the left end to the right end being the lowest pitch (LSB) and 1
The first line is the most significant bit (MSB).

Since the 12th line bit is uncertain, the total resolution of this converter is 11 bits or '/2048.

The load command signal is input to the preset input terminal P of the P counter circuit.
R8T is applied through terminal 76 to load the digital input to data input DATA.

During the period when the R counter is cleared and reset, the P counter is loaded and preset.

Therefore, at time T when the clock signal is activated, except that the R counter and P counter in FIG. 3 have a count of 4096 because they are a 12-bit system.
It operates in the same manner as described above with respect to FIG.

Since the output of the counter is applied to the OR gate 16 for each channel, the output of the OR gate 16 is pulse width modulated in accordance with the number f of digital inputs for presetting.

Complementary metal-oxide-semiconductor field effect transistor (CM
A switch circuit consisting of a pair of series connected active semiconductor devices, such as O8-FETs 80 and 82, is provided to produce an accurate output voltage within a predetermined analog voltage range.

Therefore, the output of the OR gate 16 is switched between the ground potential and a specific positive potential (R, EFO).

The +VREFO values for each channel may be the same or different.

The +VREFO value may also be programmable to a specific desired voltage.

Additionally, the ground potential can be programmed to a voltage level - VREF.
You may set any desired voltage range by replacing it with .

The pulse width modulated output is filtered by a low pass filter 18.

Low pass filter 18 includes the passive components of resistor 8486 and capacitors 94-96, and the active component of amplifier 100 connected as a voltage follower.

The substantial DC voltage level generated by filter 18 is available at output terminal 36.

From the above description, it will be appreciated that one or more P counters can be operated in conjunction with a single R counter to form a multi-channel digital-to-analog converter that converts one or more digital inputs to analog voltages.

Furthermore, the multi-channel digital-to-analog converter may be programmable and therefore computer controlled.

As mentioned above, the digital-to-analog converter of the present invention includes an R counter as the first counter means, a P counter as the second counter means, an OR gate as the pulse signal generating means, a low-pass filter as the analog signal generating means, etc. However, since there is no need to provide an R counter for each channel and only one R counter is required regardless of the number of channels, the configuration is simple, inexpensive, and consumes less power.

In addition, the number of channels can be easily increased, and the number of bits of a digital input signal can be increased simply by connecting counters in series, so resolution can be easily improved.

Further, according to the present invention, a clock generator, a first and a second
A gate circuit is provided between the counter means and the control signal closes the gate circuit to prohibit passage of the clock signal, and also presets the second counter means during the period when the first counter is cleared. , the digital input signal to the digital-to-analog converter can be switched even during one cycle of counting operation of the first or second counter means.

That is, the response to digital input signals is fast.

Furthermore, according to the present invention, the second counting means is preset only when the digital input signal changes, so that once the digital input signal is preset, the corresponding analog output signal is maintained until the point at which the digital input signal changes. In other words, the corresponding analog output signal is maintained even if the digital input signal is not stored in a register or the like.
Although the foregoing describes preferred embodiments of the invention, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit of the invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic principle of the present invention, FIG. 2 is a waveform diagram for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram of a preferred embodiment of the present invention. 10 is a clock oscillator, 12 is a first counter means, 14
1 is a second counter means, 16 is an exclusive OR gate which is a pulse signal generating means, and 18 is an analog signal generating means.

Claims (1)

[Claims] 1 A clock generator that generates a clock signal, a gate circuit that selectively passes the clock signal, and a single first clock generator that generates an output signal after counting the clock signals that have passed through the gate circuit to a predetermined number. counter means;
(4) a plurality of second counter means for generating an output signal after counting the clock signals which have been preset by each of the plurality of digital signals and passed through the gate circuit up to the predetermined number; and the first and second counter means, respectively. a plurality of pulse signal generation means for generating output pulse signals whose pulse widths are controlled according to the phase difference of the output signals; and a plurality of analogues for generating analog signals in accordance with the output pulse signals from the pulse signal generation means, respectively. and signal generating means,
supplying a control signal to the first counter means and the gate circuit to clear the first counter means and close the gate circuit to prohibit passage of the clock signal;
A digital-to-analog converter, characterized in that the second counter means is preset during a period in which the first counter means is cleared.