JPS5825254A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS5825254A
JPS5825254A JP56115503A JP11550381A JPS5825254A JP S5825254 A JPS5825254 A JP S5825254A JP 56115503 A JP56115503 A JP 56115503A JP 11550381 A JP11550381 A JP 11550381A JP S5825254 A JPS5825254 A JP S5825254A
Authority
JP
Japan
Prior art keywords
chips
semiconductor device
insulating
chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56115503A
Other languages
Japanese (ja)
Other versions
JPS5943826B2 (en
Inventor
Shoji Takishima
滝島 昭二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP56115503A priority Critical patent/JPS5943826B2/en
Priority to US06/400,815 priority patent/US4843035A/en
Publication of JPS5825254A publication Critical patent/JPS5825254A/en
Publication of JPS5943826B2 publication Critical patent/JPS5943826B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

Abstract

PURPOSE:To easily improve the characteristic of a device having an elastic surface wave element which requires an electrode of specially minute width, by arranging chips made of different materials on a plane through the intermediary of an insulating connection part, and by providing metal wirings on the continuous surfaces of the chips. CONSTITUTION:Chips A and B are arranged horizontally on a vacuum chuck 13 made of fluorocarbon resin and having a smooth surface, with their surfaces, whereon electrodes are formed, on the lower side and with a gap 14 between them. The chips are sucked up by the chuck under vacuum, epoxy resin is filled up in the gap 14 and subjected to a setting process, and thereby an insulating connection part 9 is formed. The chips A and B thus incorporated in one body are removed from the chuck 13 and arranged on a package substrate 3 being an insulator whereon a metal plate or an electroconductive layer is formed, with the back surfaces of the chips A and B coated with an insulating bonding agent 10 and an electroconductive bonding agent 11, respectively. Then a desired setting process is applied thereto. The combination of the bonding agents is selected properly in accordance with the materials and structures of the chips A and B. Next, a metal is connected thereto and a wiring 12, an electrode 6, etc. are attached thereto. Since the wiring is not present in a space between the chips, the increase in the capacity of leads and in a feedthrough is prevented, and the high-frequencey characteristic of the device is maintained.

Description

【発明の詳細な説明】 本発明は、異なる材質から成る複数のチップを含む半導
体装置゛特に半導体材料および圧電材料から成る複数の
チップを含む半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a plurality of chips made of different materials, and particularly to a semiconductor device including a plurality of chips made of a semiconductor material and a piezoelectric material.

最近、弾性表面波と半導体内キャリアを結合させること
により、減衰あるいは増巾等の線型動作を行わせる表面
波増巾器や、コンボリューションあるいはコリレーショ
ン等の非線型動作を行わせるようにした表面コンボルバ
等の半導体装置の研究、開発が盛んに行われている。
Recently, surface wave amplifiers have been developed that perform linear operations such as attenuation or amplification by combining surface acoustic waves with carriers in semiconductors, and surface wave amplifiers that perform nonlinear operations such as convolution or correlation. Research and development of semiconductor devices such as convolvers are actively being conducted.

このためには弾性表面波を発生させるだめの弾性表面波
素子と半導体内キャリアを発生させるだめの半導体素子
を必要とし、前者はLiNbO3゜LiTa0a等の圧
電材料によって後者はシリコン、金属間化合物等の半導
体材料によって構成され画素子は共通基板上に配置され
て電気的な接続がなされる。
For this purpose, a surface acoustic wave element that generates surface acoustic waves and a semiconductor element that generates carriers within the semiconductor are required. The pixel elements made of semiconductor material are arranged on a common substrate and electrically connected.

第1図は以上のような半導体装置の従来構造を示す斜視
図で、1は弾性表面波素子を構成するチップA12は半
導体素子を構成するチップB、 3は以上の両チップA
、Bを配置するだめのパッケージ基板、4はパッケージ
基板3に設けられたリード端子、5,6はチップA、B
表面に設けられた電極、7は上記両電極5,6間に接続
されたボンディングワイヤ、8は電゛極5,6とリード
端子4間に接続されたボンディングワイヤである。
FIG. 1 is a perspective view showing the conventional structure of the semiconductor device as described above, in which 1 is a chip A forming a surface acoustic wave element, 2 is a chip B forming a semiconductor element, and 3 is both the above chips A.
, B are placed on the package board, 4 is a lead terminal provided on the package board 3, and 5 and 6 are chips A and B.
Electrodes provided on the surface, 7 a bonding wire connected between the electrodes 5 and 6, and 8 a bonding wire connected between the electrodes 5 and 6 and the lead terminal 4.

ところで弾性表面波素子1と半導体素子2は異なる材質
から成っているため、画素子を組み合せて一つの半導体
装置となすには製法上多くの問題がある。例えば画素子
の電気的接続を行う場合、弾性表面波素子10表面には
電気的信号を入出力させるだめのトランスデユーサと称
される1〜2μ巾のkl等のストライプ状の電極5が多
数形成されているが、この微小中電極5を半導体素子表
面の電極6と25μ程のAll 、 Au等のワイヤ7
によりワイヤボンディング法によって接続する必要があ
る。
By the way, since the surface acoustic wave element 1 and the semiconductor element 2 are made of different materials, there are many problems in the manufacturing method when combining the pixel elements to form one semiconductor device. For example, when electrically connecting a pixel element, the surface of the surface acoustic wave element 10 has a large number of striped electrodes 5 such as 1-2μ wide KL called transducers for inputting and outputting electrical signals. However, this minute medium electrode 5 is connected to an electrode 6 on the surface of the semiconductor element and a wire 7 made of Al, Au, etc. of about 25 μm.
Therefore, it is necessary to connect by wire bonding method.

しかし上記微小中電極5はフォトリソグラフィー法によ
り加工されて形成される関係上、加工精度の点でその厚
さも通常03〜0.5μに制限されるようになっていて
、上記ワイヤボンディングを行うには1μ以上の厚さが
ないと信頼性ある接続は得られない。
However, since the minute medium electrode 5 is processed and formed by photolithography, its thickness is usually limited to 0.3 to 0.5 μm from the viewpoint of processing accuracy, and it is difficult to perform the wire bonding. A reliable connection cannot be obtained unless the thickness is 1μ or more.

またワイヤボンディング法により接続されたワイヤは、
空中を渡って画素子に接続されているために、高周波信
号を扱う場合にリード容量やフィードスルーを増大させ
て装置の特性を著るしく低下させている。
In addition, wires connected by the wire bonding method are
Because they are connected to pixel elements across the air, lead capacitance and feedthrough increase when handling high-frequency signals, significantly degrading the characteristics of the device.

本発明は以上の問題に対処してなされたもので、異なる
材質から成る複数のチップを絶縁性接続部を介して一平
面上に配置し、上記複数のチップ間表面には密着するよ
うに金属配線を設けるようにして従来欠点を除去し得る
ように構成した半導体装置およびその製法を提供するこ
とを目的とするも−のである。
The present invention has been made in response to the above problems, and consists of a plurality of chips made of different materials arranged on one plane through insulating connections, and a metal plate placed between the plurality of chips so as to be in close contact with each other. It is an object of the present invention to provide a semiconductor device configured to eliminate the conventional drawbacks by providing wiring, and a method for manufacturing the same.

以下図面を参照して本発明実施例を説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明実施例による半導体装置を示す断面図で
第1図と同一部分は同一番号で示し、9は弾性表面波素
子1用チツプAと半導体素子2用チツプBとの間隙に充
填された絶縁性接続部で上記両チップA、Bと同一平面
となるように設けうれ、例えばポリイミド、エポキシ樹
脂等の高分子化合物によって構成される。10はチップ
人の裏面とパッケージ基板3間に設けられた他の絶縁性
接続部で、シリコーン系、エポキシ系樹脂等の弾力を有
する可撓性材料によって構成される&11はチップBの
裏面とパッケージ基板3間に設けられた導電性接続部で
、金属粉末を含んだ各種樹脂材料によって構成され、電
気的、放熱的に優れた状態に保持される。12はチップ
Aおよびチク18表面に渡って密着するように設けられ
たA7 、 Au等の金属配線である。この金属配線1
2は最初にチップA。
FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. The same parts as in FIG. The insulating connection portion is provided so as to be flush with both chips A and B, and is made of a polymer compound such as polyimide or epoxy resin. Reference numeral 10 indicates another insulating connection part provided between the back surface of the chip B and the package substrate 3, and is made of a flexible material with elasticity such as silicone or epoxy resin. &11 indicates the connection between the back surface of the chip B and the package board 3. A conductive connecting portion provided between the substrates 3, made of various resin materials containing metal powder, and maintained in an excellent electrical and heat dissipating state. Reference numeral 12 denotes a metal wiring made of A7, Au, etc., which is provided so as to be in close contact with the surface of the chip A and the chip 18. This metal wiring 1
2 is chip A first.

Bおよび絶縁性接着材9表面に全面的に蒸着法等により
金属材料が付着された後、フォトリソグラフィー法によ
り所望形状に加工されことにより形成される。この金属
配線12を形成する時同時にチップ自体の電極例えばチ
ップ人表面の微小中電極5を形成するようにしても良い
。これはフォトリソグラフィー法に用いられるマスクの
パターンを変えるだけで容易に得られる。第3図は第2
図の構造を得るだめの製法を示す断面図で、以下工程順
に説明する。
A metal material is deposited on the entire surface of B and the insulating adhesive 9 by a vapor deposition method or the like, and then processed into a desired shape by a photolithography method. At the same time as this metal wiring 12 is formed, an electrode of the chip itself, for example, a minute electrode 5 on the surface of the chip may be formed. This can be easily obtained by simply changing the mask pattern used in photolithography. Figure 3 is the second
This is a sectional view showing a manufacturing method for obtaining the structure shown in the figure, and will be explained in the order of steps below.

先ず第3図ta>のように、チップ人およびチップBを
表面(電極形成面)を下側にしてバキュームチャック1
3表面に間隙14を設けるようにして水平に配置する。
First, as shown in FIG.
3. They are arranged horizontally with a gap 14 between the two surfaces.

バキュームチャック13は次に用いる絶縁性接着材9と
接着しない材質例えばフッ素樹脂、ポリエチレン、シリ
コーン樹脂等の材料によって構成され、その表面は平滑
に形成される。
The vacuum chuck 13 is made of a material that does not adhere to the insulating adhesive 9 that will be used next, such as fluororesin, polyethylene, silicone resin, etc., and its surface is formed to be smooth.

チップAおよびチク18表面をバキュームチャック13
によシ吸引した状態で、チップA、B間の間隙14内に
流動状態のポリイミド、エポキシ樹脂等の高分子化合物
を充填して間隙14を完全に埋め込むようにする。続い
て所定の硬化処理を行って絶縁性接続部9を形成した後
、この絶縁性接続部9によって一体化されたチップA、
Bをバキュームチャック13表面より取り除く。バキュ
ームチャツク13表面の平滑さによってチップA、Bお
Lび絶縁性接続部9は同一平面上に配置されたものが得
られる。
Vacuum chuck 13 the surface of chip A and chip 18.
In a strongly suctioned state, the gap 14 between the chips A and B is filled with a fluid polymer compound such as polyimide or epoxy resin so that the gap 14 is completely filled. Subsequently, after performing a predetermined curing treatment to form an insulating connection part 9, the chip A integrated by this insulating connection part 9,
Remove B from the surface of the vacuum chuck 13. The smoothness of the surface of the vacuum chuck 13 allows the chips A, B and the insulating connection portion 9 to be arranged on the same plane.

次に第3図(blのように、金属板あるいは導電層が形
成された絶縁板等から成るパッケージ基板3上に、チッ
プA、BをチップA裏面にはシリコーン系、エポキシ系
樹脂等の絶縁性接着材を塗布しかつチップB裏面には導
電性樹脂等の導電性接着材を塗布した状態で配置する。
Next, as shown in Figure 3 (bl), chips A and B are placed on a package substrate 3 made of a metal plate or an insulating plate on which a conductive layer is formed, and the back side of chip A is insulated with silicone, epoxy resin, etc. A conductive adhesive such as a conductive resin is applied to the back surface of the chip B, and the chip B is placed with a conductive adhesive such as a conductive resin applied thereto.

続いて所望の硬化処理を行って他の絶縁性接続部10お
よび導電性接続部11を形成する。上記絶縁性接着材お
よび導電性接着材の組み合せは上記のものに限らず、チ
ップA、B材質および構造等に応じ他の材料の組み合せ
にすることができる。
Subsequently, a desired curing treatment is performed to form other insulating connecting portions 10 and conductive connecting portions 11. The combination of the insulating adhesive and the conductive adhesive is not limited to the above, but other materials may be used depending on the materials and structure of the chips A and B.

次に第3図(c)の−ように、パッケージ基板3上に固
定されてるチップA、Bの表面に公知の蒸着法あるいは
スパッタリング法等によりAl、 Au等の金属材料を
付着させる。続いてフォトリソグラフィー法でもって不
要部を除去することによシ、所望形状に加工されたチッ
プA、B表面に渡る金属配線12を形成する。この金属
配線12をフォトリソグラフィー法によって加工する時
、同時にチップAsるいはB自体の電極5あるいは6、
又は両者5.6を形成することもできる。
Next, as shown in FIG. 3(c), a metal material such as Al or Au is deposited on the surfaces of the chips A and B fixed on the package substrate 3 by a known vapor deposition method or sputtering method. Subsequently, by removing unnecessary portions using a photolithography method, metal wiring 12 extending over the surfaces of chips A and B processed into a desired shape is formed. When processing this metal wiring 12 by photolithography, at the same time, the electrode 5 or 6 of the chip As or B itself,
Alternatively, both 5.6 and 5.6 can be formed.

以上により第2図の構造を得ることができる。Through the above steps, the structure shown in FIG. 2 can be obtained.

第4図は特に金属配線12付近の構造を拡大して示す斜
視図である。
FIG. 4 is an enlarged perspective view particularly showing the structure near the metal wiring 12. FIG.

以上説明して明らかなように本発明によれば、異なる材
質から成る複数のチップを絶縁性接続部を介して一平面
上に配置し、上記複数のチップ間表面には密着する!う
に金属配線を設けるように構成するものであるから、金
属配線はボンディング法により接続する必要はなくなっ
て、金属配線の厚さに直接関係なしにチップ間の電気的
接続を行うことができるので、信頼性のある接続が得ら
れる。
As is clear from the above description, according to the present invention, a plurality of chips made of different materials are arranged on one plane via insulating connection parts, and are in close contact with the surfaces between the plurality of chips! Since the structure is such that metal wiring is provided, there is no need to connect the metal wiring using a bonding method, and electrical connections between chips can be made regardless of the thickness of the metal wiring. Get a reliable connection.

また金属配線はチップ間の空中には存在しないので、高
周波信号を扱う場合でもリード容量やフィードスルーの
増大は防止されるようになり、装置の特性が低下するこ
とはなくなる。
Furthermore, since metal wiring does not exist in the air between chips, increases in lead capacitance and feedthrough are prevented even when handling high frequency signals, and device characteristics do not deteriorate.

チップの数は実施例に示したように2個に限定される必
要はなく、3個以上用いる場合にも適用することができ
る。
The number of chips does not need to be limited to two as shown in the embodiment, and the present invention can also be applied to a case where three or more chips are used.

本発明によって特に表面に微小中電極を必要とする弾性
表面波素子を含む半導体装置の特性改善が容易となり、
巾広い用途への適用が期待できるようになる。
The present invention makes it easy to improve the characteristics of semiconductor devices including surface acoustic wave elements that require small medium electrodes on the surface.
It can be expected to be applied to a wide range of applications.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第4図は従来および本発明実施例を示す斜
視図、第2図および第3図(a)乃至(C)はいずれも
本発明実施例を示す断面図である。 1・・・チップA(弾性表面波素子)、2・・・チップ
B(半導体素子)、3・・・パッケージ基板、5,6・
・・チップ電極、9.10・・・絶縁性接続部、11・
・・導電性接続部、1〔・・金属配線。 第1図 第2図 第3図 (0) 第4図
1 and 4 are perspective views showing a conventional device and an embodiment of the present invention, and FIGS. 2 and 3 (a) to 3(C) are sectional views showing an embodiment of the present invention. 1... Chip A (surface acoustic wave element), 2... Chip B (semiconductor element), 3... Package substrate, 5, 6...
...Chip electrode, 9.10...Insulating connection part, 11.
...Conductive connection part, 1 [...Metal wiring. Figure 1 Figure 2 Figure 3 (0) Figure 4

Claims (1)

【特許請求の範囲】 1、一平面上に配置された異なる材質から成る複数のチ
ップと、これら複数のチップ間に充填され上記チップと
同一表面を構成している絶縁性接続部と、上記複数のチ
ップ間表面に設けられた金属配線とを含むことを特徴と
する半導体装置。 2、上記複数のチップが半導体材料および圧電材料から
成ることを特徴とする特許請求の範囲第1項記載の半導
体装置。 3、上記圧電材料から成るチップが弾性表面波素子であ
ることを特徴とする特許請求の範囲第1項又は第2項記
載の半導体装置。 4、異なる材質から成る複数のチップを一平面上に配置
する工程と、上記複数のチップ間に絶縁性接着材を充填
する工程と、上記複数のチップ間表面に渡るように金属
配線を設ける工程、とを含むことを特徴とする半導体装
置の製法。 5、上記金属配線と同時にチップ自体の電極を設けるこ
とを特徴とする特許請求の範囲第4項記載の半導体装置
の製法。
[Claims] 1. A plurality of chips made of different materials arranged on one plane, an insulating connection portion filled between the plurality of chips and forming the same surface as the chips, and the plurality of chips A semiconductor device comprising: a metal wiring provided on an interchip surface of the semiconductor device. 2. The semiconductor device according to claim 1, wherein the plurality of chips are made of a semiconductor material and a piezoelectric material. 3. The semiconductor device according to claim 1 or 2, wherein the chip made of the piezoelectric material is a surface acoustic wave element. 4. A step of arranging a plurality of chips made of different materials on one plane, a step of filling an insulating adhesive between the plurality of chips, and a step of providing metal wiring across the surfaces between the plurality of chips. , and a method for manufacturing a semiconductor device. 5. A method for manufacturing a semiconductor device according to claim 4, characterized in that electrodes of the chip itself are provided at the same time as the metal wiring.
JP56115503A 1981-07-23 1981-07-23 Semiconductor device and its manufacturing method Expired JPS5943826B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56115503A JPS5943826B2 (en) 1981-07-23 1981-07-23 Semiconductor device and its manufacturing method
US06/400,815 US4843035A (en) 1981-07-23 1982-07-22 Method for connecting elements of a circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56115503A JPS5943826B2 (en) 1981-07-23 1981-07-23 Semiconductor device and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5825254A true JPS5825254A (en) 1983-02-15
JPS5943826B2 JPS5943826B2 (en) 1984-10-24

Family

ID=14664125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56115503A Expired JPS5943826B2 (en) 1981-07-23 1981-07-23 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS5943826B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149453A (en) * 1984-08-17 1986-03-11 Clarion Co Ltd Electrode wiring structure of composite semiconductor device
US10458821B2 (en) 2016-04-26 2019-10-29 Toyota Jidosha Kabushiki Kaisha Mounting structure for a peripheral information detection sensor used in a vehicle including an automatic driving system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147038A (en) * 1984-01-10 1985-08-02 Tokyo Gas Co Ltd Hot water circulating type space heating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149453A (en) * 1984-08-17 1986-03-11 Clarion Co Ltd Electrode wiring structure of composite semiconductor device
US10458821B2 (en) 2016-04-26 2019-10-29 Toyota Jidosha Kabushiki Kaisha Mounting structure for a peripheral information detection sensor used in a vehicle including an automatic driving system

Also Published As

Publication number Publication date
JPS5943826B2 (en) 1984-10-24

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