JPH08330469A - Wiring board for semiconductor device, and its manufacture - Google Patents

Wiring board for semiconductor device, and its manufacture

Info

Publication number
JPH08330469A
JPH08330469A JP13092295A JP13092295A JPH08330469A JP H08330469 A JPH08330469 A JP H08330469A JP 13092295 A JP13092295 A JP 13092295A JP 13092295 A JP13092295 A JP 13092295A JP H08330469 A JPH08330469 A JP H08330469A
Authority
JP
Japan
Prior art keywords
conductive
main surface
wiring board
semiconductor device
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13092295A
Other languages
Japanese (ja)
Inventor
Hiroshi Kikuchi
広 菊地
Toshihiko Sato
俊彦 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13092295A priority Critical patent/JPH08330469A/en
Publication of JPH08330469A publication Critical patent/JPH08330469A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a technique which can connect each electrode accurately to a corresponding conductive terminal, in case of drawing out a plurality of electrodes made at small pitches at a semiconductor chip. CONSTITUTION: A wiring board 1 is prepared in which conductive terminals 38 are made at the other main surface at pitches larger than the pitches of conductive terminals 3A made at one main surface. A semiconductor chip 12 is mounted, connecting the conductive terminals 38 at large pitches to the corresponding conductive terminals 15. Hereby, in case of drawing out a plurality of electrodes 14 made at small pitches at a semiconductor chip 12, they can be drawn out at enlarged pitches, so each electrode 14 can be connected accurately to corresponding conductive terminals 15.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置用配線基板
およびその製造方法に関し、特に、半導体チップの一主
面に微小ピッチで配置された複数の電極を、拡大したピ
ッチで外部に引き出したい場合に適用して有効な技術に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for a semiconductor device and a method of manufacturing the same, and more particularly to a plurality of electrodes arranged at a fine pitch on one main surface of a semiconductor chip to be drawn out at an enlarged pitch. It is related to effective technology when applied.

【0002】[0002]

【従来の技術】LSIで代表される最近の半導体装置
は、ますます多機能化の要求が高まってきており、これ
に伴いより一層高集積化が図られる傾向にある。従っ
て、半導体チップに形成される電極の数は飛躍的に増加
しつつある。
2. Description of the Related Art Recent semiconductor devices typified by LSIs are required to have more and more functions, and with this trend, higher integration tends to be achieved. Therefore, the number of electrodes formed on the semiconductor chip is increasing dramatically.

【0003】このように複数の電極を形成した半導体チ
ップを実装基板に実装する場合、半導体チップの全面に
多数のボール状の電極(以下、バンプと称する)を微小
ピッチで形成して、このバンプを実装基板に接続するよ
うにした、CCB(Controlled Colla
pse Bonding)が好んで採用されている。
When a semiconductor chip having a plurality of electrodes thus formed is mounted on a mounting substrate, a large number of ball-shaped electrodes (hereinafter referred to as bumps) are formed on the entire surface of the semiconductor chip at a fine pitch, and the bumps are formed. Of the CCB (Controlled Colla)
Pse Bonding) is preferred.

【0004】すなわち、半導体チップの一主面に微小ピ
ッチで形成された複数のバンプは、バンプに対応して絶
縁基板からなる実装基板に形成された複数の導電端子
(導電パターン)に接続されることにより、半導体チッ
プはフリップチップ法によって実装基板にフェースダウ
ンボンディグされる。
That is, a plurality of bumps formed at a minute pitch on one main surface of a semiconductor chip are connected to a plurality of conductive terminals (conductive patterns) formed on a mounting substrate made of an insulating substrate corresponding to the bumps. As a result, the semiconductor chip is face down bonded to the mounting substrate by the flip chip method.

【0005】このように高集積化された半導体チップに
微小ピッチで形成した複数のバンプを外部の回路である
実装基板に電気的に引き出す場合、実装基板としては、
配線が絶縁基板内に多層にわたって形成された多層実装
基板が使用されることが多い。この多層実装基板の材料
としては、次のような特長を備えたセラミックスが一般
に利用される。
When a plurality of bumps formed at a fine pitch on such a highly integrated semiconductor chip are electrically drawn out to a mounting substrate which is an external circuit, the mounting substrate is
A multilayer mounting substrate in which wiring is formed in multiple layers in an insulating substrate is often used. Ceramics having the following features are generally used as the material of the multilayer mounting board.

【0006】半導体チップと実装基板の熱膨張率を比
較的近似させることができるので、チップボンディング
においてバンプに加わる応力を減らすことができ、バン
プの剥がれを軽減することができる。
Since the thermal expansion coefficients of the semiconductor chip and the mounting substrate can be made relatively close to each other, the stress applied to the bump during chip bonding can be reduced and the peeling of the bump can be reduced.

【0007】ガラスエポキシなどに比べて製造公差の
小さい実装基板を製造できるので、バンプ接続用の導電
パターンを作り易い。
Since a mounting substrate having a smaller manufacturing tolerance than glass epoxy can be manufactured, it is easy to form a conductive pattern for bump connection.

【0008】その実装基板に薄膜配線をつくること
で、さらに精度の高いバンプ接続用の導電パターンを作
ることができる。
By forming a thin film wiring on the mounting substrate, a more accurate conductive pattern for bump connection can be formed.

【0009】多層配線を作り易いので、実装基板内で
信号線の引き回し、電源の分配などができる。
Since it is easy to form a multi-layer wiring, it is possible to lay out signal lines and distribute power supplies in the mounting board.

【0010】耐熱性、機密性、機械的強度などに優れ
た実装基板を製造できる。
It is possible to manufacture a mounting board having excellent heat resistance, airtightness and mechanical strength.

【0011】例えば日経BP社発行、「VLSIパッケ
ージング技術(上)」、1993年5月31日発行、P
54〜P61には、半導体チップを各種実装基板に支持
させるパッケージング技術に関して詳細に記載されてい
る。
For example, "VLSI Packaging Technology (above)" issued by Nikkei BP, May 31, 1993, P
54 to P61, a packaging technique for supporting a semiconductor chip on various mounting substrates is described in detail.

【0012】また、半導体チップを実装基板に実装する
に当たっては、予め、半導体チップの良品、不良品を検
査することが行われ、このため半導体チップはセラミッ
クスなどの検査用基板に仮付けされて、検査終了後に取
外される。そして、良品のみが実装基板にボンディング
されることになる。
In mounting the semiconductor chip on the mounting board, it is necessary to inspect whether the semiconductor chip is a good product or a defective product in advance. Therefore, the semiconductor chip is temporarily attached to an inspection substrate such as ceramics, It is removed after the inspection. Then, only good products are bonded to the mounting substrate.

【0013】さらに、半導体チップのバンプに直接に検
査用プローブを接触させて、検査を行う場合もある。し
かし、この場合は、多数のバンプが微細ピッチで半導体
チップの全面に配置されているために、各バンプに正確
に検査用プローブを接触させるのは困難である。
Further, the inspection may be carried out by directly contacting the inspection probe with the bump of the semiconductor chip. However, in this case, since a large number of bumps are arranged on the entire surface of the semiconductor chip with a fine pitch, it is difficult to accurately bring the inspection probe into contact with each bump.

【0014】[0014]

【発明が解決しようとする課題】前記のように半導体チ
ップを実装基板に実装するには、実装基板として優れた
条件を備えているセラミックスを利用することが多くな
っているが、このセラミックスは高価なので、コストア
ップが避けられないという問題がある。
As described above, in order to mount a semiconductor chip on a mounting board, ceramics having excellent conditions as a mounting board are often used, but this ceramic is expensive. Therefore, there is a problem that cost increase cannot be avoided.

【0015】また、一主面に微小ピッチで形成された複
数のバンプを、対応した導電端子に接続することによっ
て半導体チップを実装基板に実装するので、各バンプを
正確に対応した導電端子に接続するのが困難になる。こ
れは、半導体チップの検査を行うために検査用基板に仮
付けする場合も同様である。
Further, since the semiconductor chip is mounted on the mounting substrate by connecting a plurality of bumps formed on one main surface with a fine pitch to the corresponding conductive terminals, each bump is accurately connected to the corresponding conductive terminal. Hard to do. This is also the case when the semiconductor chip is temporarily attached to the inspection substrate for inspection.

【0016】本発明の目的は、半導体チップに微小ピッ
チで形成した複数の電極を外部に引き出す場合、コスト
ダウンを図ることが可能な技術を提供することにある。
It is an object of the present invention to provide a technique capable of reducing the cost when a plurality of electrodes formed on a semiconductor chip with a fine pitch are drawn to the outside.

【0017】本発明の他の目的は、半導体チップに微小
ピッチで形成した複数の電極を外部に引き出す場合、各
電極を正確に対応した導電端子に接続することが可能な
技術を提供することにある。
Another object of the present invention is to provide a technique capable of accurately connecting each electrode to a corresponding conductive terminal when a plurality of electrodes formed at a fine pitch on a semiconductor chip are drawn to the outside. is there.

【0018】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0019】[0019]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。
Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

【0020】(1)本発明の半導体装置用配線基板は、
一主面に所定のピッチで複数の電極が配置された半導体
チップを支持するための半導体装置用配線基板であっ
て、前記半導体チップの一主面に対応する一主面に前記
複数の電極の配置ピッチとほぼ等しいピッチで複数の導
電端子が形成されるとともに、前記一主面と反対側の他
主面に前記複数の導電端子と導通しかつ所定のピッチで
複数の導電端子が形成された絶縁基板からなる。絶縁基
板としては例えば弾力性を有する材料を用いる。
(1) The wiring board for a semiconductor device of the present invention comprises:
A wiring board for a semiconductor device for supporting a semiconductor chip in which a plurality of electrodes are arranged at a predetermined pitch on one main surface, wherein the plurality of electrodes are provided on one main surface corresponding to the one main surface of the semiconductor chip. A plurality of conductive terminals are formed at a pitch substantially equal to the arrangement pitch, and a plurality of conductive terminals are formed on the other main surface opposite to the one main surface so as to be electrically connected to the plurality of conductive terminals and at a predetermined pitch. It consists of an insulating substrate. As the insulating substrate, a material having elasticity is used, for example.

【0021】(2)本発明の半導体装置用配線基板の製
造方法は、互いに等しいピッチで複数の貫通孔が形成さ
れた一対のマスク板を前記貫通孔の位置が一致するよう
に重ねる工程と、前記一対のマスク板の各対応する貫通
孔に導電性ワイヤを挿通する工程と、前記一対のマスク
板を導電性ワイヤを緊張させたままで引き離す工程と、
前記一対のマスク板間の導電性ワイヤを結束する工程
と、少なくとも前記一対のマスク板間の導電性ワイヤを
絶縁体に埋設する工程と、前記導電性ワイヤを埋設した
絶縁体を導電性ワイヤを横切るように所定の幅で切断す
る工程とを含んでいる。
(2) In the method of manufacturing a wiring board for a semiconductor device of the present invention, a step of stacking a pair of mask plates in which a plurality of through holes are formed at equal pitches so that the positions of the through holes coincide with each other, A step of inserting a conductive wire into each corresponding through hole of the pair of mask plates; a step of separating the pair of mask plates while keeping the conductive wires taut.
A step of binding the conductive wires between the pair of mask plates, a step of embedding at least the conductive wires between the pair of mask plates in an insulator, and an insulator in which the conductive wires are embedded as a conductive wire. Cutting with a predetermined width so as to traverse.

【0022】(3)本発明の他の半導体装置用配線基板
の製造方法は、互いに異なるピッチで複数の貫通孔が形
成された一対のマスク板を平行に配置する工程と、前記
一対のマスク板の各対応する貫通孔に導電性ワイヤを挿
通する工程と、前記一対のマスク板を導電性ワイヤを緊
張させたままで少なくとも前記一対のマスク板間の導電
性ワイヤを絶縁体に埋設する工程と、前記導電性ワイヤ
を埋設した絶縁体を導電性ワイヤを横切るように所定の
幅で切断する工程とを含んでいる。
(3) In another method of manufacturing a wiring board for a semiconductor device of the present invention, a step of arranging a pair of mask plates in which a plurality of through holes are formed in parallel at different pitches in parallel, and the pair of mask plates. A step of inserting a conductive wire into each corresponding through hole, and a step of burying at least a conductive wire between the pair of mask plates in an insulator while keeping the conductive wire tensioned in the pair of mask plates; Cutting the insulator having the conductive wire embedded therein with a predetermined width so as to traverse the conductive wire.

【0023】[0023]

【作用】上述した(1)の手段によれば、本発明の半導
体装置用配線基板は、一主面に所定のピッチで複数の電
極が配置された半導体チップを支持するための半導体装
置用配線基板であって、前記半導体チップの一主面に対
応する一主面に前記複数の電極の配置ピッチとほぼ等し
いピッチで複数の導電端子が形成されるとともに、前記
一主面と反対側の他主面に前記複数の導電端子と導通し
かつ所定のピッチで複数の導電端子が形成された例えば
弾力性を有する絶縁基板からなるので、半導体チップに
微小ピッチで形成した複数の電極を外部に引き出す場
合、コストダウンを図ることが可能となり、また、各電
極を正確に対応した導電端子に接続することが可能とな
る。
According to the above-mentioned means (1), the semiconductor device wiring board of the present invention is a semiconductor device wiring for supporting a semiconductor chip in which a plurality of electrodes are arranged on one main surface at a predetermined pitch. In the substrate, a plurality of conductive terminals are formed on one main surface corresponding to one main surface of the semiconductor chip at a pitch substantially equal to the arrangement pitch of the plurality of electrodes, and another conductive terminal on the opposite side to the one main surface. Since it is composed of, for example, an elastic insulating substrate having a plurality of conductive terminals formed on the main surface and electrically connected to the plurality of conductive terminals at a predetermined pitch, a plurality of electrodes formed on the semiconductor chip with a fine pitch are drawn to the outside. In this case, the cost can be reduced and each electrode can be accurately connected to the corresponding conductive terminal.

【0024】上述した(2)の手段によれば、本発明の
半導体装置用配線基板の製造方法は、互いに等しいピッ
チで複数の貫通孔が形成された一対のマスク板を前記貫
通孔の位置が一致するように重ねる工程と、前記一対の
マスク板の各対応する貫通孔に導電性ワイヤを挿通する
工程と、前記一対のマスク板を導電性ワイヤを緊張させ
たままで引き離す工程と、前記一対のマスク板間の導電
性ワイヤを結束する工程と、少なくとも前記一対のマス
ク板間の導電性ワイヤを絶縁体に埋設する工程と、前記
導電性ワイヤを埋設した絶縁体を導電性ワイヤを横切る
ように所定の幅で切断する工程とを含んでいるので、半
導体チップに微小ピッチで形成した複数の電極を外部に
引き出す場合、コストダウンを図ることが可能となり、
また、各電極を正確に対応した導電端子に接続すること
が可能となる。
According to the above-mentioned means (2), in the method for manufacturing a wiring board for a semiconductor device of the present invention, a pair of mask plates having a plurality of through holes formed at equal pitches are used. A step of overlapping so as to match, a step of inserting a conductive wire into each corresponding through hole of the pair of mask plates, a step of separating the pair of mask plates while keeping the conductive wires tensioned, A step of binding the conductive wires between the mask plates, a step of embedding at least the conductive wires between the pair of mask plates in an insulator, and an insulator in which the conductive wires are embedded so as to traverse the conductive wires. Since it includes a step of cutting with a predetermined width, when pulling out a plurality of electrodes formed at a fine pitch on the semiconductor chip to the outside, it is possible to reduce the cost,
Moreover, it becomes possible to connect each electrode to the corresponding conductive terminal accurately.

【0025】上述した(3)の手段によれば、本発明の
他の半導体装置用配線基板の製造方法は、互いに異なる
ピッチで複数の貫通孔が形成された一対のマスク板を平
行に配置する工程と、前記一対のマスク板の各対応する
貫通孔に導電性ワイヤを挿通する工程と、前記一対のマ
スク板を導電性ワイヤを緊張させたままで少なくとも前
記一対のマスク板間の導電性ワイヤを絶縁体に埋設する
工程と、前記導電性ワイヤを埋設した絶縁体を導電性ワ
イヤを横切るように所定の幅で切断する工程とを含んで
いるので、半導体チップに微小ピッチで形成した複数の
電極を外部に引き出す場合、コストダウンを図ることが
可能となり、また、各電極を正確に対応した導電端子に
接続することが可能となる。
According to the above-described means (3), in another method of manufacturing a wiring board for a semiconductor device of the present invention, a pair of mask plates having a plurality of through holes formed at mutually different pitches are arranged in parallel. A step of inserting a conductive wire into each corresponding through hole of the pair of mask plates, and a conductive wire between at least the pair of mask plates with the conductive wire being tensioned in the pair of mask plates. Since the method includes a step of burying in the insulator and a step of cutting the insulator in which the conductive wire is embedded with a predetermined width so as to traverse the conductive wire, a plurality of electrodes formed at a fine pitch on the semiconductor chip. When it is drawn out, the cost can be reduced, and each electrode can be accurately connected to the corresponding conductive terminal.

【0026】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。
Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments.

【0027】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。
In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0028】[0028]

【実施例】【Example】

(実施例1)図1は本発明の実施例1による半導体装置
用配線基板を示す平面図で、図2は図1のA−A断面図
である。本実施例の半導体装置用配線基板1は、例えば
シリコーンゴムのような弾力性を有する絶縁基板2から
なり、その内部には例えばCu、Auのような複数の導
電層3が厚さ方向に対して傾斜して形成されていて、絶
縁基板2の一主面および他主面には各導電層3の導電端
子3Aおよび3Bが形成されている。あるいは、絶縁基
板2は各種樹脂やガラスエポキシのような比較的固い材
料を利用することもできる。これらシリコーンゴム、各
種樹脂、ガラスエポキシのような絶縁基板は、従来広く
利用されているセラミックスに比較してかなり安価であ
る。
(Embodiment 1) FIG. 1 is a plan view showing a wiring board for a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. The wiring board 1 for a semiconductor device of the present embodiment is composed of an insulating substrate 2 having elasticity such as silicone rubber, and a plurality of conductive layers 3 such as Cu and Au are provided inside the insulating substrate 2 in the thickness direction. Are formed so as to be inclined, and conductive terminals 3A and 3B of each conductive layer 3 are formed on one main surface and the other main surface of the insulating substrate 2. Alternatively, the insulating substrate 2 can be made of a relatively hard material such as various resins or glass epoxy. Insulating substrates such as these silicone rubbers, various resins, and glass epoxies are considerably cheaper than ceramics which have been widely used in the past.

【0029】絶縁基板2の一主面の導電端子3Aは後述
のように、この配線基板1によって支持されるべき半導
体チップに形成されている複数の電極の配置ピッチとほ
ぼ等しいピッチで形成されている。一方、絶縁基板2の
他主面の前記導電端子3Aと導通する導電端子3Bは、
導電端子3Aの配置ピッチよりも大きいピッチとなるよ
うに形成されている。これにより、半導体チップに微小
ピッチで形成されている複数の電極を外部に電気的に引
き出す場合、拡大したピッチで外部に引き出すことが可
能となる。
The conductive terminals 3A on one main surface of the insulating substrate 2 are formed at a pitch substantially equal to the arrangement pitch of a plurality of electrodes formed on the semiconductor chip to be supported by the wiring substrate 1, as described later. There is. On the other hand, the conductive terminal 3B which is electrically connected to the conductive terminal 3A on the other main surface of the insulating substrate 2 is
It is formed to have a pitch larger than the arrangement pitch of the conductive terminals 3A. Accordingly, when a plurality of electrodes formed on the semiconductor chip at a fine pitch are electrically pulled out, it is possible to pull out the electrodes at an enlarged pitch.

【0030】絶縁基板2の一主面および他主面に形成さ
れる各導電層3の導電端子3Aおよび3Bは、Ni、A
uのようなメタライズ層によって構成されている。この
メタライズ層は後述のように、半導体チップの電極であ
るバンプが濡れ易い材料が選ばれる。
The conductive terminals 3A and 3B of the conductive layers 3 formed on the one main surface and the other main surface of the insulating substrate 2 are made of Ni, A, respectively.
It is composed of a metallized layer such as u. As the metallized layer, as will be described later, a material is selected so that the bumps, which are the electrodes of the semiconductor chip, easily wet.

【0031】次に、図3乃至図7を参照して本実施例の
半導体装置用配線基板の製造方法を工程順に説明する。
Next, with reference to FIGS. 3 to 7, a method of manufacturing the semiconductor device wiring board of this embodiment will be described in the order of steps.

【0032】まず、図3に示すように、例えば金属、ガ
ラスのような材料からなる一対のマスク板5を用意し、
各マスク板5には予め互いに等しいピッチで複数の貫通
孔6を形成しておくものとする。
First, as shown in FIG. 3, a pair of mask plates 5 made of a material such as metal or glass is prepared.
It is assumed that a plurality of through holes 6 are formed in each mask plate 5 in advance at the same pitch.

【0033】次に、図4に示すように、一対のマスク板
5を対応する各貫通孔6の位置が一致するように重ねた
後、各貫通孔6に例えばCu、Auのような複数の導電
性ワイヤ7を挿通する。この導電性ワイヤ7は後程、前
記のような導電層3として利用される。
Next, as shown in FIG. 4, a pair of mask plates 5 are stacked so that the positions of the corresponding through holes 6 are aligned with each other, and then a plurality of holes such as Cu and Au are placed in each through hole 6. The conductive wire 7 is inserted. This conductive wire 7 will be used later as the conductive layer 3 as described above.

【0034】続いて、図5に示すように、各貫通孔6に
挿通した各導電性ワイヤ7を緊張させたままで、一対の
マスク板5を平行に引き離して、両者間に空間領域8を
形成する。各マスク板5の各貫通孔6が等しいピッチで
形成されていることにより、各導電性ワイヤ7は平行に
張られる。
Subsequently, as shown in FIG. 5, the pair of mask plates 5 are separated in parallel while the conductive wires 7 inserted into the through holes 6 are kept in tension to form a space region 8 therebetween. To do. Since the through holes 6 of the mask plate 5 are formed at the same pitch, the conductive wires 7 are stretched in parallel.

【0035】次に、図6に示すように、空間領域8の複
数の導電性ワイヤ7を周囲から別のワイヤ9により縛っ
て、一点に結束させる。これにより、各導電性ワイヤ7
は一点から周囲に放射状に張られた状態となる。続い
て、一対のマスク板5、導電性ワイヤ7の周囲から、例
えばエポキシ樹脂のような絶縁体10を流動状態で供給
して硬化させることにより、各マスク板5および導電性
ワイヤ7を絶縁体10内に埋設する。
Next, as shown in FIG. 6, a plurality of conductive wires 7 in the space region 8 are bound from the periphery by another wire 9 to be bound at one point. Thereby, each conductive wire 7
Is in a state of being stretched radially from one point to the surroundings. Subsequently, the mask plate 5 and the conductive wire 7 are insulated from each other by supplying an insulator 10 such as an epoxy resin in a fluid state from the periphery of the pair of mask plates 5 and the conductive wire 7 to cure the mask plate 5 and the conductive wire 7. It is buried in 10.

【0036】次に、図6で破線で示すように、一対のマ
スク板5間の絶縁体10を一対のマスク板5にほぼ平行
で各導電性ワイヤ7を横切るように所定の幅cで切断す
ることにより、図7に示すように、所定の厚さcを有す
る絶縁基板2が得られる。この絶縁基板2内には複数の
導電層3が配線されて、絶縁基板2の一主面および他主
面には各々端部が露出されている。
Next, as shown by the broken line in FIG. 6, the insulator 10 between the pair of mask plates 5 is cut with a predetermined width c so as to be substantially parallel to the pair of mask plates 5 and across each conductive wire 7. By doing so, as shown in FIG. 7, the insulating substrate 2 having a predetermined thickness c is obtained. A plurality of conductive layers 3 are wired in the insulating substrate 2, and end portions are exposed on one main surface and the other main surface of the insulating substrate 2.

【0037】続いて、導電層3の各端部に対して例えば
Ni、Auのようなメタライズ層をめっきなどによって
形成することにより、各導電端子3A、3Bが形成され
て、図1および図2に示すような構造の配線基板1が得
られる。
Subsequently, a metallized layer such as Ni or Au is formed on each end of the conductive layer 3 by plating or the like to form the conductive terminals 3A and 3B. A wiring board 1 having a structure as shown in is obtained.

【0038】このようにして形成された配線基板1にお
いては、図5および図7に示したように、一対のマスク
板5の間隔aおよび最側端の導電性ワイヤ7の間隔bを
調整することにより、あるいは厚さcを調整することに
より、一主面における導電端子3Aのピッチと、他主面
における導電端子3Bのピッチの比率、いわゆる収束率
を変えることができる。
In the wiring board 1 thus formed, as shown in FIGS. 5 and 7, the distance a between the pair of mask plates 5 and the distance b between the conductive wires 7 at the outermost ends are adjusted. Therefore, or by adjusting the thickness c, the ratio of the pitch of the conductive terminals 3A on one main surface to the pitch of the conductive terminals 3B on the other main surface, that is, the so-called convergence rate can be changed.

【0039】次に、図8乃至図11を参照して本実施例
の配線基板の他の製造方法を工程順に説明する。
Next, another method of manufacturing the wiring board of this embodiment will be described in the order of steps with reference to FIGS.

【0040】まず、図8に示すように、例えば金属、ガ
ラスのような材料からなる一対のマスク板5を用意し
て、空間領域9を介して平行に配置する。各マスク板5
には予め互いに異なるピッチで複数の貫通孔6を形成し
ておくものとする。
First, as shown in FIG. 8, a pair of mask plates 5 made of a material such as metal or glass is prepared and arranged in parallel with a space region 9 interposed therebetween. Each mask board 5
In this case, a plurality of through holes 6 are formed in advance at mutually different pitches.

【0041】次に、図9に示すように、一対のマスク板
5の対応する各貫通孔6に例えばCu、Auのような複
数の導電性ワイヤ7を挿通する。各マスク板5の各貫通
孔6が異なるピッチで形成されていることにより、各導
電性ワイヤ7は傾斜して張られる。この導電性ワイヤ7
は後程、前記のような導電層3として利用される。
Next, as shown in FIG. 9, a plurality of conductive wires 7 such as Cu and Au are inserted into the corresponding through holes 6 of the pair of mask plates 5. Since the through holes 6 of each mask plate 5 are formed at different pitches, each conductive wire 7 is stretched and stretched. This conductive wire 7
Will be used later as the conductive layer 3 as described above.

【0042】続いて、図10に示すように、各貫通孔6
に挿通した各導電性ワイヤ7を緊張させたままで、一対
のマスク板5、導電性ワイヤ7の周囲から、例えばエポ
キシ樹脂のような絶縁体10を流動状態で供給して硬化
させることにより、各マスク板5および導電性ワイヤ7
を絶縁体10内に埋設する。
Then, as shown in FIG. 10, each through hole 6
While the conductive wires 7 inserted into the elastic member 10 are kept taut, an insulating material 10 such as an epoxy resin is supplied in a fluid state from the periphery of the pair of mask plates 5 and the conductive wires 7 to cure the insulating wires 10. Mask plate 5 and conductive wire 7
Are embedded in the insulator 10.

【0043】次に、図10で破線で示すように、一対の
マスク板5間の絶縁体10を一対のマスク板5にほぼ平
行で各導電性ワイヤ7を横切るように所定の幅cで切断
することにより、図11に示すように、所定の厚さcを
有する絶縁基板2が得られる。この絶縁基板2内には複
数の導電層3が配線されて、絶縁基板2の一主面および
他主面には各々端部が露出されている。
Next, as shown by a broken line in FIG. 10, the insulator 10 between the pair of mask plates 5 is cut with a predetermined width c so as to cross the conductive wires 7 substantially in parallel with the pair of mask plates 5. By doing so, as shown in FIG. 11, an insulating substrate 2 having a predetermined thickness c is obtained. A plurality of conductive layers 3 are wired in the insulating substrate 2, and end portions are exposed on one main surface and the other main surface of the insulating substrate 2.

【0044】続いて、導電層3の各端部に対して例えば
Ni、Auのようなメタライズ層をめっきなどによって
形成することにより、各導電端子3A、3Bが形成され
て、図1および図2に示すような構造の配線基板1が得
られる。
Then, a metallized layer such as Ni or Au is formed on each end of the conductive layer 3 by plating or the like to form the conductive terminals 3A and 3B. A wiring board 1 having a structure as shown in is obtained.

【0045】このようにして形成された配線基板1にお
いては、図8に示したように、一対のマスク板5の間隔
aあるいは厚さcを調整することにより、収束率を変え
ることができる。
In the wiring board 1 thus formed, as shown in FIG. 8, the convergence rate can be changed by adjusting the distance a or the thickness c between the pair of mask plates 5.

【0046】図12は本実施例による配線基板1の使用
例を示す断面図である。配線基板1は、LSIからなる
半導体チップ12と実装基板13との間に配置される。
半導体チップ12の一主面には、例えばはんだ(Pb−
Sn合金)のようなバンプからなる複数の電極14が微
小ピッチで配置されている。一方、実装基板13の一主
面には、複数の導電端子15がその電極14の配置ピッ
チよりも大きいピッチで配置されている。この導電端子
15は配線基板1の導電端子3A、3Bと同様にNi、
Auのようなメタライズ層で構成されている。
FIG. 12 is a sectional view showing an example of use of the wiring board 1 according to this embodiment. The wiring board 1 is arranged between a semiconductor chip 12 made of an LSI and a mounting board 13.
On one main surface of the semiconductor chip 12, for example, solder (Pb-
A plurality of electrodes 14 made of bumps such as Sn alloy) are arranged at a fine pitch. On the other hand, a plurality of conductive terminals 15 are arranged on one main surface of the mounting substrate 13 at a pitch larger than the pitch of the electrodes 14. The conductive terminal 15 is made of Ni, like the conductive terminals 3A and 3B of the wiring board 1.
It is composed of a metallized layer such as Au.

【0047】配線基板1の一主面の半導体チップ12の
複数の電極14の配置ピッチとほぼ等しいピッチの複数
の導電端子3Aには、各々対応する半導体チップ12の
電極14が接続されている。一方、配線基板1の他主面
のその電極14の配置ピッチよりも大きいピッチである
複数の導電端子3Bには、各々対応する実装基板13の
導電端子15がはんだ18により接続されている。
The electrodes 14 of the corresponding semiconductor chip 12 are connected to the plurality of conductive terminals 3A having a pitch substantially equal to the arrangement pitch of the plurality of electrodes 14 of the semiconductor chip 12 on the one main surface of the wiring board 1. On the other hand, the conductive terminals 15 of the mounting board 13 are connected to the plurality of conductive terminals 3B having a pitch larger than the arrangement pitch of the electrodes 14 on the other main surface of the wiring board 1 by the solder 18.

【0048】一例として、約10mm×10mmの面積
の半導体チップ12の一主面には、直径約0.15〜
0.2mmの複数の電極14が約0.3mmのピッチで
形成されており、厚さ約1〜2mmの配線基板1の内部
には直径約0.05〜0.15mmの複数の導電層3が
形成されている。配線基板1の一主面の複数の導電端子
3Aは約0.3mmのピッチで形成され、他主面の複数
の導電端子3Bはその値0.3mmよりも大きく形成さ
れ、この値は収束率によって決定される。
As an example, one main surface of the semiconductor chip 12 having an area of about 10 mm × 10 mm has a diameter of about 0.15.
A plurality of 0.2 mm electrodes 14 are formed at a pitch of about 0.3 mm, and a plurality of conductive layers 3 having a diameter of about 0.05 to 0.15 mm are provided inside the wiring board 1 having a thickness of about 1 to 2 mm. Are formed. The plurality of conductive terminals 3A on one main surface of the wiring board 1 are formed with a pitch of about 0.3 mm, and the plurality of conductive terminals 3B on the other main surface are formed with a value larger than 0.3 mm, which is a convergence rate. Determined by

【0049】図13は本実施例による配線基板1の他の
使用例を示す断面図である。配線基板1は、LSIから
なる半導体チップ12と検査用基板16との間に配置さ
れる。半導体チップ12の一主面には、例えばはんだ
(Pb−Sn合金)のようなバンプからなる複数の電極
14が微小ピッチで配置されているとともに、検査用基
板16の一主面には、複数の導電端子17がその電極1
4の配置ピッチよりも大きいピッチで配置されている。
この導電端子17は配線基板1の導電端子3A、3Bと
同様にNi、Auのようなメタライズ層で構成されてい
る。
FIG. 13 is a sectional view showing another example of use of the wiring board 1 according to this embodiment. The wiring board 1 is arranged between the semiconductor chip 12 made of LSI and the inspection board 16. A plurality of electrodes 14 made of bumps such as solder (Pb—Sn alloy) are arranged at a fine pitch on one main surface of the semiconductor chip 12, and a plurality of electrodes 14 are provided on one main surface of the inspection substrate 16. The conductive terminal 17 of the electrode 1
They are arranged at a pitch larger than the arrangement pitch of No. 4.
Like the conductive terminals 3A and 3B of the wiring board 1, the conductive terminal 17 is composed of a metallized layer such as Ni or Au.

【0050】配線基板1の一主面の半導体チップ12の
複数の電極14の配置ピッチとほぼ等しいピッチの複数
の導電端子3Aには、各々対応する半導体チップ12の
電極14が仮付けされる。一方、配線基板1の他主面の
その電極14の配置ピッチよりも大きいピッチである複
数の導電端子3Bには、各々対応する実装基板16の導
電端子17がはんだ18により仮付けされる。
The electrodes 14 of the corresponding semiconductor chip 12 are temporarily attached to the plurality of conductive terminals 3A having a pitch substantially equal to the arrangement pitch of the plurality of electrodes 14 of the semiconductor chip 12 on one main surface of the wiring board 1. On the other hand, the conductive terminals 17 of the corresponding mounting board 16 are temporarily attached to the plurality of conductive terminals 3B having a pitch larger than the arrangement pitch of the electrodes 14 on the other main surface of the wiring board 1 by the solder 18.

【0051】検査用基板16の導電端子17と導通する
測定端子(図示せず)には、検査装置が接続されて、半
導体チップ12の良品、不良品の検査が行われる。検査
終了後、配線基板1は半導体チップ12および検査用基
板16との仮付け部から取外される。そして、半導体チ
ップ12は良品のみが、図12に示したように実装基板
13に実装される。
An inspection device is connected to a measurement terminal (not shown) that is electrically connected to the conductive terminal 17 of the inspection board 16 to inspect the semiconductor chip 12 for a good product and a defective product. After the inspection is completed, the wiring board 1 is removed from the temporary attachment portion with the semiconductor chip 12 and the inspection board 16. Then, only the good semiconductor chips 12 are mounted on the mounting substrate 13 as shown in FIG.

【0052】このような本実施例によれば次のような効
果が得られる。
According to this embodiment, the following effects can be obtained.

【0053】(1)高価なセラミックスを利用すること
なく、安価な材料で配線基板1を構成できるので、半導
体チップ12に微小ピッチで形成した複数の電極14を
外部に引き出す場合、コストダウンを図ることが可能と
なる。
(1) Since the wiring board 1 can be formed of an inexpensive material without using expensive ceramics, the cost can be reduced when the plurality of electrodes 14 formed on the semiconductor chip 12 at a fine pitch are drawn to the outside. It becomes possible.

【0054】(2)一主面に形成する導電端子3Aのピ
ッチよりも大きいピッチで導電端子3Bを他主面に形成
した配線基板1を用意して、この大きなピッチの導電端
子3Bを実装基板13の対応した導電端子15に接続し
て半導体チップ12を実装するので、半導体チップ12
に微小ピッチで形成した複数の電極14を外部に引き出
す場合、拡大したピッチで引き出せるため、各電極14
を正確に対応した導電端子15に接続することが可能と
なる。
(2) A wiring board 1 having conductive terminals 3B formed on the other main surface at a pitch larger than the pitch of the conductive terminals 3A formed on one main surface is prepared, and the conductive terminals 3B having this large pitch are mounted on the mounting board. The semiconductor chip 12 is mounted by connecting to the corresponding conductive terminals 15 of the semiconductor chip 12.
When a plurality of electrodes 14 formed with a fine pitch are drawn to the outside, each electrode 14 can be drawn at an enlarged pitch.
Can be accurately connected to the corresponding conductive terminal 15.

【0055】(3)弾力性を有する材料で配線基板1を
構成できるので、チップボンディングにおいてバンプの
ような電極14に加わる応力を減らすことができる。
(3) Since the wiring board 1 can be made of a material having elasticity, stress applied to the electrodes 14 such as bumps in chip bonding can be reduced.

【0056】(4)一主面に形成する導電端子3Aのピ
ッチよりも大きいピッチで導電端子3Bを他主面に形成
した配線基板1を用意して、この大きなピッチの導電端
子3Bを検査用基板16の対応した導電端子17に仮付
けして半導体チップ12を検査するので、複数の電極1
4を外部に拡大したピッチで引き出せるため、正確な検
査を容易に行うことが可能となる。
(4) A wiring board 1 having conductive terminals 3B formed on the other main surface at a pitch larger than the pitch of the conductive terminals 3A formed on one main surface is prepared, and the conductive terminals 3B having this large pitch are used for inspection. Since the semiconductor chip 12 is inspected by temporarily attaching it to the corresponding conductive terminals 17 of the substrate 16, the plurality of electrodes 1
Since 4 can be pulled out to the outside at a pitch enlarged, accurate inspection can be easily performed.

【0057】(5)特別な工程を経ることなく、簡単な
工程で、微小ピッチの電極14を外部に拡大して取り出
せる配線基板1を製造することができる。
(5) It is possible to manufacture the wiring board 1 in which the electrodes 14 having a fine pitch can be expanded to the outside and taken out by a simple process without any special process.

【0058】(実施例2)図14は本発明の実施例2に
よる半導体装置用配線基板を示す断面図で、実施例1の
配線基板1において、特に他主面の導電端子3Bを短リ
ード19の形に形成した例を示すものである。
(Embodiment 2) FIG. 14 is a cross-sectional view showing a semiconductor device wiring board according to a second embodiment of the present invention. In the wiring board 1 of the first embodiment, in particular, the conductive terminals 3B on the other main surface are connected to the short lead 19. It shows an example formed in the shape of.

【0059】このような実施例2によっても、一主面に
形成する導電端子3Aのピッチよりも大きいピッチで導
電端子3Bを他主面に形成しているので、実施例1と同
様な効果を得ることができる。また、これに加えて、他
主面の導電端子3Bを短リード19の形に形成したこと
により、実装基板13あるいは検査用基板16の対応し
た導電端子に接続する場合、はんだの広がりを抑えるこ
とができるため、比較的複雑なパターンの導電端子に対
しても正確な接続が可能となる効果を得ることができ
る。
According to the second embodiment as well, since the conductive terminals 3B are formed on the other main surface at a pitch larger than the pitch of the conductive terminals 3A formed on the one main surface, the same effect as that of the first embodiment is obtained. Obtainable. In addition to this, by forming the conductive terminal 3B on the other main surface in the form of the short lead 19, when connecting to the corresponding conductive terminal of the mounting substrate 13 or the inspection substrate 16, the spread of solder is suppressed. Therefore, it is possible to obtain an effect that accurate connection can be made even to a conductive terminal having a relatively complicated pattern.

【0060】(実施例3)図15は本発明の実施例3に
よる半導体装置用配線基板を示す断面図で、一主面の導
電端子3Aのピッチと他主面の導電端子3Bのピッチを
ほぼ等しく形成して、他主面の導電端子3Bのみを周囲
方向に広げて形成した配線基板1を示すものである。
(Embodiment 3) FIG. 15 is a sectional view showing a wiring board for a semiconductor device according to Embodiment 3 of the present invention. The pitch of the conductive terminals 3A on one main surface and the pitch of the conductive terminals 3B on the other main surface are almost the same. The wiring board 1 is formed in the same manner and is formed by expanding only the conductive terminals 3B on the other main surface in the circumferential direction.

【0061】このような実施例3によっても、配線基板
1の他主面の導電端子3Bが周囲方向に広げて形成して
あるので、実装基板13あるいは検査用基板16の対応
した導電端子に接続する場合、接続が容易になるため、
実施例1に準じた効果を得ることができる。
Also in the third embodiment, since the conductive terminals 3B on the other main surface of the wiring board 1 are formed so as to be widened in the peripheral direction, they are connected to the corresponding conductive terminals of the mounting board 13 or the inspection board 16. If you do, it will be easier to connect,
The effect according to Example 1 can be obtained.

【0062】(実施例4)図16は本発明の実施例4に
よる半導体装置用配線基板を示す断面図で、必要に応じ
て一主面あるいは他主面の導電端子3A、3Bの隣接し
たもの同士を短絡するように形成した配線基板1を示す
ものである。
(Embodiment 4) FIG. 16 is a sectional view showing a wiring board for a semiconductor device according to Embodiment 4 of the present invention, in which conductive terminals 3A, 3B on one main surface or the other main surface are adjacent to each other as required. 1 shows a wiring board 1 formed so as to short-circuit each other.

【0063】このような実施例4によっても、必要に応
じて配線基板1の一主面あるいは他主面の導電端子3
A、3Bの隣接したもの同士を短絡するようにしてある
ので、実装基板13あるいは検査用基板16の対応した
導電端子に接続する場合、比較的複雑なパターンの導電
端子は迂回することができるため、接続が容易になるの
で、実施例1に準じた効果を得ることができる。
Also according to the fourth embodiment as described above, the conductive terminals 3 on one main surface or the other main surface of the wiring board 1 are used as required.
Since adjacent ones of A and 3B are short-circuited, when connecting to the corresponding conductive terminals of the mounting board 13 or the inspection board 16, the conductive terminals of a relatively complicated pattern can be bypassed. Since the connection is easy, the effect according to the first embodiment can be obtained.

【0064】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。
As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【0065】例えば、前記実施例では配線基板の材料と
しては特定のものに例をあげて説明したが、同等の機能
を有するものであれば、それに限らず他の材料を利用す
るようにしても良い。
For example, in the above-mentioned embodiment, the material of the wiring board has been described as an example, but it is not limited to this as long as it has an equivalent function, and other materials may be used. good.

【0066】また、配線基板に接続すべき半導体チップ
としては、バンプ電極を有する例で説明したが、これに
限らず微小ピッチで電極が形成されている半導体チップ
であれば、同様に適用することができる。
The semiconductor chip to be connected to the wiring board has been described with an example having bump electrodes. However, the present invention is not limited to this, and any semiconductor chip in which electrodes are formed at a fine pitch can be similarly applied. You can

【0067】さらに、実施例中で配線基板に形成する導
電層の数は一例を示したものであり、同様にして、実施
例中で示した構成部分の寸法は一例を示したものであ
り、これらは目的、用途等に応じて任意に選択すること
ができる。
Furthermore, the number of conductive layers formed on the wiring board in the examples is an example, and similarly, the dimensions of the constituent portions shown in the examples are examples. These can be arbitrarily selected according to the purpose, use, etc.

【0068】なお、図2に示した実施例1による半導体
装置用配線基板は、図17に示したように導電端子3
A、3Bを省略するようにしても良い。
The semiconductor device wiring board according to the first embodiment shown in FIG. 2 has the conductive terminals 3 as shown in FIG.
A and 3B may be omitted.

【0069】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である半導体
集積回路装置の技術に適用した場合について説明した
が、それに限定されるものではない。本発明は、少なく
とも半導体チップの一主面に微小ピッチで配置された複
数の電極を、拡大したピッチで外部に引き出す条件のも
のには適用できる。
In the above description, the case where the invention made by the present inventor is mainly applied to the technology of the semiconductor integrated circuit device which is the background field of application has been described, but the invention is not limited thereto. The present invention can be applied to at least a plurality of electrodes arranged at a minute pitch on one main surface of a semiconductor chip to the outside at an enlarged pitch.

【0070】[0070]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0071】(1)高価なセラミックスを利用すること
なく、安価な材料で配線基板を構成できるので、半導体
チップに微小ピッチで形成した複数の電極を外部に引き
出す場合、コストダウンを図ることが可能となる。
(1) Since the wiring board can be made of an inexpensive material without using expensive ceramics, it is possible to reduce the cost when a plurality of electrodes formed on the semiconductor chip with a fine pitch are drawn out. Becomes

【0072】(2)一主面に形成する導電端子のピッチ
よりも大きいピッチで導電端子を他主面に形成した配線
基板を用意して、この大きなピッチの導電端子を実装基
板の対応した導電端子に接続して半導体チップを実装す
るので、半導体チップに微小ピッチで形成した複数の電
極を外部に引き出す場合、拡大したピッチで引き出せる
ため、各電極を正確に対応した導電端子に接続すること
が可能となる。
(2) A wiring board having conductive terminals formed on the other main surface at a pitch larger than the pitch of the conductive terminals formed on one main surface is prepared, and the conductive terminals having the large pitch are used as the corresponding conductive materials on the mounting board. Since the semiconductor chip is mounted by connecting to the terminals, when drawing out multiple electrodes formed on the semiconductor chip with a fine pitch to the outside, it is possible to draw out at an enlarged pitch, so each electrode can be connected to the corresponding conductive terminal accurately. It will be possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1による半導体装置用配線基板
を示す平面図である。
FIG. 1 is a plan view showing a wiring board for a semiconductor device according to a first embodiment of the present invention.

【図2】図1のA−A断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】本発明の実施例1による半導体装置用配線基板
の製造方法の一工程を示す斜視図である。
FIG. 3 is a perspective view showing a step of the method of manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図4】本発明の実施例1による半導体装置用配線基板
の製造方法の他の工程を示す断面図である。
FIG. 4 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図5】本発明の実施例1による半導体装置用配線基板
の製造方法のその他の工程を示す断面図である。
FIG. 5 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図6】本発明の実施例1による半導体装置用配線基板
の製造方法のその他の工程を示す断面図である。
FIG. 6 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図7】本発明の実施例1による半導体装置用配線基板
の製造方法のその他の工程を示す断面図である。
FIG. 7 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図8】本発明の実施例1による半導体装置用配線基板
の他の製造方法の一工程を示す断面図である。
FIG. 8 is a cross-sectional view showing a step of another method of manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図9】本発明の実施例1による半導体装置用配線基板
の他の製造方法の他の工程を示す断面図である。
FIG. 9 is a cross-sectional view showing another step of the other method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図10】本発明の実施例1による半導体装置用配線基
板の他の製造方法のその他の工程を示す断面図である。
FIG. 10 is a cross-sectional view showing another step of the other method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図11】本発明の実施例1による半導体装置用配線基
板の他の製造方法のその他の工程を示す断面図である。
FIG. 11 is a cross-sectional view showing another step of the other method for manufacturing the semiconductor device wiring board according to the first embodiment of the present invention.

【図12】本発明の実施例1による半導体装置用配線基
板の使用例を示す断面図である。
FIG. 12 is a cross-sectional view showing an example of use of the semiconductor device wiring board according to the first embodiment of the present invention.

【図13】本発明の実施例1による半導体装置用配線基
板の他の使用例を示す断面図である。
FIG. 13 is a cross-sectional view showing another usage example of the semiconductor device wiring board according to the first embodiment of the present invention.

【図14】本発明の実施例2による半導体装置用配線基
板を示す断面図である。
FIG. 14 is a sectional view showing a wiring board for a semiconductor device according to a second embodiment of the present invention.

【図15】本発明の実施例3による半導体装置用配線基
板を示す断面図である。
FIG. 15 is a sectional view showing a wiring board for a semiconductor device according to a third embodiment of the present invention.

【図16】本発明の実施例4による半導体装置用配線基
板を示す断面図である。
FIG. 16 is a sectional view showing a semiconductor device wiring board according to a fourth embodiment of the present invention.

【図17】本発明の実施例1による半導体装置用配線基
板の変形例を示す断面図である。
FIG. 17 is a cross-sectional view showing a modified example of the semiconductor device wiring board according to the first embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体装置用配線基板、2…絶縁基板、3…導電
層、3A…一主面の導電端子、3B…他主面の導電端
子、5…マスク板、6…貫通孔、7…導電性ワイヤ、8
…空間領域、9…別のワイヤ、10…絶縁体、12…半
導体チップ、13…実装基板、14…半導体チップの電
極、15…実装基板の導電端子、16…検査用基板、1
7…検査用基板の端子、18…はんだ、19…短リー
ド。
DESCRIPTION OF SYMBOLS 1 ... Wiring board for semiconductor devices, 2 ... Insulating board, 3 ... Conductive layer, 3A ... Conductive terminal on one main surface, 3B ... Conductive terminal on other main surface, 5 ... Mask plate, 6 ... Through hole, 7 ... Conductivity Wire, 8
... space area, 9 ... another wire, 10 ... insulator, 12 ... semiconductor chip, 13 ... mounting board, 14 ... semiconductor chip electrode, 15 ... mounting board conductive terminal, 16 ... inspection board, 1
7 ... Terminal of inspection board, 18 ... Solder, 19 ... Short lead.

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 一主面に所定のピッチで複数の電極が配
置された半導体チップを支持するための半導体装置用配
線基板であって、前記半導体チップの一主面に対応する
一主面に前記複数の電極の配置ピッチとほぼ等しいピッ
チで複数の導電端子が形成されるとともに、前記一主面
と反対側の他主面に前記複数の導電端子と導通しかつ所
定のピッチで複数の導電端子が形成された絶縁基板から
なることを特徴とする半導体装置用配線基板。
1. A wiring board for a semiconductor device for supporting a semiconductor chip in which a plurality of electrodes are arranged at a predetermined pitch on one main surface, the one main surface corresponding to the one main surface of the semiconductor chip. A plurality of conductive terminals are formed at a pitch substantially equal to the arrangement pitch of the plurality of electrodes, and a plurality of conductive terminals are formed on the other main surface on the opposite side of the one main surface to the plurality of conductive terminals and at a predetermined pitch. A wiring board for a semiconductor device, comprising an insulating substrate on which terminals are formed.
【請求項2】 前記絶縁基板は、弾力性を有する材料か
らなることを特徴とする請求項1に記載の半導体装置用
配線基板。
2. The wiring board for a semiconductor device according to claim 1, wherein the insulating substrate is made of a material having elasticity.
【請求項3】 前記所定のピッチは、前記複数の電極の
配置ピッチよりも大きいピッチであることを特徴とする
請求項1または2に記載の半導体装置用配線基板。
3. The wiring board for a semiconductor device according to claim 1, wherein the predetermined pitch is larger than an arrangement pitch of the plurality of electrodes.
【請求項4】 前記一主面に形成された導電端子と前記
他主面に形成された導電端子は、絶縁基板の内部に形成
された導電層を通じて導通していることを特徴とする請
求項1乃至3のいずれか1項に記載の半導体装置用配線
基板。
4. The conductive terminal formed on the one main surface and the conductive terminal formed on the other main surface are electrically connected to each other through a conductive layer formed inside an insulating substrate. 4. The wiring board for a semiconductor device according to any one of 1 to 3.
【請求項5】 前記一主面の複数の導電端子が半導体チ
ップの対応した複数の電極に接続されるとともに、前記
他主面の複数の導電端子が実装基板の対応した導電端子
に接続されることを特徴とする請求項1乃至4のいずれ
か1項に記載の半導体装置用配線基板。
5. A plurality of conductive terminals on the one main surface are connected to corresponding electrodes on a semiconductor chip, and a plurality of conductive terminals on the other main surface are connected to corresponding conductive terminals on a mounting board. The wiring board for a semiconductor device according to claim 1, wherein the wiring board is for a semiconductor device.
【請求項6】 前記一主面の複数の導電端子が半導体チ
ップの対応した複数の電極に仮付けされるとともに、前
記他主面の複数の導電端子が検査用基板の対応した導電
端子に仮付けされることを特徴とする請求項1乃至4の
いずれか1項に記載の半導体装置用配線基板。
6. A plurality of conductive terminals on the one main surface are temporarily attached to a plurality of corresponding electrodes of a semiconductor chip, and a plurality of conductive terminals on the other main surface are temporarily attached to a corresponding conductive terminal of an inspection board. The wiring board for a semiconductor device according to claim 1, which is attached.
【請求項7】 互いに等しいピッチで複数の貫通孔が形
成された一対のマスク板を前記貫通孔の位置が一致する
ように重ねる工程と、前記一対のマスク板の各対応する
貫通孔に導電性ワイヤを挿通する工程と、前記一対のマ
スク板を導電性ワイヤを緊張させたままで引き離す工程
と、前記一対のマスク板間の導電性ワイヤを結束する工
程と、少なくとも前記一対のマスク板間の導電性ワイヤ
を絶縁体に埋設する工程と、前記導電性ワイヤを埋設し
た絶縁体を導電性ワイヤを横切るように所定の幅で切断
する工程とを含むことを特徴とする半導体装置用配線基
板の製造方法。
7. A step of stacking a pair of mask plates in which a plurality of through holes are formed at equal pitches so that the positions of the through holes are aligned with each other, and the corresponding through holes of the pair of mask plates are electrically conductive. A step of inserting a wire; a step of separating the pair of mask plates while keeping the conductive wires taut; a step of binding the conductive wires between the pair of mask plates; and a conduction between at least the pair of mask plates. Of a conductive wire embedded in an insulator, and a step of cutting the insulator in which the conductive wire is embedded with a predetermined width so as to cross the conductive wire. Method.
【請求項8】 互いに異なるピッチで複数の貫通孔が形
成された一対のマスク板を平行に配置する工程と、前記
一対のマスク板の各対応する貫通孔に導電性ワイヤを挿
通する工程と、前記一対のマスク板を導電性ワイヤを緊
張させたままで少なくとも前記一対のマスク板間の導電
性ワイヤを絶縁体に埋設する工程と、前記導電性ワイヤ
を埋設した絶縁体を導電性ワイヤを横切るように所定の
幅で切断する工程とを含むことを特徴とする半導体装置
用配線基板の製造方法。
8. A step of arranging a pair of mask plates in which a plurality of through holes are formed at mutually different pitches in parallel, and a step of inserting a conductive wire into each corresponding through hole of the pair of mask plates, A step of embedding at least the conductive wire between the pair of mask plates in an insulator while the conductive wire is tensioned in the pair of mask plates; and crossing the conductive wire through the insulator in which the conductive wire is embedded. And a step of cutting the wiring board to a predetermined width.
JP13092295A 1995-05-30 1995-05-30 Wiring board for semiconductor device, and its manufacture Pending JPH08330469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13092295A JPH08330469A (en) 1995-05-30 1995-05-30 Wiring board for semiconductor device, and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13092295A JPH08330469A (en) 1995-05-30 1995-05-30 Wiring board for semiconductor device, and its manufacture

Publications (1)

Publication Number Publication Date
JPH08330469A true JPH08330469A (en) 1996-12-13

Family

ID=15045879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13092295A Pending JPH08330469A (en) 1995-05-30 1995-05-30 Wiring board for semiconductor device, and its manufacture

Country Status (1)

Country Link
JP (1) JPH08330469A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926931A1 (en) * 1997-04-16 1999-06-30 Shinko Electric Industries Co. Ltd. Wiring board having vias
WO2004064162A1 (en) * 2003-01-08 2004-07-29 Hamamatsu Photonics K.K. Wiring substrate and radiation detector using same
WO2004093194A1 (en) * 2003-04-11 2004-10-28 Hamamatsu Photonics K.K. Radioactive ray detector
EP1492168A1 (en) * 2002-03-08 2004-12-29 Hamamatsu Photonics K.K. Sensor
JP2005183669A (en) * 2003-12-19 2005-07-07 Tdk Corp Mounting substrate and electronic component using it
US7230247B2 (en) 2002-03-08 2007-06-12 Hamamatsu Photonics K.K. Detector
US7545044B2 (en) 2003-02-24 2009-06-09 Hamamatsu Photonics K.K. Semiconductor device and radiation detector employing it
JP2011082496A (en) * 2009-09-09 2011-04-21 Dainippon Printing Co Ltd Through-hole electrode substrate and method of manufacturing the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926931A1 (en) * 1997-04-16 1999-06-30 Shinko Electric Industries Co. Ltd. Wiring board having vias
EP0926931A4 (en) * 1997-04-16 2006-12-06 Shinko Electric Ind Co Wiring board having vias
EP1492168A1 (en) * 2002-03-08 2004-12-29 Hamamatsu Photonics K.K. Sensor
EP1492168A4 (en) * 2002-03-08 2007-03-28 Hamamatsu Photonics Kk Sensor
US7230247B2 (en) 2002-03-08 2007-06-12 Hamamatsu Photonics K.K. Detector
US7326907B2 (en) 2003-01-08 2008-02-05 Hamamatsu Photonics K.K. Wiring substrate and radiation detector using same
WO2004064162A1 (en) * 2003-01-08 2004-07-29 Hamamatsu Photonics K.K. Wiring substrate and radiation detector using same
CN100401523C (en) * 2003-01-08 2008-07-09 浜松光子学株式会社 Wiring substrate and radiation detector using same
US7545044B2 (en) 2003-02-24 2009-06-09 Hamamatsu Photonics K.K. Semiconductor device and radiation detector employing it
CN100409447C (en) * 2003-04-11 2008-08-06 浜松光子学株式会社 Radioactive ray detector
US7507971B2 (en) 2003-04-11 2009-03-24 Hamamatsu Photonics K.K. Radioactive ray detector
WO2004093194A1 (en) * 2003-04-11 2004-10-28 Hamamatsu Photonics K.K. Radioactive ray detector
JP2005183669A (en) * 2003-12-19 2005-07-07 Tdk Corp Mounting substrate and electronic component using it
JP2011082496A (en) * 2009-09-09 2011-04-21 Dainippon Printing Co Ltd Through-hole electrode substrate and method of manufacturing the same
US9443788B2 (en) 2009-09-09 2016-09-13 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate
US10014244B2 (en) 2009-09-09 2018-07-03 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate
US20180277471A1 (en) * 2009-09-09 2018-09-27 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate
US10600728B2 (en) 2009-09-09 2020-03-24 Dai Nippon Printing Co., Ltd. Through-hole electrode substrate

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