JPS582492B2 - Hot air conditioner - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention aims to provide a sawtooth wave frequency division circuit capable of performing sawtooth wave frequency division at an arbitrary frequency division ratio.

What is conventionally known as a sawtooth wave frequency divider circuit is a combination of a plurality of cascaded square wave frequency dividers and a summing mixer circuit.

In other words, a rectangular wave frequency divider is used that is synchronized with the input sawtooth wave, and the repetition period is 2 times, 4 times, 8 times, etc. of the input sawtooth wave and connected in cascade. It was added based on the ratio.

FIG. 1 shows a waveform diagram for explaining the operation of this device.

A is an input sawtooth wave, and B, C, and D are rectangular waves with repetition periods of 2 times, 4 times, and 8 times, respectively.

E is the divided sawtooth output It is synthesized as

In the above conventional device, the repetition period is doubled, quadrupled, eight times,...
In general, it is possible to divide the frequency by a factor of 2n (where n is an integer), but it cannot be applied to other factors such as 3 times, 7 times, etc.

The present invention provides a circuit system which does not have the drawbacks of the above-mentioned conventional example, can easily realize frequency division by an arbitrary integer ratio, and is suitable for integration into an integrated circuit.

The present invention will be explained below with reference to Examples, but it goes without saying that the present invention is not limited to these Examples.

FIG. 2 shows an embodiment of the present invention, and FIG. 3 is a waveform diagram of a main part of the actual room example shown in FIG.

In FIG. 2, 1 is a sawtooth wave input terminal, 2 is a clock generation circuit that receives the input sawtooth wave and generates two-phase clocks φ1 and φ2, 3 and 4 are lines for clocks φ1 and φ2, respectively; 5.6 .7 is a ring counter circuit driven by clocks φ1 and φ2, 8 and 9.10 are operational amplifiers for mixing, and 11, 12, and 13 are calculations for reversing the polarity with two resistors γ each. amplifier,
14, 15, and 16 are frequency division output terminals that output sawtooth waves whose frequencies are divided by 1/2, 1/3, and 1/4, respectively.

Figure 3 shows the signal waveforms of each part in Figure 2, and V1 is terminal 1.
The input sawtooth waves, φ1 and φ2, are generated by the clock generation circuit 2 and are two-phase clocks that drive the ring counters 5 and 6.7. Q11 is the output of the ring counter 5, Q21, Q2
2 is the output of ring counter 6, Q31, Q32, Q33
is the output of the ring counter 7, and V14, V15, and 16 are the outputs of the frequency division output terminals 14, 15, and 16, respectively.

Next, the operation of the embodiment shown in FIG. 2 will be described with respect to the case where the frequency is divided by 1/4, that is, the 1/4 frequency divided signal of the input sawtooth wave at the terminal 1 is obtained at the terminal 16.

The input signal V1 is converted by the clock generating circuit 1 into clocks φ1 and φ2 having mutually opposite phases.

φ1 and φ2 drive the ring counter 7.

An example of the structure of the ring counter 7 is shown in FIG. 4a.

In Figure 4a, 71, 72, and 73 are all D flip-flops, 74.75 is a 2-input AND gate, and 16
is an inverter.

When the output of the D flip-flop 13 becomes high level, a low level is input to the D flip-flops 71-73, and at the next clock timing, all outputs of the D flip-flops 71-73 become low level.

While the output of 73 is at low level, the input of 71 is supplied with a high level, and the inputs of 72 and 73 are supplied with the outputs of 71 and 72, respectively.

An example of the circuit configuration of the D flip-flop 71 is shown in FIG.

The same applies to 12 and 73. 711,714.118 is n
-Channel enhancement type MOS transistor, 7
Numerals 13 and 717 are n-channel depletion type MOS transistors, and 712 and 716 are parasitic capacitors, which serve as temporary storage for charges during dynamic operation.

The D flip-flop shown in FIG. 5 is one stage of a dynamic shift register, and reads an input at the rising edge of φ1 and outputs it at the rising edge of φ2.

Although FIG. 5 shows an example in which a dynamic shift register is used as the D flip-flop, a static configuration may also be used, or a charge transfer element such as a BBD (packet gated device) or a C
Figure 4b shows another configuration example of the ring counter 7, which can of course be configured using a CD (charge coupled device), etc., and 77, 78, and 79 are D with a reset function.
It is a flip-flop.

In this case as well, the output signal waveform is the same as in the circuit of FIG. 4a.

From the above circuit configuration, Q31, Q32, and Q33 have a third
The waveform shown in the figure, that is, the waveform whose high-level duty ratios are 3/4, 2/4, and 1/4, respectively, and whose falling timings coincide with each other, is obtained.

Returning to FIG. 2, Q31, Q32, Q33 and V1 are synthesized in an equal ratio by a circuit consisting of four resistors with the same value R, an operational amplifier 10, and a feedback resistor R53, and further the value γ is The polarity is inverted by the two resistors and the operational amplifier 13.

At the frequency-divided output terminal 16, a frequency-divided sawtooth wave output having the same amplitude as the input sawtooth wave and four times the repetition period is obtained as shown in FIG.

In the conventional example, since the rectangular wave frequency dividers are connected in cascade, the frequency of the handled signal becomes lower as it goes to the later stages, but in the circuit system of the present invention, as is clear from Fig. 2, the frequency of the handled signal becomes lower regardless of the number of frequency division stages. Since ring counters 5 to 7 are operated by the same clock, even when a large number of frequency divider circuits are integrated on the same chip, the operating frequency of the circuit is determined only by the input signal, and therefore the circuit design and wafer process condition settings are It is only necessary to optimize for a specific frequency, and there is a large degree of freedom in design.

This is particularly effective when using a dynamic operation circuit.

Further, in this embodiment, a circuit for dividing the frequency of a sawtooth wave with a steep fall has been described, but it goes without saying that a sawtooth wave with a steep rise can also be frequency divided in the same manner according to the present invention.

As explained above using the embodiments, the present invention can provide a circuit that performs sawtooth wave frequency division with an arbitrary integer ratio.
Furthermore, it is possible to provide a circuit that is advantageous in terms of integrated circuit configuration.

[Brief explanation of drawings]

Figure 1 A, B. C, D, and E are waveform diagrams for explaining a conventional device, FIG. 2 is a circuit diagram of a sawtooth wave frequency dividing circuit in an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining a conventional device.
V14, Q21, Q22, V15, Q31, Q32, Q
33, V16 is the waveform diagram for explaining the circuit in Figure 2,
Figures a and b are specific circuit diagrams of a portion of the circuit in FIG. 2, and FIG. 5 is a circuit diagram of a further portion of the circuit in FIG. 4a. 1... Sawtooth wave input terminal, 2... Clock generation circuit, 5, 6.7... Ring counter circuit, 8, 9, 10, 11, 12.13 ......Operation amplifier, 14, 15.16... Frequency division output terminal.

Claims (1)

[Claims] 1. A means such as a ring counter that is driven by a clock signal synchronized with the input sawtooth wave and outputs pulses with different duty ratios is provided, and the output of this means and the input sawtooth wave are set at equal amplitude ratios. A sawtooth wave frequency dividing circuit characterized by being provided with an adding circuit for adding.