JPS58222562A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten an access time and reduce power consumption by introducing a hierarchical structure to the address system and stored data detecting system. CONSTITUTION:The adjacent two block pairs are selected by a higher-ranked row decoder 14, only a lower-ranked docoder 15 between such block pairs is activated, other lower-ranked decoder are power-cut, and an output is fixed to non- active level. The activated lower-ranked row decoder selects one of large blocks 12, namely, a row of small block and charges a row drive line 4 corresponding to the row up to the active level. Therefore, memory cell accumulation data of the selected row is transmitted to the lower data line 5a which is a bit line and only the lower data line 5a which is one bit line is connected to a sense amplifier 9a within a small block 13 owing to a multiplexer 7a which has received an output of lower-ranked column decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention divides a memory cell array in which a plurality of memory cells are arranged in a matrix into a plurality of blocks, introduces a hierarchical structure in an addressing method and a storage data detection method, and creates an integrated semiconductor device. It is related to storage devices.

FIG. 1 is a plan view showing the layout of a conventional semiconductor memory device. In the figure, (1) is a memory cell, (2)
is a memory cell array in which memory cells (1) are arranged in rows and columns, (3) is a row decoder to which the encoded row address signal is input, (4) is a row drive line, and (5) is a lower data line called a bit line. , (6) Upper data line called the 0 line, (7) column multiplexer, (8) tj: column decoder, (9) sense amplifier, (10) output buffer, (ii) data output terminal It is.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, the encoded row address signal is sent to the row decoder (
3), this row decoder (3) operates and selects one corresponding row. Therefore, only the row drive line (4) corresponding to this selected row is charged to the active level, and the other row drives (m<4) Fl are discharged to the inactive level. Then, the memory cell (1) in the selected row receives the row drive line signal and transmits the stored data to the lower data line (5) corresponding to that column. Further, when the encoded next column address signal is input to the column decoder (8), this column decoder (8) operates and selects one corresponding column. Therefore, the selected column f is connected to the upper data line (6) of the next lower data line (5) corresponding to the selected column via the column multiplexer (7). Therefore, one memory cell (1
) is transmitted to the upper data line (6). This upper data line signal is amplified by a sense amplifier (9), adjusted to a predetermined level by an output buffer (10), and outputted from a data output terminal (11).

However, in a conventional semiconductor memory device, a lower data line (5) which is a bit line and an upper data line (6) which is an I10 line extend in the column direction and row direction from one end of the memory cell array (2) to the other. Since the memory cell is extended, these parasitic capacitances are large, and the time required for the sense amplifier to detect memory cell information is long, resulting in a long access time. In particular, I'5 having a large memory capacity requires a long access time. Recently, a method has been proposed to reduce the I10 line capacitance by providing sense amplifiers in every few columns. It is an object of the present invention to reduce the load capacity to be driven by cells, shorten access time, and provide a semiconductor memory device with low power consumption. All arranged memory cell groups are divided into multiple large blocks, and each large block is divided into multiple small blocks. A row decoder, a lower row decoder to which a lower row address signal is input, an upper column decoder to which an upper column address signal is input, a lower column decoder to which a lower column address signal is input, and a lower column decoder that passes through the memory cell array in the column direction. It amplifies the signals of the upper data line that passes through each large block in the row direction, the lower data line that passes through the small block in the column direction, and the middle data line. a multiplexer that selects one of the upper data lines, a sense amplifier that is controlled by the output of the upper data line, and a sense amplifier that outputs only the selected one of the lower data lines to the upper data line. 2 is a plan view showing an embodiment of the semiconductor memory device according to the present invention. In the same figure, (12)
is a large block, (13) is a small block, and (14) is a chip corresponding to the large block (12). Decoder, (15) t-1 A lower row decoder, (16) 41 memory cell array, which is arranged in the center of the chip corresponding to this large block (12) and receives a lower row address signal, which is a lower group of row address signals. (2
), and an upper column decoder to which an upper column address signal, which is an upper group of column address signals, is input;
17) A lower column decoder arranged at the lower side of the ti memory cell array (2) and to which a lower column address signal, which is a lower group of column address signals, is input; (18) a Fi large block (12);
(19) is an upper data line that passes through the memory cell array (2) in the column direction;
20) is an amplifier that amplifies the signal on the intermediate data line (18) and outputs it to the upper data line (19), and (21) is a multiplexer.

Note that the large output tube (12) is connected to the memory cell array (2).
) is divided into a plurality of blocks, for example, four blocks. Further, the small block (13) is each block when the large block (12) is divided into a plurality of blocks, and the detailed structure thereof is shown in FIG. The small block (13
), (7a) is a sense amplifier for only selected lower data lines (5a) which are all bit lines passing through part (2a) of memory cell array (2) in the column direction. multiplexer connected to (9a), (9a
) is a sense amplifier connected to the memory cell (18), (2
2) is a MOS whose input is the output (17a) of the lower column decoder (17) that passes through the large block (12) in the row direction.
) is a transistor. Note that each row drive line (4) of a part (2a) of the memory cell array (2) is connected to a lower row decoder (1).
Next, the read operation of the semiconductor memory device with the above configuration will be explained.0 First, two adjacent block pairs are selected by the upper row decoder (14), and the lower row decoder (14) between them is connected to the output of 0. 15) is activated, the power of the other lower row decoders is cut off, and the output is fixed at an inactive level of 0. Then, this activated, the next lower row decoder is activated, and the next lower row decoder is activated, and the power of the other lower row decoders is cut off. Select one row in the small block and move the row drive line (4) corresponding to that row.
? ? Charge to a four-sexual level. Therefore, the memory cell accumulated data of the selected row is transmitted to the lower data line (5&) which is a bit line, and the lower column decoder output is received by the multiplexer (7a) to select one bit in the small block (13). Lower data line (5a) (7)
The output of this sense amplifier (9m) is connected to the sense amplifier (9m), and the output of this sense amplifier (9m) is connected to the middle data line (18
), but since it is controlled by the upper column decoder output (16a), only the sense amplifier of the small block (13) selected by which upper column decoder detects data.
Drives the intermediate data line (18). At this time, the lower data line (5a) which is a bit line and the multiplexer (7)
Since the parasitic capacitance of &) is small, the data is transferred to the sense amplifier (
9a) is detected immediately. In addition, the power of the other sense amplifiers is cut and the output becomes high impedance. The intermediate data line signal amplified by the sense amplifier is further amplified by the amplifier (20), and the upper data line signal (19) is amplified by the amplifier (20).
), but since it is controlled by the amplifier (20) Fi upper row decoder (14), the unselected amplifier (20
) is power cut and becomes a high impedance output.

In this way, the small block (13) is connected to the upper row decoder (14).
) and the upper column decoder (16) select 1, and the rows and columns in the small block (13) are selected by the lower row decoder (15) and the lower column decoder (1T). In addition, the data lines include a lower data line (5a) which is a bit line that passes through the small block (13) in the column direction, a middle data line (1B) that passes through the large block (12) in the row direction, and a memory Upper data line (19) passing through the entire cell array (2) in the column direction
There are three types, and between them there is a sense amplifier (9a) and an amplifier (20) that are each controlled by the upper row decoder output or upper column decoder output, and can sequentially transmit and amplify data. .

In the above embodiment, the sense amplifier (9a) is controlled only by the output of the upper column decoder (16a), but it goes without saying that it may also be controlled by the output of the upper row decoder (14). be. Also, the intermediate data line (18)
Although the case where an amplifier (20) is provided between the data line and the upper data line (19) is shown, it is of course possible to provide a multiplexer means without an amplification function such as a transfer gate instead. .

As described above in detail, according to the semiconductor memory device according to the present invention, a hierarchical structure is introduced into the addressing method and the storage data detection method, so that a short access time can be obtained. Furthermore, power consumption is reduced by cutting the power of the lower row decoder output by the upper row decoder output, and by dividing the upper column decoder and lower column decoder into two, thereby reducing the total number of column decoder circuits.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the layout If of a conventional semiconductor memory device, FIG. 2 is a plan view showing the layout of an embodiment of the semiconductor memory device according to the present invention, and FIG. 3 is a detail of the small block in FIG. 2. This is a wiring diagram. (1)...Memory cell, (2) and (2b)...
・・Memory cell array, (3) ・・Row decoder, (
4)...Row drive line, (5) and (5b)...
Lower data line (bit line), (6) @... Upper data line (10 lines), (7) and (7a)... Column multiplexer, (8)... Column decoder, (9 ) and (9a)... sense amplifier, (10), φ... output terminal, (11)... data output terminal, (12)
...Large block, (13) ...Small block, (
14)... Upper row decoder, (15)... Lower bone row decoder, (16) ψ... Upper column decoder, (17
)...lower column decoder, (1B)...middle data line, (19)...upper data line, (20)...-
・An7', (21) ・Contest multiplexer, (22
) -- MOS ) transistor. In addition, in the figures, the same symbols are the same or 2+: indicates corresponding parts. 0 Agent Makoto Kuzuno - Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A memory cell array is created in which a group of memory cells arranged in a matrix is divided into multiple large blocks, each large block is divided into multiple small blocks, and an upper row address signal is input to each large block. an upper row decoder that
A lower row decoder to which a lower row address signal is input, an upper column decoder to which an upper column address signal is input, a lower column decoder to which a lower column address signal is input, and an upper data line passing through the memory cell array in the column direction. , a middle data line passing through each large block in the row direction, a lower data line serving as a bit line passing through the small block in the column direction, and a signal on the middle data line being amplified to form an upper data line. a multiplexer that selects one of the upper data lines, a sense amplifier controlled by the output of the upper data line, and a selected one of the lower data lines to this sense amplifier. A semiconductor memory device comprising a multiplexer for connection.