KR100622764B1 - Semiconductor memory device with divided input / output line structure - Google Patents

Abstract

In the semiconductor memory device, the word line is selected by the row address, the bit line is selected by the column address, and data is loaded to the common IO line, and then another column address is enabled. In order to prevent data from colliding with other cells, the common IO line is divided into upper and lower parts of the sub-cell block and controlled to be driven differently. A semiconductor memory device having a line structure.

Description

Semiconductor memory device with divided input / output line structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and in particular, a divided input / output line in which a line from a memory cell to a final input / output pad is arranged to operate without increasing a chip area even when a bus signal, which is a data width, increases. A semiconductor memory device having a structure.

In general, the basic elements constituting the DRAM (hereinafter referred to as 'DRAM') are a cell block capable of storing data, a decoder capable of selecting such a cell, and a selected It consists of a sense amplifier that can amplify cell data. In particular, the decoder uses an X-Address Decoder to select a word line of a cell and a column to select a bit line pair signal (hereinafter referred to as 'BIT, / BIT') signal from cell data. It is divided into an address decoder (Y-Address Decoder). A DRAM having such a structure is shown in Fig. 1, where the row address decoder and column address decoder are omitted.

FIG. 1 illustrates a semiconductor memory device having a conventional input / output line structure in an x4 mode, hereinafter referred to as 'l / O'. The BIT and / BIT lines in the memory cell block 11 are illustrated in FIG. The common IO line and the sense amplifier 13 are located between each cell block 11.

Referring to the process of sensing and transferring data by the above configuration, when the row decoder is enabled by the row address, the word line is selected. When the column decoder is enabled by the column address, the bit lines BIT and / BIT are selected. The data carried on the bit line is amplified by the bit line sense amplifier and then transferred to the common IO line by the column decoder output signal. This data is again amplified by the data busline (hereafter referred to as the 'common IO line') sense amplifier 13 and then passed to the main IO line (or global IO line) and then through the data output buffer to the DQ pin (data output). Pin).

However, in the conventional memory device having the structure as shown in FIG. 1, when data is loaded on the common IO line and data is entered into the same common I / O line when another column address is enabled, the common I / O is eventually obtained. The data of two different cells meet on the line, making correct data output impossible. In addition, FIG. 1 illustrates a case in which the data width is x4. When converting the data width to x8, the IO line has to be doubled as shown in FIG. Therefore, as many layout areas as the number of IO lines are required, this requires a larger layout area for xl6 and x32.

Accordingly, the present invention provides a semiconductor memory device having a divided input / output line structure in which a line from a memory cell to a final input / output pad is arranged to operate without increasing a chip area even if a bus signal, which is a data width, increases. There is a purpose.

In order to achieve the above object, the present invention provides a plurality of sub-cell blocks; Split I / O lines located above and below the sub cell block so that two or more cell data selected by column addresses are transferred to different lines; And local I / O lines located between the sub-cell blocks and connected one by one with the divided I / O lines implemented above and below, wherein the local I / O lines are shared by a certain number of sub cell blocks.

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention, and includes a plurality of subcell blocks 20,

At least two divided input / output lines located above and below the subcell block so that two or more selected by column addresses transmit cell data to different lines;

Located between the sub-cell block and provided with the input and output divided input and output lines and the local input and output lines connected one by one.

According to the present invention, the word line is selected by the row address, the bit line is selected by the column address, and the data is loaded to the common IO line. Then, when another column address is enabled, different cells are stored in the same IO line. In order to prevent data from colliding with each other, the common IO line is separated above and below the subcell block 20. These separate IO lines (hereinafter referred to as 'split IO lines') are controlled by external addresses to be driven differently. In this case, the address controlled to allow cell data to be siled on different divided I / O lines is a column address, and this method is more effective when the data width is x4 / x8 / xl6 / x32.

The divided IO lines are connected to the local IO lines laid out between the sub-cell blocks 20 before being connected to the IO line sense amplifiers, which are connected one by one with the divided IO lines located above and below the upper and lower divided IO lines. Lose.

The sub cell block refers to a certain cell array, but this means that the cell density is divided according to each driving capability by l6M DRAM / 64MDRAM / 256MDRAM. . Accordingly, the number of split I / O lines may also vary depending on the number of cell arrays in the sub cell block, which may be implemented in another embodiment. However, the principle is based on the basic principle of dividing each l / O line into split l / O lines.

As described above, in the semiconductor memory device having the divided input / output line structure according to the present invention, after the word line is selected by the row address, the bit line is selected by the column address, and data is loaded onto the common IO line. When another column address is enabled, in order to prevent data of different cells from colliding with the same IO line, the common IO line is controlled to be driven differently by separating the upper and lower parts of the sub-cell block. In one case, there is less effect of loss of layout area. In addition, since the R / C of the I / O line is smaller, the operation speed is faster and the refresh efficiency is increased.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

1 is a configuration diagram of a semiconductor memory device having a conventional input / output line structure in x4 mode.

2 is a configuration diagram of a semiconductor memory device having a conventional input / output line structure in x8 mode.

3 is a configuration diagram of a semiconductor memory device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawing

11, 12: cell block 13, 14: sense amplifier

20: subcell block

Claims (1)

A plurality of subcell blocks; Split I / O lines located above and below the sub-cell block to transfer two or more cell data selected by column addresses to different lines; And A local I / O line located between the sub-cell blocks and connected to the divided I / O lines implemented one above the other, wherein the local I / O lines are shared by a specific number of sub-cell blocks A semiconductor memory device having an input / output line structure.