KR860002156A - Semiconductor devices - Google Patents

Semiconductor devices Download PDF

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Publication number
KR860002156A
KR860002156A KR1019850005080A KR850005080A KR860002156A KR 860002156 A KR860002156 A KR 860002156A KR 1019850005080 A KR1019850005080 A KR 1019850005080A KR 850005080 A KR850005080 A KR 850005080A KR 860002156 A KR860002156 A KR 860002156A
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KR
South Korea
Prior art keywords
memory cell
information
semiconductor device
bit line
sense amplifier
Prior art date
Application number
KR1019850005080A
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Korean (ko)
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KR890004475B1 (en
Inventor
다까야수 사꾸라이
Original Assignee
사바 쇼오이징
가부시끼 가이샤 도오시바
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Publication of KR860002156A publication Critical patent/KR860002156A/en
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Publication of KR890004475B1 publication Critical patent/KR890004475B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

반도체 장치Semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 일실시예에 따른 반도체 장치의 일부를 나타내는 구성도.1 is a block diagram showing a part of a semiconductor device according to an embodiment of the present invention.

제2도는 제1도의 일부분을 구체화시킨 예를 나타내는 회로도.2 is a circuit diagram showing an example in which a part of FIG. 1 is embodied.

제4도는 본 발명의 다른 실시예에 따른 반도체장치의 일부를 나타내는 구성도.4 is a block diagram showing a part of a semiconductor device according to another embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 어드레스 버퍼 2 : 리프레쉬 어드레스 발생기1: address buffer 2: refresh address generator

3 : 멀티플렉스 4 : 출력회로3: multiplex 4: output circuit

5 : BL11~BL14,,SA11,SA12,SA21,SA22: 감지증폭기5: BL 11 ~ BL 14 , , SA 11 , SA 12 , SA 21 , SA 22 : Sense Amplifier

6 : LA11,LA12,LA21,LA22,LA11',LA12,'LA21',LA22' : 래치회로6: LA 11 , LA 12 , LA 21 , LA 22, LA 11 ', LA 12 ,' LA 21 ', LA 22 ': Latch circuit

7 : S11~S14,S21~S24,2S11,2S12,2S212S,22,2S1,2S2,2S11',2S12',2S21',2S22'7: S 11 ~ S 14 , S 21 ~ S 24 , 2S 11 , 2S 12 , 2S 21 2S, 22 , 2S 1 , 2S 2 , 2S 11 ', 2S 12 ', 2S 21 ', 2S 22 '

: 스위치회로: Switch circuit

8 : CB: 비트선의 용량 9 : CR: 행 디코덩선의 용량8: C B : capacity of bit line 9: C R : capacity of row deco-balloon

10 : DWL1: 더미 워드선 11 : Mc1,Mc2,Mc3,Mc4: 메모리셀10: DWL 1 : dummy word line 11: Mc 1 , Mc 2 , Mc 3 , Mc 4 : memory cell

12 : RD1,RD2,RD3,RD4: 행 디코더 13 : WL1,WL2,WL3,WL4: 워드선12: RD 1 , RD 2 , RD 3 , RD 4 : Row decoder 13: WL 1 , WL 2 , WL 3 , WL 4 : Word line

14 : DMC1,DMC2: 다이내믹 메모리셀 15 : QB,: 비트선 선택용 트랜지스터14: DMC 1 , DMC 2 : dynamic memory cell 15: Q B , : Bit line selection transistor

Claims (3)

메모리셀 어레이와, 상기 메모리셀 어레이의 구성 요소가 되는 각각의 메모리 셀에 접속되어 소정의 메모리셀을 선택하기 위한 어드레스 신호를 전송하는 워드선, 상기 워드선에 의해 선택되어진 메모리셀의 데이터를 전송하는 비트선, 상기 비트선과 접속되어 상기 데이터를 입출력하는 입출력회로 등을 구비하고 있는 반도체 장치에 있어서, 상기 메모리셀 어레이(MC1∼MC4)에 접속되어 있는 비트선(BL11,)의 정보를 감지증폭하는 감지증폭기(SA11∼SA14)(SA21∼SA24)와, 상기 감지증폭기의 출력을 래치시키는 래치회로(LA11∼LA22), 복수의 상기 래치 회로와 데이터선 사이에 각각 접속되면서 행 디코더 출력에 의해서 제어되어지는 스위치 회로(2S11∼2S22), 상기 감지증폭기와 상기 래치회로 사이에 접속되는 감지증폭기 출력측 스위치회로(S 11~S14, S21~S24) 등을 구비하고서상기 감지증폭기에 의해 감지된 제1의 정보를 래치시킨 다음, 상기 감지증폭기 출력측 스위치 회로를 오프 상태로 제어하여 감지증폭기에서 제2의 정보를 감지할 수 있도록 된 것을 특징으로 하는 반도체 장치.A word line that is connected to a memory cell array and each memory cell that is a component of the memory cell array, transmits an address signal for selecting a predetermined memory cell, and transfers data of the memory cell selected by the word line; A semiconductor device including a bit line to be connected to the bit line, an input / output circuit for inputting and outputting the data, and the like, wherein the bit line BL 11 to the memory cell arrays MC 1 to MC 4 are connected. Sensing amplifiers SA 11 to SA 14 (SA 21 to SA 24 ) for sensing and amplifying information of the amplifier; latch circuits LA 11 to LA 22 for latching the outputs of the sensing amplifiers; Switch circuits 2S 11 to 2S 22 controlled by the row decoder output while being connected between the lines , and sense amplifier output side switch circuits S 11 to S 14 and S 21 to be connected between the sense amplifier and the latch circuit . S 24 ) and latching the first information sensed by the sense amplifier, and then controlling the sense amplifier output side switch circuit to an off state so that the second amplifier can sense the second information. A semiconductor device. 제1항에 있어서, 제1의 정보는 통상적인 독출 동작에 따르고, 제2의 정보는 리프레쉬 동작에 따르도록 된 것임을 특징으로 하는 반도체 장치.2. The semiconductor device according to claim 1, wherein the first information is in accordance with a normal read operation and the second information is in accordance with a refresh operation. 제1항에 있어서, 상기 비트선이 다수로 분할된 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the bit line is divided into a plurality. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019850005080A 1984-08-03 1985-07-16 Semiconductor device KR890004475B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59-163508 1984-08-03
JP59163508A JPS6142794A (en) 1984-08-03 1984-08-03 Sense amplifier system of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR860002156A true KR860002156A (en) 1986-03-26
KR890004475B1 KR890004475B1 (en) 1989-11-04

Family

ID=15775195

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019850005080A KR890004475B1 (en) 1984-08-03 1985-07-16 Semiconductor device

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JP (1) JPS6142794A (en)
KR (1) KR890004475B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63298797A (en) * 1987-05-28 1988-12-06 Nec Ic Microcomput Syst Ltd Semiconductor memory
JP2599747B2 (en) * 1988-03-10 1997-04-16 沖電気工業株式会社 Control method of semiconductor memory
JPH01241093A (en) * 1988-03-22 1989-09-26 Fujitsu Ltd Semiconductor memory
JP2552009B2 (en) * 1989-10-27 1996-11-06 日本電気アイシーマイコンシステム株式会社 Semiconductor memory
JPH04119590A (en) * 1990-09-10 1992-04-21 Fujitsu Ltd Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089891A (en) * 1983-10-21 1985-05-20 Nec Corp Semiconductor memory

Also Published As

Publication number Publication date
JPH041434B2 (en) 1992-01-13
KR890004475B1 (en) 1989-11-04
JPS6142794A (en) 1986-03-01

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