KR920006983A - Semiconductor memory device with low noise sensing structure - Google Patents

Semiconductor memory device with low noise sensing structure Download PDF

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Publication number
KR920006983A
KR920006983A KR1019910017156A KR910017156A KR920006983A KR 920006983 A KR920006983 A KR 920006983A KR 1019910017156 A KR1019910017156 A KR 1019910017156A KR 910017156 A KR910017156 A KR 910017156A KR 920006983 A KR920006983 A KR 920006983A
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KR
South Korea
Prior art keywords
bit line
pair
memory device
semiconductor memory
line pair
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Application number
KR1019910017156A
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Korean (ko)
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KR950014243B1 (en
Inventor
도시오 고무로
Original Assignee
세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
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Publication of KR920006983A publication Critical patent/KR920006983A/en
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Publication of KR950014243B1 publication Critical patent/KR950014243B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음No content

Description

저잡음 감지 구조를 가진 반도체 메모리 장치Semiconductor memory device with low noise sensing structure

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 반도체 메모리 장치의 제1실시예를 도시한 회로도,1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention;

제2도는 제1도에 도시된 반도체 장치의 동작을 설명하기 위한 파형도,FIG. 2 is a waveform diagram illustrating the operation of the semiconductor device shown in FIG. 1;

제3도는 본 발명에 따른 반도체 메모리 장치의 제2실시예를 도시한 회로도.3 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention.

Claims (5)

어레이형의 행렬 방향으로 장치된 다수의 메모리 셀, 열 유니트내에 상기 메모리 셀을 접속하는 다수의 비트 라인 페어 및, 행 유니트의 상기 메모리 셀을 접속하는 워드 라인을 포함하는 메모레 셀 어레이, 한 단부에서 각각의 상기 비트 라인 페어에 제각기 접속되고, 각 페어의 비트 라인의 퍼텐셜차를 동작적으로 증폭하는 감지 증폭기와, 제어 신호에 대응하는 최소한 두부분으로 상기 다수의 비트라인을 제각기 분할하는 전달 게이트 수단을 구비하며, 제n열(여기서, n은 홀수 정수임)에 속하는 비트라인 페어에 대한 상기 감지 증폭기는 상기 비트 라인 페어의 한 단부 및 제n+1열에 속하는 비트 라인 페어에 대한 상기 비트 페어의 다른 단부상에 장치되는 반도체 메모리 장치.Memory cell array comprising a plurality of memory cells arranged in an array matrix direction, a plurality of bit line pairs connecting the memory cells in a column unit, and a word line connecting the memory cells in a row unit, one end A sense amplifier which is respectively connected to each of said bit line pairs in sigma, operatively amplifies the potential difference of the bit lines of each pair, and a transfer gate means for dividing said plurality of bit lines into at least two portions corresponding to a control signal, respectively. Wherein the sense amplifier for a bitline pair belonging to an nth column (where n is an odd integer) includes one end of the bit line pair and the other of the bit pair for a bit line pair belonging to an n + 1th column. A semiconductor memory device mounted on an end portion. 제1항에 있어서, 일정한 퍼텐셜을 공급하는 전원라인과, 프리차지 신호에 응답하여 상기 파워소스 라인으로 상기 다수의 비트 라인의 접속을 제어하는 접속 수단을 포함하는 반도체 메모리 장치.2. The semiconductor memory device according to claim 1, further comprising a power supply line for supplying a constant potential and connection means for controlling the connection of the plurality of bit lines to the power source line in response to a precharge signal. 제1항에 있어서, 상기 전달 게이트 수단은 상기 제n비트 라인 페어에 대응하는 다수의 제1전달 게이트 수단과, 상기 n+1비트 라인 페어에 대응하는 다수의 제2전달 게이트 수단을 구비하며, 상기 제어 신호는 상기 제1및 제2전달 게이트 수단에 접속될 수 있는 제1및 제2제어 신호를 포함하는 반도체 메모리 장치.The transfer gate means of claim 1, further comprising: a plurality of first transfer gate means corresponding to the nth bit line pair, and a plurality of second transfer gate means corresponding to the n + 1 bit line pair, And the control signal comprises first and second control signals that can be connected to the first and second transfer gate means. 제2항에 있어서, 상기 접속 수단은 상기 제n비트 라인 페어에 제각기 접속된 제1접속 수단과, 상기 제n+1비트 라인 페어에 제각기 접속된 제2접속 수단을 포함하며, 상기 프리차지 신호는 제각기 제1및 제2접속 신호에 공급되는 반도체 메모리 장치.3. The precharge signal of claim 2, wherein the connection means comprises first connection means respectively connected to the nth bit line pair, and second connection means respectively connected to the n + 1 bit line pair. Is a semiconductor memory device supplied to the first and second connection signals, respectively. 제1항에 있어서, 상기 전달 게이트는 각 비트 라인 페어에 대응하는 둘이상의 수에 제공되고, 상기 제어 신호는 그에 따라 둘이상의 제어 신호를 포함하는 반도체 메모리 장치.The semiconductor memory device of claim 1, wherein the transfer gates are provided in two or more numbers corresponding to each bit line pair, and the control signal accordingly includes two or more control signals. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910017156A 1990-09-29 1991-09-28 Semiconductor memory device with the low-noise sensing structure KR950014243B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26149590 1990-09-29
JP90-261495 1990-09-29

Publications (2)

Publication Number Publication Date
KR920006983A true KR920006983A (en) 1992-04-28
KR950014243B1 KR950014243B1 (en) 1995-11-23

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US (1) US5377151A (en)
EP (1) EP0479170B1 (en)
KR (1) KR950014243B1 (en)
DE (1) DE69121503T2 (en)

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JP3358030B2 (en) * 1993-01-22 2002-12-16 日本テキサス・インスツルメンツ株式会社 Semiconductor memory device and initialization method thereof
JP3397404B2 (en) * 1993-08-09 2003-04-14 株式会社日立製作所 Semiconductor storage device
US5499218A (en) * 1995-01-31 1996-03-12 Goldstar Electron Co., Ltd. Method for driving bit line selecting signals
JP3268158B2 (en) * 1995-03-31 2002-03-25 株式会社東芝 Semiconductor device and manufacturing method thereof
KR100489355B1 (en) * 1997-11-20 2005-08-17 주식회사 하이닉스반도체 Memory element for noise reduction
JP3415420B2 (en) * 1997-12-01 2003-06-09 株式会社東芝 Semiconductor integrated circuit device
US5999477A (en) * 1998-06-23 1999-12-07 Vanguard International Semiconductor Corporation Distributed array activation arrangement
KR100335267B1 (en) * 1998-06-29 2002-09-25 주식회사 하이닉스반도체 Semiconductor memory device reduces the consumption of sensing current
JP4050839B2 (en) 1999-01-29 2008-02-20 松下電器産業株式会社 Semiconductor memory device
JP3348432B2 (en) * 1999-09-14 2002-11-20 日本電気株式会社 Semiconductor device and semiconductor storage device
KR100516695B1 (en) * 1999-12-30 2005-09-22 주식회사 하이닉스반도체 Row active method of semiconductor memory device
FR2881564B1 (en) * 2005-02-02 2007-06-01 St Microelectronics Sa INTEGRATED MEMORY CIRCUIT, ESPECIALLY SRAM MEMORY AND CORRESPONDING MANUFACTURING METHOD
CN102170292B (en) * 2011-01-31 2014-05-07 华为技术有限公司 Data processing method, data processing system and related equipment

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JP2712128B2 (en) * 1988-10-11 1998-02-10 株式会社日立製作所 Semiconductor storage device
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JPH02302986A (en) * 1989-05-16 1990-12-14 Mitsubishi Electric Corp Dynamic type semiconductor memory

Also Published As

Publication number Publication date
EP0479170B1 (en) 1996-08-21
DE69121503D1 (en) 1996-09-26
KR950014243B1 (en) 1995-11-23
DE69121503T2 (en) 1997-02-13
EP0479170A3 (en) 1993-02-24
US5377151A (en) 1994-12-27
EP0479170A2 (en) 1992-04-08

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