JPS58220540A - 網輻輳制御方式 - Google Patents

網輻輳制御方式

Info

Publication number
JPS58220540A
JPS58220540A JP57102144A JP10214482A JPS58220540A JP S58220540 A JPS58220540 A JP S58220540A JP 57102144 A JP57102144 A JP 57102144A JP 10214482 A JP10214482 A JP 10214482A JP S58220540 A JPS58220540 A JP S58220540A
Authority
JP
Japan
Prior art keywords
speed
low
circuit
receiving
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57102144A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0378018B2 (enExample
Inventor
Hisashi Matsumura
松村　久司
Osamu Ishiwata
石綿　修
Takeshi Harakawa
原川　竹氏
Kazufumi Ishikawa
石川　和文
Hiroyuki Wada
和田　宏行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi High Tech Corp
Original Assignee
Hitachi Ltd
Hitachi Electronics Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Electronics Engineering Co Ltd filed Critical Hitachi Ltd
Priority to JP57102144A priority Critical patent/JPS58220540A/ja
Publication of JPS58220540A publication Critical patent/JPS58220540A/ja
Publication of JPH0378018B2 publication Critical patent/JPH0378018B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
    • H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
    • H04L12/525—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques involving a stored program control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
JP57102144A 1982-06-16 1982-06-16 網輻輳制御方式 Granted JPS58220540A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57102144A JPS58220540A (ja) 1982-06-16 1982-06-16 網輻輳制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57102144A JPS58220540A (ja) 1982-06-16 1982-06-16 網輻輳制御方式

Publications (2)

Publication Number Publication Date
JPS58220540A true JPS58220540A (ja) 1983-12-22
JPH0378018B2 JPH0378018B2 (enExample) 1991-12-12

Family

ID=14319552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57102144A Granted JPS58220540A (ja) 1982-06-16 1982-06-16 網輻輳制御方式

Country Status (1)

Country Link
JP (1) JPS58220540A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240149A (ja) * 1987-03-27 1988-10-05 Yokogawa Electric Corp デ−タ伝送バツフア回路
CN112651208A (zh) * 2020-12-30 2021-04-13 杭州加速科技有限公司 一种fpga芯片内各模块之间的布线拥塞优化方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63240149A (ja) * 1987-03-27 1988-10-05 Yokogawa Electric Corp デ−タ伝送バツフア回路
CN112651208A (zh) * 2020-12-30 2021-04-13 杭州加速科技有限公司 一种fpga芯片内各模块之间的布线拥塞优化方法

Also Published As

Publication number Publication date
JPH0378018B2 (enExample) 1991-12-12

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