JPS5821908A - Signal suppressing circuit - Google Patents

Abstract

PURPOSE:To attain the suppression of signal without using any diode characteristics, by obtaining the optional suppression characteristics even to an input signal of a low signal amplitude and at the same time simplifying the control of the suppression characteristics. CONSTITUTION:When the input signal S1 is set at O, the base potential of a transistor (TR) T2 is equal to the value obtained by subtracting the A-K voltage VD3 from the reference voltage V4 which is applied via a bias resistance R4. On the other hand, the base potential of a TRT1 is equal to the value obtained by subracting the A-K voltage VD4 from the voltage V4. The emitter potentials of the TRs T1 and T2 are set at the level which varied by the B-E potential respectively. Here the emitter potentials of the TRs T1 and T2 are equal to the voltage V4 if the accuracy is high for the diode and the transistor. Thus no current flows to a load resistance R4. With application of the signal S1, the base voltages of TRs T1 and T2 vary by a degree of S1. The emitter voltage also changes in the same way. Thus a current flows to a load resistance R5 by an amount equivalent to the change of said emitter voltage.

Description

[Detailed description of the invention] The present invention relates to a signal suppression circuit.

FIG. 1 shows a circuit diagram of a conventional signal suppression circuit using diodes. In Figure 1, S is the input signal, C
The part is the DC blocking capacitor, and the R part is the /IAS resistor.
R3 and R3 are respectively load resistances, vl-■? call and v
3 is a bias voltage, D and D2 are diodes, 10 is an adder circuit, and 11 is an output terminal.

A brief explanation of the operation is as follows.

The input signal S□ is a sine wave signal having positive and negative amplitudes as shown in FIG. 2, with the bias voltage V set at the average level. As shown in FIG. 3, the current flowing through the diode D2 is equal to the bias voltage V of the load resistor R3, the voltage between the input signal S and the bias voltage V, where vB1!
, :voltage between the anode and cathode of the diode Imo, reverse saturation current T: absolute temperature, Boltzmann constant q: charge amount.In other words, in Fig. 3, vBIc
+v1, the current flowing through the diode D2 has diode characteristics.

On the other hand, in the negative direction of the input signal S, similarly, the load resistance R2
The voltage is converted by the bias voltage v2 and the voltage FILI and 111' determined based on the aforementioned V, (=V knee V,), the voltage drop of load resistance R$l e %, and K, and the voltage is converted into nine positive and negative halves, respectively. Positive 7J signal per cycle: VoU, (+)! V3+(I,.-R3
) Negative direction: voU, r←)=V2- (I F, 0'・
R2) are added by the adder circuit 10 and then output from the output terminal 11.

In the signal suppression circuit using diodes as described above, the suppression characteristics are determined by the diode characteristics, and therefore, in order to obtain an output signal that is not affected by the diode characteristics, it is necessary to increase the input signal amplitude. However, since the DC potentials for each positive and negative half cycle are not equal, it is necessary to match the DC potentials and add them.

Therefore, an object of the present invention is to be able to obtain arbitrary suppression characteristics even for input signals with low signal amplitudes without being affected by diode characteristics, and to easily adjust the suppression characteristics. The object of the present invention is to provide a signal suppression circuit that can suppress signals.

FIG. 4 shows a circuit diagram of a signal suppression circuit according to an embodiment of the present invention. In Fig. 4, S is an input signal, C2 is a DC blocking capacitor, I and 2 are bias currents, D3 and D4 are base bias diodes, T0 and T2 are output transistors of class AB operation, R, a Bias resistance for input signal, R5 is load resistance, v
4 is a reference voltage, 12 is a current controlled current source, and 13 is an output terminal.

A brief explanation of the operation is as follows.

When the input signal S is zero, the pace potential of the transistor T2 is equal to the reference voltage v applied through the bias resistor R4.
4 to the anode-cathode voltage VD of diode D3
It is now v4-vD3, which has dropped by 5 minutes.

On the other hand, the pace potential of the transistor T is similarly increased by the anode-cathode voltage VD4 of the diode D4 to v4+vD4. Further, the emitter potential of the transistor T2 is the emitter potential, the emitter potential vBF, and the emitter potential vBF, 0. The emitter of the transistor T is v4'' VD4-■Bl!!l-) The emitter of the transistor T is v, -VD3+V□2. , diode Ds m D4 and transistor T, T2 are each made with great precision, then VD
4=VB! ! ! l “D!Is” vBI2 and Nap,
The emitter potential of the transistor J' Tl e T2 becomes equal to the reference voltage v4, and no current flows through the load. Furthermore, when the input signal S is input, the pace voltage of the transistor T2 mentioned above changes by the amount of the input signal S0, and the emitter potential changes as well, so the changing voltage, i.e. On the other hand, the voltage-controlled current source 12 has a current value controlled by the input signal S, and the current corresponding to the difference voltage between the input voltage S and the reference voltage v4 is added to the load resistor R5. The configuration is such that

FIG. 5 shows a signal suppression circuit configured to use the input signal S as a control signal after being amplified by the amplifier circuit 14 in order to increase the sensitivity 't of the voltage-controlled current source 12.

The operation of the signal suppression circuit shown in FIG. 4 will be further explained using the specific circuit diagram shown in FIG. 6 and the signal waveform diagram shown in FIG. 7 as follows.

The operation when the input signal S is zero (this will be explained below).

Diodes D3t and D4 are resistors R. The active region is biased by a bias current I2 composed of a transistor T3 and a bias current I composed of a resistor R and a transistor T4, and the midpoint potential thereof is
It is made to match the reference voltage v4 through the bias resistor R4.

The anode of the diode D is connected to the pace of the transistor T□, and the cathode of the diode D30 is connected to the pace of the transistor T.

The emitters of T2 are commonly connected and biased to a reference voltage V, through a common load resistor R5. That is,
The voltage between the anode and cathode of the diode D3 and the voltage between the base and emitter of the transistor T2 are the same, and the voltage between the anode and cathode of the diode D4 and the voltage between the base and emitter of the transistor T are the same. Emitter of T2 and reference voltage 74
The current between them is zero. On the other hand, transistors T and TT
The output current of the first voltage controlled current source constituted by the resistor R1o and the resistor R1o is as follows. The pace potential of the transistor T8 is reduced from the reference voltage v4 by the diode D3 to a nine voltage v.
B8=v4-vD3, and the pace potential of the transistor is the voltage VB, which is the voltage dropped by the diode D5 to rftJll, = v4-VD5, and the pace potential of the transistor
e D5 m) transistor T, and resistor R12
If the bias current of diode D5 determined by and the bias current I2 of diode D4 are equal, then VB8=
vB. Therefore, the output current I of this first voltage-controlled current source. 8 is 1 out of 1 VB8-VB9 = O vT, KT. However, ■ and o are transistors T. It is a constant current determined by the emitter potential of and the resistor R.

Also, transistors T5e T6 * T7 and resistor R8
The output current of the second voltage controlled current source composed of
If transistors T4 and T2 and diodes D4 and D6 are equal, then transistor T6. The base potentials of T, , , are vB6=v4+VD4, VB7=v4+vD6, rounding, where vD4=vD6, and VB6=VBf, respectively. Therefore, the output current ■. 6 becomes g + 1. However, I5 is a constant current determined by the emitter potential of transistor T5 and resistor R8.

Here, ξ is the constant current I of the first voltage controlled current source. If the constant current I5 of the second voltage-controlled current source is made equal, then 1
o8-Io6=O, and the current from the voltage-controlled current source does not flow through the load resistor R5 when there is no signal.

Next, the operation when the input signal vs has positive polarity will be explained. Transistor T
Therefore, a signal current flows through the load resistor R5. On the other hand, the output currents of the first and second voltage controlled current sources are respectively transmitted by the transistors T8.
Since the pace potential of T changes, it changes as shown below.

■D8=(v4+vs)-vD, VD6=(V,+V8)-VD Therefore, transistors T8 and T, and transistors T6 and T? The total cabinet voltage is VB8- vB,z ((V, +
V8)-VD3)-(v,-vD5)= vsvB6-
VB, = ((v, +v8]-vD-1(v4-VD6)
= vs. On the other hand, the output current I , I ke, 06
08 (10). As a result of this rounding, the output currents of the first and second voltage-controlled current sources become %I(8>IO2), and the difference current valve is supplied with the emitter current of the transistor T, resulting in a load resistance Current 1OUT flowing through R5
is・■=■−CIo8−1゜6) OUT B. That is, the signal current (8) corresponding to the current (Io8-16) does not flow from the transistor T to the load resistor R5, but instead flows to the voltage controlled current source.

The amplitude of the input signal S corresponding to the current supplied to the first and second voltage controlled current sources is suppressed as the voltage waveform output to the output terminal 13.

Further, when the input signal v8 has negative polarity, the voltage and current of each part change as follows.

The emitter potential of the transistor Tz e T2 is D,
g (V, -V8), the signal current I8 is toned, ) the pace potential of the transistor TBe T6 is v
B6 = c v, -V8) + 'VD.

v - (V - V) - VD3 B8　　　　　　　B becomes.

Transistors T6 and T, and transistors T8 and T.

The base potential differences are VB8-VB, -((V, -VS)-VD3)-(V
, -VD, ) = -V8VB6-VB, = ((V
, -V8) -VD--(V, -VD6) == -V8.

Therefore, the currents of the first and second voltage controlled current sources are:
Each is as follows.

5 106 > IO8 The difference current (Io,
-1o8) is the same as when inputting the positive polarity signal described above.
The current flowing to the load resistor R6 is supplied from the voltage controlled current source as the emitter current of the transistor T2.
OU'l' is '0UT='El - (108-1
06) The amplitude of the input signal S corresponding to the current of Tonashi' (■06-ICB) is not output,
The output signal is suppressed in the same way as when a positive polarity signal is input.

The relationship between each current and input signal in each of the operating regions described above is shown in FIGS. 7 and 8.

Figure 8 shows the output chambers ff1l and I from the first and second voltage controlled current sources, respectively indicated by fi+ lines 05
C! 8 The current is the difference current between the two, and % 08 is the load resistance R
, the outflow current is 5% IC6 is the inflow current, so the difference current is ■. To close, apply force as shown in Figure 7. !
8 is a signal current, and l0UT is the output current of (I8-I.), which is suppressed in positive and negative levels from the reference potential (0 point).

Figure 9 is Figure 5 Ki? 2 shows a specific circuit diagram of a signal suppression circuit using an amplifier. Transistor any 1aT engineering. , T-engineer 8. T2゜, diodero work.

Resistance R□6e R, R work. , R□ form an amplification circuit. Diode D7 e DB + Dgs
D. , transistors T , T , T , T
, resistance R, R.

is 14 115 16
13 and 14R are bias resistors. The other circuits are the same as the circuit shown in FIG. 6, so their explanation will be omitted.

As described above, the signal suppression circuit of the present invention is composed of nine NPN) transistors and nine PNP) transistors, each having an input signal voltage superimposed on a reference potential inputted to each base and a common load connected to each emitter. ,tm
an AB class output circuit that supplies the load with an output current that increases or decreases in response to the height of an input signal voltage superimposed on the reference potential; and an AB class output circuit that is controlled by the input signal voltage and whose signal amplitude is constant around the reference potential. Within the amplitude of the AB
A small output circuit α output current with a slope opposite to the slope with respect to the input signal voltage, which increases and decreases in response to the height of the input signal voltage, and which becomes one step outside the constant amplitude, is applied to the load before εAB class. Since the output circuit includes a voltage controlled current source that adds and supplies current to the output circuit, the following effects are achieved.

(1) Even if the input signal has a low amplitude, arbitrary suppression characteristics can be obtained.

(Since the suppression range of the two signals can be determined by the gL?It value of the voltage-controlled current source, the suppression characteristics can be easily controlled.

(3) Since this is a signal suppression circuit that does not use diode characteristics, it is not affected by diode characteristics.
The input/output characteristics of the unsuppressed level of the signal have good ull characteristics.

(4) Good temperature stability of suppression characteristics.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional signal suppression circuit, FIGS. 2 and 3 are respective signal waveform diagrams, FIG. 4 is a circuit diagram of a signal suppression circuit according to an embodiment of the present invention, and FIG. 5 is a modified version. FIG. 6 is a specific circuit diagram of the circuit shown in FIG. 4, FIGS. 7 and 8 are signal waveform diagrams thereof, and FIG. 9 is a specific circuit diagram of the circuit shown in FIG. 5. T...NPN) transistor, T2...PNP
) transistor, -... reference voltage, R5... load resistance, R4... resistor, 12... voltage controlled current source Fig. 1 Fig. 6 Fig. 2 Fig. 3 Fig. 4 Fig. 5

Claims (1)

[Claims] The input signal voltage superimposed on the reference potential is input to each base, and a common load is connected to each emitter.
ABIi is composed of a PN ) transistor and a PNP ) transistor, and supplies the load with an output current that is superimposed on the reference potential and increases or decreases in response to the level of the running input signal voltage.
AB power circuit, controlled by the input signal voltage, the signal amplitude of which is controlled by the input signal voltage at a slope opposite to the slope of the AB class ratio output circuit output current with respect to the input signal voltage within a constant amplitude centered on the reference potential; a voltage-controlled current source that supplies the load with a substantially step-like current that decreases in response to the height of the amplitude and remains constant outside the constant amplitude; circuit.