JPS58218260A - Compressed data decoding system - Google Patents

Abstract

PURPOSE:To realize the high speed decoding operation, by combining a controlling part, which performs some controlling operation and, an exclusive use decoding circuit. CONSTITUTION:The output (f) of a flip-flop circuit FF2, which is firstly set to the specific state and performs inverse operation according to a signal indicating the finish of decoding operation, assigns the kind of a compressed data. When a compressed data DAT(h) is given to a processor CPU through an input and output circuit I/O and a data bus DAB, a writing and reading pulse is transmitted, and an address assigning signal, which is synchronized with an address bus ADB, is transmitted. They are decoded by a decoder DEC to be given to one of OR gates G1-G4 so that a decoding operation is performed by an exclusive use decoding circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to FJAli, a method for decoding compressed data used in data transmission, etc.

Recently, in 6-cage data transmission, in order to reduce the transmission time when bits of the same logical value are consecutive, compressed data is used to express each successive bit of the same logical value in a compressed form. It is now necessary to decode the received data on the receiving side.

Therefore, in the past, decoding operations were performed by preparing a decoding program and having the processor execute a sible program. Since the required time is relatively long, it has the drawback of causing a time mismatch between the decoding operation and the data transmission.

The present invention has the purpose of fundamentally eliminating the drawbacks of the conventional technology, and is an extremely effective system that achieves faster decoding operations by skillfully combining a control section that performs some control operations and a dedicated decoding circuit. This provides a method for decoding compressed data.

The present invention will be described in detail below with reference to figures showing embodiments, but first, the basic idea of the present invention will be explained.

FIG. 1 is a schematic diagram showing the basics of the decoding operation according to the present invention, and shows an example of decoding 2-bit compressed data. At the start stage "0", first the first bit of the compressed data is logical. It determines whether the value is 11" or 10n, moves to the first stage "1j or 2", and also in this case also determines whether the electric 2 bit of the compressed data is 11" or 0゛'. In the second stage "3" to "6", a decoding result corresponding to the compressed data is obtained. Therefore, each bit constituting a series of compressed data is sequentially included. Store decoding data and a signal indicating the end of the decoding operation, that is, the second stage 13" to "6", to the memory address corresponding to the address designation signal,
Repeats the operation of sequentially specifying memory addresses using data read from memory that sequentially contains each bit of compressed data, and ends the decoding operation when a signal indicating the end of the decoding operation is read from the memory. At the same time, it is only necessary to take out the data read from the memory at this time as the decoding result.

The table below shows an example of the contents stored in such a memory, and shows the contents of data corresponding to each address.

That is, for example, when decoding compressed data '1#vi'', first, at stage '0', address 1 is decoded.
0# Droplet 1" @1* sl# Hayabusa 1# %1""1
Specify “11# and data 'o” to“%0#
%0″% 0# % Q++ % P % 0#
#11 of the compressed data
Beep) Add $1″,%010″10″%0”%O
If you create an address designation signal of n %Qn $011 $15 and specify the address of stage "1" by this, the data IQnIQ "%0#%0 # @ O
II ◆1"%Q# Since %QN is read out, add the second bit %1# of the compressed data to this bit Do, and sO"'o"so'so""0"$1' I
By creating an addressing signal of O"sl" and specifying the address of stage "3", data 11"%0#
"to"so"o"to"to"11" is read out.

Therefore, the data bit Dγ is used as a signal indicating the end of the decoding operation, and the data bit Do=D
If s is used to indicate the content of the compressed data, the result of the sive code is indicated by the data bit Do=Ds.

Therefore, in the above table, s1' is stored in the data pick (Dy) at stages "3" to "6" as a signal indicating the end of the decoding operation, and s1' is stored as a signal indicating the end of the decoding operation.
3" to "6", signals indicating the contents of the compressed data are stored in the data bits Do""Ds in accordance with each stage.

However, the above table corresponds to the compressed data that shows the series of %On, and as a transmission convention, the compressed data that expresses the continuous IQ'' is transmitted first, and then the continuous %1" is transmitted and this is repeated, so for the purpose of decoding the compressed data expressing continuous %1", the 6th bit (A) in the address in the table above is Prepare a similar table with 11" binding, and store it in memory as well.
□Yes. 7.41 E, l, '1llll'1llt,
□, eh.

It is necessary to specify the memory storage area according to the type of compressed data.

Fig. 2 is a block diagram of a concrete circuit configuration using the above basic idea and memory, and Fig. 3 is a timing chart showing waveforms of each part in Fig. 2, and the above-mentioned contents are stored in the memory MM. The readout output of this is held by the latch circuit LAT, and the gate circuit GA
This signal is given as an address designation signal for the memory MM via T, and by repeating this, the above-described decoding operation is realized.

In addition, when the processor CPU as a control unit is given the compressed data DAT(h) via the input/output circuit I10 and the data motherboard 11JDAB, it sends out a write pulse and a read pulse in response to the compressed data DAT(h).
An address designation signal synchronized with each of these pulses is sent to the address bus line ADB, and this is decoded by the decoder DEC to the OR gates 61 to 61. 4o Izuku will give you a cane. Seven.

□ There is. Therefore, first the write pulse is generated as a whisper 0'' and the output Q4 of the decoder DEC becomes %0''. At this time, the output (m) of the OR gate G2 is 41'', so A
The output (a) of the ND gate G5 becomes 10", which causes the 7 lip-flop circuit (hereinafter referred to as F'FC) FF+,
The output (b) of this gate circuit becomes QOI+, and the output of the gate circuit GAT becomes an open state indicating "all contest 1", resulting in the state of stage "0" shown in the table above, and the state of the memory MM is Bit Do=D4 to $011
1ull %OrT times" is read out and held by the latch circuit LAT in response to the clock pulse (9).

However, at this time, since the compressed data DAT (h) is given to the input Do in the two-tuna circuit LAT, the first bit of the compressed data pAT (h) is
It is included and retained by being added to the readout output from the MM.

In addition, the initial reset pulse (d) from K to FF
In this case, C・FF2 is reset as a specific state,
The output (e) is set to 11'', the output (f) is set to $011, and the output (f) is applied to the sixth bit D6 in the gate circuit GAT.

Next, FFc-FF1 is set by the clock pulse (C), and its output (b) becomes "sl", so that the get circuit GAT is turned on, and the holding output (i) of the latch circuit LAT is transferred to the memory. It is given as the MM hair address specification number i, and the stage "1" or "2" in the above table.
The corresponding data is read out and held together with the second bit of the compressed data DAT by the latch circuit LAT in response to the clock pulse <9>. Provided as a memory M address addressing signal.

Therefore, the state will be one of stages "3" to "6" in the table above, and the corresponding data will be read from the memory, and at the same time the processor CPU will send out a read pulse, the output Q2 of the decoder DEC will be %On
In this case, the %OR gate Gm (D output (m) becomes 1on, and accordingly, the register RG is set to the memory MM
The readout output from the DAB is held, and its contents are provided as a decoding result to the processor CPU via the data bus DAB.

In stages "3" to "6", the 7th bit (Dy) of the data is sent from the memory MM as the output (j) of %l#, so FFC and FF3 are is set, and by giving its output (b) to the processor CPU as an interrupt command, the processor CPU writes the content area 9 of the register RG.

Further, at the same time as the processor CPU sends out a write pulse as %Qn, the output Ql of the decoder DEC is set to 10'', so the output of the OR gate Gl (4 becomes 10n, and this resets FFC-FF3. Ru.

However, the decoding operation starts from the moment when the output (b) of FFC-FF1 becomes So'' and returns to 11''. At that point, the decoding circuit ends and the compression is ゛・1゛''.

The above operations are repeated in response to the arrival of data pAT(h).

Note that the decoded result is restored to the state before compression in the processor CPU and sent to a predetermined part via the data bus DAB'.

In addition, the output (when the gong occurs, the output of FFC-FF2 (
Since e) is 11", the output (k) corresponding to the output (j) inverts the FFC "F" F2 and sets it, making the output (f) t - 1", and then sending Compressed data DAT (h
) Specifies the storage area for decoding.

However, in this case as well, the decoding operation is performed in the same manner as described above.

Therefore, the processor CPU only performs a few control operations, which simplifies the program.Since the decoding operation is performed by a dedicated decoding circuit, the time required for decoding is shortened, and the transmission rate is high. It becomes easier to decode DAT(h).

Furthermore, if the processor CPU has each individual output port i, it takes a decoder DEC and an OR gate Gl, G2.04 to obtain the outputs (a), (t), -, etc.
, AND game) Gs, etc. is eliminated, and the same effect can be achieved even if FFC#FF+, FFs, register RG, etc. are replaced with memory, and the processor C
P.U.

The present invention can be modified in various ways, such as using a dedicated control circuit instead.

As is clear from the above description, according to the present invention, high-speed decoding of compressed data is achieved with a relatively simple configuration, so that remarkable effects can be obtained when used in various data transmissions.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the basic idea of the invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a timing chart showing waveforms of various parts in FIG. MM...Memory, LAT...Latch circuit,
GAT--Gate circuit, RG--Register, C
PU... Processor (control unit), FF, -...
・FFC (flip-flop circuit). Patent applicant: ShinNippon Electric Co., Ltd. agent Masaki Yamakawa (and one other person) Figure 1

Claims (1)

[Claims] An addressing signal that sequentially includes each bit constituting a series of compressed data, data for decoding according to the type of compressed data, and a signal indicating the end of the decoding operation are stored in the address of the troubled memory, and first, The type of the compressed data is specified by the output of a free-fly flop circuit that is set to a specific state and performs an inversion operation in response to a signal indicating the end of the decoding operation, and the type of the compressed data is specified according to the control of the control unit based on the compressed data. The operation of sequentially specifying the address of the memory by data read from the memory which sequentially includes each bit constituting the compressed data is repeated, and when a signal indicating the end of the decoding operation is read from the memory, the A compressed data decoding method characterized in that the decoding operation is completed and the data read from the memory at this time is taken out as a decoding result.