JPS5816344A - Data compression and storage device - Google Patents

Abstract

PURPOSE:To reduce the data quantity and decrease the time of the data transfer, by counting the number of the continuous and same data frames and writing the number of the continuous data in the next storage device. CONSTITUTION:The first input data 10 is converted into a write data 14 through a switch circuit 6 to be written into a storage circuit 1 by a write indicating signal 15 supplied from a control circuit 5 and at the same time to be held at a latching circuit 3. The next input data 10 is compared with a comparison data 19 held at the circuit 3 through a comparator 4. When the coincidence is obtained between the data 10 and 19, the circuit 4 feeds the comparison coincidence signal 12 to the circuit 5 in the form of 1. The circuit 5 sets the count indicating signal 11 at 1 to actuate a counter circuit 2 and then sets the signal 15 at 0 to avoid writing the data 10. When no coincidence is obtained between the next data and the preceding data after 2 data 10 are continuous, the signal 12 is set at 0. Then the circuit 5 switches the circuit 6 to the counting signal 18 by the signal 13 to turn it into a data 14. The signal 15 and a marker bit 16 are set at 1, and the data 14 and the bit 16 are written into the circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data compression storage device in a data processing device.

Conventional storage devices have disadvantages in that the amount of data to be stored increases and it takes time to transfer the data because the data sent to them is written as is.

An object of the present invention is to provide a data compression storage device that can reduce the amount of stored data and shorten transfer time.

In other words, one purpose of the present invention is to count the number of consecutive identical data frames, and when the same data is consecutive, write the consecutive number to the storage device next to the data and calculate the amount of data to be stored when the same data is consecutive. The object of the present invention is to provide a data compression storage device I which stores a small amount of data and reduces data transfer time by reducing the amount of data.

The present invention includes a latch circuit that temporarily holds input data, a comparator that compares the data held in the latch circuit with new data, and a counter that counts based on the coincidence output of the comparator. When FC data is input, Q input data is written first. When FC) input data is input, when the comparator outputs a match output, Vi writing is stopped. When the comparator outputs a mismatch output, the counter The value of and ya. Day 2 is the count value. 'v − い(
.

11'.

The data compression storage device of the present invention includes a latch circuit that temporarily holds input data and outputs it as comparison data, and a comparison circuit that compares the comparison data with new human data and outputs a comparison match signal when they match. , a # number circuit that counts according to the comparison match signal and outputs a count signal; and a switching circuit that outputs the it number times signal instead of the input data as write data when the comparison match signal is supplied. When the comparator outputs a discrepancy output, a marker pit is added to indicate that the count signal and 1-inclusive data are count data.
It is configured to include a storage device in which the next write data is written to ``1''.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 shows an example of input data supplied to the embodiment shown in FIG. 1, write data corresponding to this input data, and marker picks. FIG.

The data compression storage device shown in FIG. 1 includes a latch circuit 3 that temporarily holds input data 10 and outputs it as comparison data 19.
, a comparison circuit 4 which compares the comparison data 19 and input data 10 and outputs a comparison match signal 12t when they match; and a comparison circuit 4 which counts the number of consecutive identical data frames and outputs a count signal 1.
8; a switching circuit 6 that switches between the count signal 18 and the input data 10 according to the instruction signal 13 and outputs the result as write data 14; and a storage circuit 1 that stores the write data 14. , based on the comparison match signal 12, outputs a marker pit 16 indicating that the count instruction signal 11 is switched to the instruction code 13 and the write data 14 to be stored is the count signal 18, and outputs the write instruction signal 15. The control circuit 5 is configured to include a control circuit 5. Note that a reset signal 17 is supplied to the counting circuit 2 and the control circuit 5 when initializing them.

When writing data, the counting circuit 2 and the control circuit 5 are initialized in advance by the reset signal 17, and the switching circuit 6 is configured to select input data 1° by the switching instruction signal 13 supplied from the control circuit 5. , the marker pit 16 from the control circuit 5 is also k0g.
Keep it.

The first input data 1o sent to the switching circuit 6
The write data 14 is written into the memory circuit l by the write instruction signal 15 supplied from the control circuit 5, and is held so as to be outputted to the latch circuit 3 as comparison data 19.

Next, the human power data 10 that is sent is compared with the comparison data 19 that is sent first and is held in the latch circuit 3 and the comparison circuit 4.
are compared. If the input data lo and the comparison data 19 match, the comparison match signal 12 becomes '11' and is input to the control circuit 5.

If the comparison match signal 12 is %1g, the control circuit 5 sets a count instruction signal 11t-'1', and the counting circuit 2 counts based on this signal. Further, at this time, the write instruction signal 15trO' is output from the control circuit 5, and the write data 14 is not written.

In this way, if the input data 1o matches the previous data, the counting circuit 2 only counts and the write data is not written to the memory circuit 1.

When the comparison circuit 4 detects that the next input data 10 does not match the previous data after two or more pieces of input data 10 match consecutively, the comparison match signal 12 becomes 10'.

Since the comparison match signal 12 becomes 101, the control circuit 5 first switches the switching circuit 6 from the i instruction signal 13Vc to the counting signal 18 output from the counting circuit 2, and converts this counting signal 18 into The write data is set to 14, the marker pit 16 is set to %1j, and the write instruction signal is set to 15.
is set to 11' and 11' is written in the memory circuit 1 as the count signal 18 and marker pit 16.

When the same data is not consecutive, the control circuit 5 always uses the switching instruction signal 13 to switch the switching circuit 6 to the input data 10.
, and the marker bit 16 is set to 101, and the input data 10 is always written to the memory circuit l.

FIG. 2 shows the write data 14 written to the memory circuit 1 and the marker bits 16e corresponding to each frame of the write data 14 when input data 101 is written to the memory circuit l, indicating that the same data is present. If the count value to the data frame 5. The marker pits 11' are sequentially written into the memory circuit.

The data compression storage device of the present invention has the effect of reducing the amount of data to be stored by compressing the same continuous data and improving the transfer speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a Q-embodiment of the present invention. FIG. 2 is a data configuration diagram showing an example of the human data supplied to the embodiment shown in FIG. 1, and write data and marker pits corresponding to this input data.

Claims (1)

[Claims] A latch circuit that temporarily holds input data and outputs it as comparison data, a comparison circuit that compares the comparison data and new input data and outputs a comparison match signal when they match, and a comparator circuit that performs counting according to the comparison match signal. A counting circuit that outputs a counting signal, a switching circuit that outputs the input data Q 9VC as write data when the comparison match signal is supplied, and a switching circuit that outputs the counting signal when the comparator outputs a mismatch output. 1. A data compression storage device comprising a signal and a memory circuit for writing a marker bit indicating that the write data is counting data and writing the next write data.