JPS58218259A - Compressed data decoding system - Google Patents

Abstract

PURPOSE:To realize the high speed decoding of a compressed data, by finishing a decoding operation when a signal, which indicates the finish of the decoding operation, is read out of a memory, and taking out a reading data out of a memory as a coding result. CONSTITUTION:When decoding a compressed data of 2 bits, a starting stage 0 discriminates whether the 1st bit of the compressed data is 1 or 0 of a logical value, and, according to the result, it is transferred to 1 or 2 of the 1st stage, where the 2nd bit of the compressed data is discriminated whether it is 1 or 0. Then, in the 2nd stage 3-6, a result decoded according to the compressed data is obtained. Therefore, it is sufficient to store a data for address data of a memory corresponding to an address assigning signal, which is successively included with each bit constituting the series of the compressed data, and a signal indicating the finish 3-6 of coding operation, to repeat the operation to assign the address of the memory by means of a reading data out of the memory, and to take out the reading data as the decoded result at the time of finishing the decoding operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for decoding compressed data used in data transmission and the like.

In recent years, in various types of data transmission, compressed data is used to represent each bit of the consecutive same ring value in a compressed form in order to shorten the transmission time when pits of the same ring value are consecutive. In the evening, it is necessary to decode this fl on the receiving side.

Therefore, in the past, the decoding operation was performed by preparing a decoding program and having the processor execute the p7''μ-gram. , since the time required for decoding is relatively long, there is a drawback that a time mismatch occurs between the decoding operation and the data transmission.

The present invention aims to fundamentally eliminate the drawbacks of the conventional technology, and is an extremely effective system that achieves high-speed decoding by skillfully combining a control section that performs some control operations and a dedicated decoding circuit. , which provides a method for decoding compressed data.

Hereinafter, the present invention will be explained in detail with reference to figures showing embodiments.First, the basic idea of the present invention will be explained. An example of decoding compressed data is shown below. In the start stage "0", it is first determined whether the first bit of the compressed data is a logical value of 11'' or 10'', and the rlJ of the first stage is determined accordingly. t7'htli
After moving to "2", the second bit of the compressed data is determined whether 11# is %o〃, and then the compressed data is changed in the second stage "3" to "6". Accordingly, each pix constituting the series of pressure i data corresponds to the address designation signal included sequentially, and the address header of the next memory, 7I-D. data for and 2°-)'111
fe(7)1%7"il, :[〒"'. 1°1~"6"
After repeating the operation of sequentially specifying the address of the L1 memory in the read data from the memory containing each bit of the compressed data sequentially, the decoding operation is finished, and the data from the memory at this time is It is only necessary to take out the read data as the decoding result.

The table below shows an example of the contents stored in such a memory, and shows the contents of data corresponding to each address.

1゛1 □ ゛.

That is, for example, when decoding compressed data of %1〃%l'', first, at stage "0", address
^l〃11″ '1″ is specified and data ss is ON.
, % 0 // % g /ISS 01 Qi 0〃%0
11011 Read turtle 0, add the first bit % 1 // of the compressed data to this bit Do, and get 1.1
o#turtleO#,%gI side〃ki 0〃attached〃ki 0# ki//
After creating an addressing signal for , and specifying the address of stage 4 "l" by nine rc construction, data p 'Xg
I % 0 // % O// Ki g//
-0/7 1%1# %0. ! NO〃 is read, so the second bit of the compressed data is transferred to the second bit)%1 of the compressed data.
．． Add #, 10 “kameo#,'so#%g/l
%g# XXl/+ Mo01 Ki1", (D7
The data 111 is created by creating a DRE δ designation signal and designating the address of stage "3".
j (S OI % g"%g#1lL1# is read 0. Therefore, the data bit D? is used as a signal to indicate the end of the decoding operation, and the data bits Do and D3 are used to indicate the contents of the compressed data. If it is set as shown, the decoding result will be indicated by the data bits Do - Ds K.

Therefore, in the above table, 1" is stored as a signal indicating the end of the decoding operation in the data bit (Dy) of the data in stages "3" to "6". A signal indicating the content of the compressed data is stored in the data bit (Do=Ds) according to each stage.

Figure 2 is a four-dimensional diagram of a specific circuit configuration using the above basic idea and memory, and Figure 3 is a timing chart showing waveforms of each part in Figure 2. is stored at t'L, and its readout output is held by the latch circuit LAT and then given as a signal to specify the address of the memory MM via the group circuit GAT. The above-described decoding operation can be achieved by converting nt.

In addition, as a control unit, the Keyaki:Reirosetsusa CPU transmits compressed data D via the input/output circuit I10 and data mother MDAB.
When AT(h) is given, it sends out write pulses and read pulses in response to input, and also sends addressing signals synchronized with these pulses to the address bus ADB, which in turn sends an E-fed to the decoder DEC. Therefore, if the write pulse is generated as 10'' and the output Q4 of the decoder DEC becomes 10'', then this When the output of OR gate G2 (→ is '1〃, the output (&) of AND game) becomes '0'',
Here, ni↓ is a flip-flop circuit (hereinafter referred to as FFC)
When the FFI is reset, its output (b) becomes 0", and the output of the gate circuit GAT becomes all-1 (temporarily open state), resulting in the stage "0" state shown in the table above, and the memory MM's it Do=Da to -61'
IIQ 0/I Whisper 0// is read out and output to the latch circuit LAT in response to the /, o clock pulse (f) 1'''
be held back.

7' (W) At this time, since the compressed data DAT(h) is given to the input Do of the latch circuit LAT, the first bit of the compressed data DAT is added to the readout output from the memory MM. Including Niji n, it is further retained.

In addition, the processor CPU sends the 6th bit D to 10'' of the data terminal, and the write pulse t
In order to send it as '0' and make the output Q3 of the decoder DEC %0, the FFC-FF snow is reset by the output (d) of the 6th bit and the output (,) of the OR gate Gs. The output (f) is applied as 1ON to the sixth bit (D+s) at the input of the gate circuit GAT.

Then, clock pulse (c) is applied to clock pulse (c).
is set, and its output (b) becomes %IN19. When the gate circuit GAT turns on, the holding output 0) of the latch circuit LAT is given as an addressing signal to the memory MM, and the above table The stage of rlJ゛Matasha'
2" state, the data corresponding to this is read out,
Since it is held in the latch circuit LAT together with the second bit of the digital compressed data DAT (h) in response to the clock pulse (f), this is again applied to the memory MM as an addressing signal via the gate circuit GAT.

Therefore, Izn in stages "3" to "6" in the above table.

This state occurs, and the corresponding data is read out from the memory, and at the same time as the processor CPU sends out a read pulse, the decoder DEC outputs Q*t.
To set -% OW, the output of OR gate G (- is 1015), correspondingly, register RG holds the readout output from memory MM, and the contents of the input are stored as data as the decoding result. 0 applied to the processor CPU via the bus DAB 'e. Note that in stages Qr3J to "6", the seventh bit D7 of the data from the memory MM is 11.
The output (j) is the output (j) of 4.
) The p1 processor CPU takes in the contents of the register RG by giving it to the t processor CPU as an interrupt command.

9. Next, at the same time as the processor CPU sends out the write pulse as '0', the decoder DE
A method to set the output Q1 of C as O'l, OR gate G
The output of 1 (4 is Qi O), this flK is FFC
-FF+1 is reset to 0, therefore FFC-F
After the output (b) of F1 becomes Qi O〃, 'IIIJF
The decoding operation starts from the moment the FFC returns to
- The decoding operation ends when the output (ω) of FF8 reaches %O'', and the above operation is repeated in response to the arrival of compressed data DAT(h).

Note that the decoded result is restored to the state before compression in the processor CPU and sent to a predetermined part via the data bus DAB.

t+, the compressed data D A T (h) is transmitted as a transmission convention that the data representing continuous %0" is transmitted first, followed by the data representing continuous 'v'1", This is fL'lH anti-i1 is anti-hair 1, and the divination data DAT expressing continuous '1'' is de=r-h't aeya, □,.nashi7□oyu, 6゜ツ)1
−″1〃 The next table is stored in the memo IJMM, and after completing the above decoding operation, the processor C
The output (d) of the 6th bit D6 in PUK is -IN
Turning to FFCFF5, the output (f) of this is set to %lN, and the stored contents are specified in order to decode the compressed data DAT that continuously represents 7't'l'. In this case as well, the decoding operation is performed in the same manner as described above.

Therefore, the processor CPU only performs a few control operations.9 The program is simplified, and the decoding operation is performed by a dedicated decoding circuit, so the decoding time is shortened and the compressed data can be transferred at a high transmission rate. DAT (h)? It becomes easy to decode.

In addition, if there is an individual output port for each processor CPU K, to obtain the outputs (,)', (,), (→,
If the need to use AND gate G11, etc.' is eliminated, 1i-'J, FFC-FF5t to FFs and register R
The same is true even if G etc. are replaced with memory, and the processor CP
The present invention can be modified in various ways, such as a dedicated control circuit may be used in place of U.

As is clear from the above description, according to the present invention, high-speed decoding of p1 compressed data is realized with a relatively simple configuration, and remarkable effects can be obtained when used in various data transmissions.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the basic idea of the invention, FIG. 2 is a block diagram showing an embodiment of the invention, and FIG. 3 is a timing chart showing the waveform of each i in FIG. MM...-Mesori, LAT--Latch circuit, G
AT-...Gate circuit, RG...Register, CP
U...Processor (control unit) 0 Patent applicant: ShinNippon Electric Co., Ltd. Agent, Uneki Yamakawa (and one other person) Figure 1

Claims (1)

[Claims] Data input for decoding and a signal indicating the end of the decoding operation are stored in a memory address corresponding to an address designation signal that sequentially includes each pit constituting a series of compressed data, and a signal indicating the end of the decoding operation is stored in accordance with the control of the control unit based on the compressed data. repeating the operation of sequentially specifying the address of the memory using data read from the memory sequentially including each bit constituting the compressed data, and a signal indicating the end of the data operation is read from the memory. A method for decoding compressed data, characterized in that the data read from the memory at this time is taken out as a decoding result at the same time as the decoding operation is completed.