JPS6017798A - Voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a speech synthesis device that uses a fragment synthesis method and a drum-shaped encoding method.

[Prior art and its problems]

Conventionally, speech synthesizers use the speech tree synthesis method or the A
Waveform encoding methods such as L) PGM and Al) M are commonly used. The conventional speech unit synthesis method and waveform encoding method described above are each configured as an independent LSI, and are used depending on the purpose. However, if each synthesis method is configured as a separate LSI as described above, the number of LSIs increases, making manufacturing and management extremely troublesome.

[Purpose of the invention]

The present invention has been made in view of the above points, and includes one LS
It is an object of the present invention to provide a speech synthesis device that can be used in combination with two speech synthesis methods, a speech unit synthesis method and a waveform coding method, without complicating the circuit configuration.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the figure, I is an elemental piece control ROM, which contains amplitude data, elemental piece start address, and pitch data.

The number of segment repetitions, a flag for instructing audio output, etc. are stored, and the contents of the 8-pin memory are read out in accordance with the address designation of the address counter 2, and are folded into the buffers 38 to 3eK by the timing signal φA. And buffer 3aK
The input amplitude data is sent to the segment decoding/synthesizing circuit 4. Further, the segment head address read into the buffer 3b is set in the address counter 5, and the address of the segment ROM 6 is designated according to the contents of the address counter 5. This elemental piece ROM 6 stores an elemental piece waveform. In this case, in order to reduce the amount of information, the segment waveform is written in the segment ROM 6 in the form of AIJPCM or ADM. Moreover, the elemental piece data written to the elemental piece kLOM6' is as follows.

The length is oJ odd and is separated by WNI) marks. For example, if the segment data is stored in the form of 4-bit ADPcM, for example, "1000" among the numerical values represented by the 4 pits is used as the ENJJ mark. Furthermore, data for waveform encoding is written in the segment ROM 6 in the form of ALI)'CM for a certain period of time, for example, several seconds. And the above elemental piece R
The data read from OM e is sent to the end mark detection circuit 7 and also sent to the segment decoding/synthesizing circuit 4 via the AND1gl path 8. The above end mark Kenda episode M7
outputs a detection signal φE when it detects the end mark,
The signal is input to the AND circuit 9, and is also input to the AND circuit 8.degree.11 via the inverter io. Also, AND circuit 1
A clock pulse φ is input to address counter 1, and its output signal is sent to address counter 5 as a count-up signal. On the other hand, in the buffer 3C, the elemental piece control RO
Pitch data is read from MJ, bi, tsuchi counter I
2 and the zero detection circuit 13. In this case, when the elemental piece control kLOM1 reads the waveform encoding data from the elemental piece ROM6, the pitch data output from the elemental piece control kLOMt is set in advance to be "0".

The pitch counter 12 receives a clock pulse φ when the pitch data is set.

, and outputs the count contents to the zero detection circuit 14. This cello detection circuit 14 outputs a signal φpo and supplies it to the AND circuit 15 when the count content of the pitch counter 12 reaches 10''. Further, the output of the zero detection circuit 13 is applied to the AND circuit 15 via an inverter 16 as a signal φ.

This signal φp is further input to AND circuit 9 via inverter 17. And the above AND circuits 9 and 15
The output is inputted to the address counter 5 and pitch counter 12 as a set command through the OR circuit 18 together with the timing signal φS, and is also inputted to the repetition counter Z9 as a down count signal. Further, the number of repetitions of an elemental piece is read out from the elemental piece control ROMI into the buffer 3d, and is set in the repetition counter I9 by the timing signal φB. When the data is set, the repetition counter 19 performs a down-count operation in synchronization with the signal from the OR circuit 18, and provides the count contents to the zero detection circuit 20. When the content of the repetition counter 19 becomes "0", the cell detection circuit 20 detects this state, outputs the signal φR, and counts up the address color/2. Further, a flag is read out from the segment control ROM 1 to the buffer 3e and input to the AND circuit w121. Moreover, this AND circuit Ti1i521 has a clock pulse φ
. is input, and its output is sent to the AND circuit 11 and pitch counter 12 as a clock pulse φ1. Therefore, in the above purple piece decoding/synthesis step #54, the elemental piece R
The OM 6 performs a decoding operation using the segment data read out via the AND circuit 8 and the amplitude data of the buffer 3ah), and the decoded signal is passed through the conversion circuit 22 and output to the outside.

Next, the operation of the above embodiment will be explained. The control data stored in the segment control ROMJ is read out according to the address specified by the address counter 20 and written into the buffers 3a to 3eK in synchronization with the timing signal φAK. Then, according to the data outputted from the buffers 33 to 3eK@, speech synthesis is performed using a speech unit synthesis method or a waveform encoding method. In the case of speech unit synthesis method, buffer 3C
In the case of the % shaping encoding method, the pitch data stored in the buffer 3C becomes 0. First, the speech synthesis operation using the speech unit synthesis method will be explained. In the case of speech segment synthesis, the amplitude data is stored in buffer 3a, the segment start address is stored in buffer 3b, and the buffer 3
Pitch data is written to C, the number of segment repetitions is written to buffer 3d, and a flag is written to buffer 3e in synchronization with the timing signal φ.

Following the timing signal φ, the timing signal φS is applied to the address color/reference 5 and the pitch counter 12 via the OR circuit 18, and the segment head address held in the buffer 3b is set in the address counter 5. At the same time, the pitch data held in the buffer 3C is set in the pitch counter 12. Further, thereafter, the timing signal φB is outputted, and the number of repetitions of the wood piece held in the buffer 3d is set in the repetition counter 19. Further, the gate of the AND circuit 21 is opened by the flag held in the buffer 3e, and a clock pulse φ is generated. is output from the AND circuit 21 as a clock pulse φ1. This clock pulse φ1 is passed through the AND circuit 11 and sent to the address counter 5, whose contents are sequentially counted up.According to the count contents of this address counter 5, the address of the elemental piece ROM 6 is specified, and the elemental piece ROM 6 is designated. Data is read out sequentially. In this case, the output of the end mark detection circuit 7 is 0 until the end mark is read from the elementary piece kLOM 6, and the output of the inverter 10 is 0.
1 and opens the gate of the AND circuit 8. Therefore, the segment data read from the segment ROM 6 is passed through the AND circuit 8 to the segment decoding and synthesis circuit j! It is sent to i54, where the segment waveform data is encoded and multiplied by the amplitude value of the buffer 3a.

Then, this multiplication result is also outputted from the elemental piece decoding/synthesizing circuit 4, converted into analog No. 46 by the IJ/A conversion circuit 22, and outputted to the outside. On the other hand, when the pitch data of the buffer 3C is set, the pitch counter 12 starts counting by the clock pulse φ1 applied via the AND circuit 21. However,
If the segment data currently stored in the segment ROM e is shorter than the pitch data set in the pitch counter I2, the end mark is read out from the segment ROM 6 to the end mark detection circuit 7 before l pitches are completed. The end mark detection circuit 7 outputs a signal φB. Therefore, the output of the inverter 1o becomes 10'', the gate of the AND circuit 11 is closed, the input of the clock pulse φ1 to the address color/reference circuit 5 is prohibited, and the count-up operation is stopped.

Furthermore, since the output of the inverter IO becomes 0, the gate of the AND circuit 8 is closed, and from then on, the elemental piece decoding and synthesis (
9) A value of "0" is input to path 4 as segment data. On the other hand, the pitch counter 12 continues to operate and clocks! <A count operation is performed every time the pulse φ1 is given. And the contents of Pitchkara/Ri 12 are “
0'', the zero detection circuit 14 outputs a signal φp.

is outputted and input to the set terminals of the address counter 5 and pitch color/receiver 12 via the AND circuit 15 and the OR circuit 18. Therefore, the address counter 5 is set again with the segment head address from the buffer 3b, and the pitch counter 12 is set with pitch data from the buffer 3C, so that the same audio waveform is generated from the beginning.

At the same time, the content of the repetition counter 19 is set to "-1" by the detection signal φpo of the zero detection circuit I4. Also, contrary to the above case, if the pitch is shorter than the elemental piece, the end is sent from the elemental piece ROM 6. Before the mark is read out, the content of the pitch counter 12 becomes "0" and the zero detection circuit 14
A detection signal φpO is output. This detection signal φpo
As described above, the address counter 5 is set to the top address of the piece of wood, the pitch counter 12 is set to pitch data, and the contents of the repeat I9 are r-rjed. The same operation is repeated thereafter, and when the decoding process for the designated piece of wood has been performed a designated number of times and the content of the repetition counter 19 becomes "0", the zero detection circuit 20
A detection signal φR is outputted from. The contents of the address counter 2 are counted and amplified by this detection signal φR, the next elemental piece control information is read out to the buffers 3a to 3e, and the next elemental piece decoding control is started.

On the other hand, in the case of speech synthesis using the waveform encoding method, the pitch data enriched in the buffer 3CK is "0" among the elemental piece control information read from the elemental piece system #几OMr. Furthermore, the segment head address written in the buffer 3b is an address that specifies the leading position of the area where the waveform encoding data of the segment OM6 is stored. When "0" is written as the backup JclC pitch data, the output of the zero detection circuit 13 becomes 1, the output of the inverter 16 becomes "0", and the gate of the AND circuit 15 is closed. Therefore, even if the zero detection circuit 14 detects the set content "0" of pitch force + 7y 12,
The detection signal φ1. . is blocked by the AND circuit 15.

Furthermore, when the output of the inverter 16 also becomes 0'', the output of the inverter 17 becomes 1 and is input to the AND circuit 9. In this state, the contents of the address counter 5b are counted up by the first member by the clock pulse φ1, and the One W
The memory contents of OM6 are andt! The signal is read out to the segment decoding/synthesizing circuit 4 via the 21 path 8. This segment decoding/synthesizing circuit 4 handles data read from the segment ROM 6 and the buffer 3a.
The audio is reproduced based on the amplitude value from the IJ/A conversion circuit 22 and output to the outside.

Thereafter, when the end mark is read from the segment ROM 6, a detection signal φE is outputted from the end mark detection circuit 7 and inputted to the AND circuit 9. At this time, the AND circuit 9 receives the ``l''l'' signal from the inverter 1XI7, so the end mark detection signal φE is output from the AND circuit #69 and sent to the set terminal of the address counter 5 via the OR circuit 18 Therefore, the segment start address held in the buffer 3b is set in the address counter 5. Also, at this time, the contents of the repetition counter 19 are incremented. It is repeated and when the content of the repetition counter 19 becomes "0", the zero detection circuit 20 also outputs zero detection No. 18 φR, and the address counter 2 is counted and amplified. Information is in buffer 3a
~3C, and the above-described operation is repeated.

When performing speech synthesis using the waveform encoding method as described above, pitch information is ignored and one segment is reproduced in its entirety until an end mark is detected.

〔Effect of the invention〕

As described above, according to the present invention, one LSI can be used for both the speech unit synthesis method and the waveform encoding method, and the memory can be shared by each synthesis method, so the circuit can be simplified. Its purpose in composition can be peracid. Furthermore, since two voice synthesis systems can be provided with one LSI and SL, the number of LSIs to be displayed is reduced, and manufacturing and management become easier.

[Brief explanation of the drawing]

The figure is a circuit configuration diagram showing an embodiment of the present invention. ! ... Elemental piece control ROM, 3a to 3e... Buffer,
4... Elemental piece decoding synthesis circuit, 6... Elemental piece RUM, 7.
...End mark detection circuit.

Claims (1)

[Claims] A wood block control ROM that stores segment control 1# information for a speech segment synthesis method and a drum-shaped encoding method, and a speech segment control ROM that stores speech segment control 1# information for a speech segment synthesis method and a drum-shaped encoding method. The segment kVJM is formed by storing speech segment data together with an end mark, and the segment R when the control information for burning the speech segment synthesis method is read from the wood segment control ROM.
A means for extracting the wood piece data from the OM until the specified pitch length or end mark is detected. If the control information related to the waveform encoding method is read from the elementary side (a4 RO~1), the pitch data is ignored,
Means for continuously outputting segment data from the segment ROM until the end mark is read, segment data to be piled from the upper segment OM, and control information from the segment control 11 OM. A speech synthesis device 0 characterized by comprising a segment decoding and synthesis circuit that decodes speech shaping according to the following.