JPS58217034A - デ−タ処理装置 - Google Patents

デ−タ処理装置

Info

Publication number
JPS58217034A
JPS58217034A JP10039882A JP10039882A JPS58217034A JP S58217034 A JPS58217034 A JP S58217034A JP 10039882 A JP10039882 A JP 10039882A JP 10039882 A JP10039882 A JP 10039882A JP S58217034 A JPS58217034 A JP S58217034A
Authority
JP
Japan
Prior art keywords
clock
data transfer
channel
input
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10039882A
Other languages
English (en)
Japanese (ja)
Other versions
JPS622351B2 (enrdf_load_stackoverflow
Inventor
Akinori Horikawa
堀川　顯憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10039882A priority Critical patent/JPS58217034A/ja
Publication of JPS58217034A publication Critical patent/JPS58217034A/ja
Publication of JPS622351B2 publication Critical patent/JPS622351B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP10039882A 1982-06-11 1982-06-11 デ−タ処理装置 Granted JPS58217034A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10039882A JPS58217034A (ja) 1982-06-11 1982-06-11 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10039882A JPS58217034A (ja) 1982-06-11 1982-06-11 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS58217034A true JPS58217034A (ja) 1983-12-16
JPS622351B2 JPS622351B2 (enrdf_load_stackoverflow) 1987-01-19

Family

ID=14272873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10039882A Granted JPS58217034A (ja) 1982-06-11 1982-06-11 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS58217034A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172359A (ja) * 1987-01-12 1988-07-16 Fujitsu Ltd 直接メモリアクセスシステム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63172359A (ja) * 1987-01-12 1988-07-16 Fujitsu Ltd 直接メモリアクセスシステム
US5016165A (en) * 1987-01-12 1991-05-14 Fujitsu Limited Direct memory access controlled system

Also Published As

Publication number Publication date
JPS622351B2 (enrdf_load_stackoverflow) 1987-01-19

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