JPS58215070A - Planar semiconductor device and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Brainer semiconductor device and a manufacturing method thereof.

[Technical background of the invention]

In a semiconductor device with a Brehner structure, for example a Brehner transistor, the pnn associated breakdown voltage is determined by the minimum radius of curvature of the edge of the redoped region, and therefore ultimately by the minimum radius of curvature of the limit of the interwall charge region. nru. The flatter the joint (7t) and the smaller the radius of curvature, the lower the breakdown voltage.

It is known that the breakdown voltage of such a pn ground can be increased by a so-called field plate. This is a metal body provided on the oxide in contact with one diffusion region and partially covering the edge of the oxide.

Such field plates require a considerable amount of area on the surface of the P4 device and are not recommended for use in some cases, such as integrated circuits, because they require This is because the area is the area that you want to use for printing.

West German Published Patent Publication DE-082944937 describes a shallow diffusion or ion implantation region and a high breakdown voltage? A brainer semiconductor device having the following characteristics is described. In this device, this high breakdown voltage is achieved by means of a protective ring placed at a distance from the pn junction as well as a thin film containing an insulating layer. This thin @ is semi-insulating,
It has at least two areas with precisely differentiated potentials. If the thin film is held at two different potentials, the space charge region becomes characterized by a large radius of curvature, which allows common semiconductor devices to have high breakdown voltages.

[Summary of the Invention] This invention does not use field sheet metal, that is, it is possible to calculate the breakdown voltage of pn retrofit in a simpler way than the % measurement area 1 out of 1 τ record field. This solves the problem of egg proliferation.

In this invention, dust having a conductive shape opposite to that of the substrate is placed on a semiconductor substrate, and is surrounded by another region of the same conductivity type in an annular manner to eliminate the doping impurity concentration in those regions. Lord 1
The above-mentioned problem can only be solved by lowering the territory and height of the enemy.

According to the present invention, it is possible to easily increase the failure voltage compared to the case where a field plate is used.

However, it is also possible to assemble the entire field plate of the invention in a suitable manner.

[Embodiments of the invention]

Examples will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a semiconductor substrate 4 of No.
31 of the conductivity type opposite to the conductivity type of the semiconductor body in the base body.
Direction areas 1, 2. ．． 3 is formed n. Semiconductor substrate 4 and area 1, 2.3 > yohi pnn finishing example 510
A window is provided in the region l of this loquat layer 5, and a Kankan six sword S is placed therein. Regions 3 and 2 are arranged in a ring surrounding region l, $;n.

The doping impurity concentration is low corresponding to the following equation.

NO<N3<N2<N1 It is desirable that all three regions have approximately the same depth X. That is, XI=X2=X3.

However, it is also possible to set the depth X to have the following relationship.

XI < X2 <
;+si −neutral 1 between the zones. Let the failure voltage be '[Jd, and the voltages UJ, U2 . U3:)
Ul) Let U2>U3. First, when the voltage U3 is applied to the electrode 6, the carriers in the region 3 with the doped impurity concentration N3 are cleaned, and then when the voltage U2 is applied, the carriers in the contacting region 2 with the doped impurity concentration N2 are removed. fL, below the failure voltage U (the voltage increases at i2 and becomes f'L).

Figures 2 and 3 show a state in which the space charge region expands depending on the pressure applied to the crucian carp. An increase in the breakdown voltage occurs because the wall-to-wall charge fragments that hold the bond in the cell shown in FIG.

The exemplary embodiment provides for three annular regions'; it is of course possible to have more.

The lateral Il@ of the annular region depends on the depth of the region, the doping concentration of the substrate and the number of regions, and may range from 5 to 20 μm. The individual regions may be made narrower as the number n increases.

The semiconductor device of the embodiment shown in FIGS. 1 to 3 is manufactured as follows.

For example, by using an ion implantation method, a dielectric region 3 is formed in the n-type half-2s body substrate 4 with a doped impurity concentration of No. using all the masks of corresponding dimensions. Area 2 was removed using a new mask with all openings.
, a region l is formed in the area 2 using the entire mask with the smallest opening. Is the conductivity type opposite to that of the substrate in this area? For example, it is produced by an ion implanter of boron ions. At the depth of the implantation and the degree of impurity concentration, the depth is always as large or small as that of region 3.
If you trace it so that it becomes as low as , it will be n. Following the application of the insulation N5, an opening is provided in the area of the region fl into which the gauntlet 6 is mounted. These methods are followed by conventional methods.

FIG. 4 shows the semiconductor device according to FIG. 1, which is equipped with the entire structure according to the invention, and further includes the entire field plate 7.

[Brief explanation of drawings]

1 to 243 are full cross-sectional views of a first example of the invention, and FIG. 4 is a cross-sectional view of a second embodiment of the invention. 4, ... 4 whole cows, 1, 2. ．． 3...Opposite a to the base
亙-type area, 5...Zetsu#, J Koji, 6...Denzan, 7...
・Field board.

Claims (3)

[Claims] (1) At least 11 pn junctions are present in a 14-electrode type semiconductor substrate, and an insulating layer is disposed on the conductive substrate, and a pn junction exposed on the surface of the semiconductor substrate is In a planar semiconductor device, a region of a conductivity type opposite to that of the substrate f'L disposed in a semiconductor substrate is annularly surrounded by one or more regions of a conductivity type opposite to that of the substrate; The doping impurity concentration is extremely low in the foreign region, which is a characteristic of Fullyna semiconductor devices. (2) The planar semiconductor device according to claim 1, wherein each region penetrates the semiconductor substrate to the same depth. (3) Minimum opening from mask with desired maximum island opening? Is it possible to use several different masks and sequentially implant ions of the same type so that the impurity doping concentration increases sequentially under the same conditions to form regions of conductivity type opposite to the substrate? A method for manufacturing a planar semiconductor device characterized by: