JPS58212227A - Amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain an amplifier circuit for operating dynamically, by operating the 1st and the 2nd transistors(TRs) as FFs and discharging one of the 1st and the 2nd nodes. CONSTITUTION:When the potential difference between digit lines 4,4' is large, if the potential difference between the nodes 2,3 exceeds a threshold voltage VTH of an MOS TR, one of a TRQ11 or Q9 is turned off. Since the potential of a gate electrode 3 of the TRQ11 is lower than that of the source electrode 2, the TRQ11 remains turned off, and since the gate electrode 2 of the TRQ9 has a potential difference in excess of the VTH to the source electrode 3, the TRQ9 is turnd on. As a result, charges of a gate electrode node 9 of a TRQ4 are discharged through the TRQ9 for turning off the TRQ4. On the other hand, since the TRQ11 is turned off, the charges of the node 8 are not dicharged for turning on the TRQ2.

Description

Detailed Description of the Invention The present invention relates to an insulated gate field effect transistor, mainly an MO8 field effect transistor (hereinafter referred to as MO8T).
The present invention relates to a circuit configured by the above, and particularly to a circuit that amplifies a minute difference signal and obtains a binary output.

Although the following explanation will be made using an N-channel MO8T, it is essentially the same for a P-channel MO8T or other insulated gate field effect transistors.

Dynamic memory using MO8T is required to have a high number of connections, and (7) MOS memory circuit input signals other than the clock signal are small compared to the MO8 level (12V). 0.4~2.4V)
Therefore, it is necessary to convert to MO8 level. On the other hand, as memory capacity increases, one-transistor memory cells with the smallest memory cell area are used, but when a one-transistor memory cell is read, the binary signal stored in that cell is read out. , Susuwa, "1", 鴴 information is 01~0.5V on the Desirat line.
Only a small degree of potential change occurs, and therefore an amplification circuit is required to amplify this minute signal.

Conventionally, a circuit shown in FIG. 1 has been used as a circuit for amplifying such a small signal. That is, the amplifier circuit 1 is composed of a flip-flop consisting of switching transistors Q1 and Q3 and load transistors Q and Q4. The flip-flop outputs 2 and 3 are connected to the memory circuit--digit line 4.4', respectively, and their load capacitances are made equal. When cell 5, which is one of the memory cells connected to digit line 4, is read out, memory cell 5' connected to digit line 4' is not read out, and instead, the memory cell 5' connected to digit line 4' is A reference potential intermediate between the cell information "'1" and "0" is generated on the digit line 4'. Conversely, when the cell 5' connected to the digit line 4' is read out, a reference potential is generated on the digit line 4 by the reference voltage generating circuit 6.

FIG. 2 shows the waveforms of both digit lines 4, 4'.

The operation of the circuit shown in FIG. 1 will be described below using the waveforms shown in the same figure.

Digit lines 4 and 4' are precharged to the same level by transistors Qs and Qa, respectively, by clocker 3 before time t1. The transistor Q7, to which a clock signal is applied to the gate, is used to improve the efficiency in which the digit lines 4 and 4' are at the same level, and the precharge lock signal G3 is lower than the precharged level. You don't need it if it's high enough. After the precharge is completed at time t1 and the clock 6 goes low, the address signal selects, for example, the address line 7 and goes high, and the information in the memory cell 5 is read out. When address line 7 becomes high level, charge is exchanged between digit line 4 and memory cell 5, and a change in potential appears on digit line 4 in accordance with cell information 61'', 60''.

On the other hand, the reference voltage generating circuit 6' gives the digit line 4' a potential intermediate between ``1'' and ``1''.As a result, 0.1 V is applied between the digit lines 4 and 4' before time 1.
A potential difference of approximately At time t3, the clock signal φ! When the amplifier circuit 1 is activated by the transistor Q8, the charges on the digit lines 4 and 4' are discharged through the transistors Ql and Qm, respectively. However, since there is a potential difference as described above, there is a difference in the on-resistance of the transistors Q1 to Q3. Now, if digit line 4 is higher, the resistance of transistor Q3 is smaller, so digit line 4
′ becomes a low level more quickly. As a result, the on-resistance of transistor Q becomes increasingly large, which slows down the potential drop of digit line 4 and amplifies the potential difference between the digit lines. As a result, the output node of the flip-flop 2.3
A large potential difference occurs between them at time t3. Therefore, at time t3, the clock signal is set to a high level, the digit line 4, which has once gone low, is set to a high level again by the load transistor Q, and the digit +134' can be kept at a low level.

Incidentally, although the clock signals -1 and -6 have been explained separately, it is possible to operate even if these signals are the same signal.

In the amplifier circuit of FIG. 1, a DC current always flows through the transistor Q1 or Q4 while the clock 6 is at a high level.

Therefore, providing such an amplifier circuit for each digit line consumes a large amount of power.

Furthermore, transistor Ql-Q8 and transistor QzeQ
It is also necessary to take a large ratio of the size of 4. These are major drawbacks of this amplifier circuit.

In addition, in this circuit example, it is also possible to make the common source connection point of transistors Q+ & Qa common to multiple amplifier circuits, and to use only one transistor Qs for activating the amplifier circuits for multiple amplifier circuits. be.

An object of the present invention is to provide an amplifier circuit with low power consumption.

Another object of the invention is to provide an amplifier circuit that performs dynamic operation.

Still another object of the present invention is to provide an amplifier circuit suitable for amplifying minute difference signals.

Another object of the present invention is to provide an amplifier circuit suitable as a sense amplifier for a memory circuit having a one-transistor memory cell as a memory element.

An amplifier circuit according to the invention includes first and second nodes, means for precharging said first and second nodes, and said first and second nodes.
a first load circuit controlled by the potential of the node;
A first series circuit of field effect transistors, and a second series circuit of a second load circuit and a second field effect transistor controlled by the potential of the second node □ point':, and means for connecting the gate of the first transistor to an intermediate connection point of the second series circuit; and means for connecting the gate of the second transistor to an intermediate connection point of the second series circuit; first and second nodes, means for precharging the first and second nodes, and a second series circuit connected to an intermediate connection point of the first node and the first series circuit; a third field effect transistor controlled by the potential of the intermediate node;
a fourth field effect transistor connected between the middle connection point of the series circuit and controlled by the potential of the middle connection point of the first series circuit; The present invention is characterized in that one of the first and second nodes is discharged by operating as a p-tub circuit.

More preferably, this amplifier circuit is used as a sense amplifier of a memory circuit using a one-transistor memory cell as a memory element.

According to the present invention, there is no direct current path in the amplifier circuit, so there is no power consumption, and dynamic operation is possible, so it is possible to create a regioreless circuit. 'The area occupied on the integrated circuit can be reduced.

Hereinafter, the present invention will be described in detail using examples in order to better understand the present invention.

The above-described insulated gate field effect transistor used in the present invention has a source, a drain, and a control, or gate, electrode, but the source electrode may be used as a drain electrode, or the drain electrode may be used as a source electrode. Even if it is used as , it is equivalent and does not limit the present invention.

FIG. 3 shows a reference example of the present invention, and parts equivalent to those in FIG. 1 are given the same reference numerals. 1 output 2 of the flip-flop constituted by transistors Q1 to Q4 is input to the gate of switching transistor Q9. The drain of transistor pQ9 is connected to power supply VD through load transistor QIO.
D and is also connected to the gate 9 of the transistor Q4. The other output 3 of the flip-flop becomes the gate input of the switching transistor Qu. transistor Q
The drain of ss is connected to the power supply VDD via the load transistor Q1m, and is also connected to the gate 8 of the transistor Q2. A precharge lock signal Da3 is applied to the gate of the load transistor Q1o*Qxt. Further, the sources of the transistors Qs+Qtl are commonly connected, and the transistor Ql1 has the clock signal φ4 applied to the gate.
It is grounded through 1.

Flip-flop 1j) The transistors Qa and Q4 are each connected to the power supply VDD via a transistor Qt4*Qts to which a clock signal G2 is applied to the gate. Pootstrap capacitors C1 and C2 are connected between the gate of transistor Q14 and node 8, and between the gate of transistor Qss and node 9, respectively.

The operation of the circuit shown in FIG. 3 will be explained using the operation waveforms shown in FIG. 4.

Before time t1, digit lines 4 and 4'9 nodes 8 and 91 nodes 2 and 3 are precharged to predetermined potentials, respectively, by clock signal 933. transistor Q,
As mentioned above, 10- is for making the precharge levels of nodes 2 and 3 more accurate, so that the parasitic capacitance of digit lines 4 and 4' can be configured to be equal, and the levels of nodes 2 and 3 are equal. Preferably unnecessary.

When a signal is applied to the address line at time t1 after the precharge lock signal 3 becomes low level, a cell signal is output to the digit lines 4 and 4'.

When the clock signal 1111 is set to high level at time t1 and the amplifier circuit 1' is activated, the digit line 4 is turned on by time t3.
4', that is, the potential difference between nodes 2 and 3 is amplified. This is similar to the circuit example shown in FIG. To make the following explanation easier to understand, it is assumed that digital #4 is higher than the potential of digital 4'. By raising the clock signal -4 to a high level from time t3, the precharged charges at nodes 8 and 9 can be discharged, but since the digit line 4' is at a low level, the transistor Q is in an OFF state. , the charge is not discharged at node 8 and remains at a high level. On the other hand, since the digit line 2 is at a high level, the transistor Qe is in the ON'' state, and the node 9
That evening, the load is discharged to a low level. As a result, transistor Q2 is turned on because its gate electrode 8 is at a high level, while transistor Q4 is turned off because its electrode 9 is at a low level. At that time t4, clock g3
By bringing Q2.2 high, digit line 4 is connected to transistor Q2.2. is charged through the Q eye, while the digit wire 4'
is not charged because the transistor Q4 is off, and is brought to the ground potential by the transistors Qs and Qs. The transistor Q2. thus charges the digit +1i14 #4'. By controlling the gate 1tU of Q4 with the digit line 4.4', the current flowing in the amplifier circuit 1' can be eliminated.

Here, the capacitors C1 and C raise the nodes 8 and 9 to a higher potential than the precharged potential by capacitive coupling, reduce the ON resistance of the transistors Qg and Q4, increase the charging speed, and further increase the charging potential. It exists for the purpose of obtaining a high value, and is not essential for operation. Also, as in the conventional example, the common source connection point of the transistor QhQ3 may be shared by a plurality of amplifier circuits.

FIG. 5 shows an example of a non-explosion surface, and the difference between this example and the example shown in FIG. It is a connected configuration, and the transistor Qls and clock signal 12+4 in FIG. 3 are unnecessary.

The operation of the circuit shown in FIG. 5 will be explained below using the waveforms shown in FIG.

Before time 11, the digit line 4°4' is set by the clocker 3.
, nodes 2, 3 and 8.9 are precharged to the same potential, and at time t1 digit lines 4, 4'
The cell information is read out in the same manner as in the circuit example shown in FIG.

To simplify the explanation, it is assumed that the digit line 4 is at a high potential. At time tl, the clock signal $1 becomes high level and this amplifier circuit is activated. Similar to the circuit example shown in FIG. 3, the potential of the digit lines 4 and 4' decreases, but the potential difference between them is greatly amplified. Here, both cylinder point 2,
When the potential difference between MO8T and MO8T exceeds the threshold voltage VTR of MO8T, one of transistors Q2 and ldQ is turned on. That is, the transistor Qn remains off because the gate electrode 3 is lower than the source electrode 2;
9 has a potential difference between the gate electrode 2 and the source electrode 3 that exceeds the VTR, and is turned on.

As a result, the charge at node 9 of the gate electrode of transistor Q4 is discharged through transistor Q9, and
is in the off state. On the other hand, transistor Q.

Since is in the off state, the charge at node 8 is not discharged,
Transistor Q is in the ON state. When the clock signal 6 is set to high level at time t3, the transistor Q14 becomes O.
The transistors Q14 and Q! are in the N state. Node 2 is charged through D, but since transistor Q4 is off, Node 3 is not charged and remains at a low level, so D
C There is no current path at all.

FIG. 7 is a circuit diagram showing another embodiment of the present invention, in which parts equivalent to those in FIG. 5 are designated by the same reference numerals.

Among the transistors forming the flip-flop, the load transistor Q2. The flip-flop activation clock signal G1 is applied to both sources of Q3, and the sources of switching transistors Q1 and Q314- are both grounded. The signal of input line (digit line) 4.4' is transmitted by transistor Qta+Qlt
are input to the gates of the transistors Qla +
The drain output of Qty is the output 3 of the flip-flop,
2 are connected to each other. Also Q16゜Ql? The sources of both are grounded. The input lines 4, 4' are further grounded through the transistor Q1s t Qti, and Q18#Q1
The outputs 3 and 2 of the flip-flops are input to the gates of .

The operation of the circuit shown in FIG. 7 will be explained using the imitation model shown in FIG.

By time t1, node 8.9 is precharged to the same potential by clock signal φ3. Since the clock signal f11 is at a low level and the node 8.9 is precharged and at a high level, the transistor Q=, Q4 is in the ON state and the node 2.3 is at the same low level as the clock signal goo. . At least human power 4,4', :□:1, If one of the signals has a potential exceeding the VTR of MO8'I'', then from time 1. When the clock signal G! changes to a high level, the node 2.3 becomes Trying to reach a high level.

However, if there is a slight potential difference between the inputs 4 and 4', the transistor Qllll p Ql? Since there is a difference in the ON resistance of the nodes 2 and 3, there is a difference in the speed at which the nodes 2 and 3 reach the high level.

If input 4 is at a higher level than input 4', node 2 will be higher than node 30 level, and transistor Q3 will become faster (
It becomes ON state. For this reason, the potential difference between nodes 2 and 3 increases further, and when the difference exceeds the VTR at time t2, transistor Q is turned on and the charge at node 9 begins to be discharged. On the other hand, transistor Qll is in an off state because its source potential is higher than its gate potential, and as a result, transistor Q! A difference occurs between the ON resistances of Q4 and Q4, and node 2 becomes a higher level, but node 9 is discharged and transistor Q4 is turned off, so that no current flows from clock signal φ to contact 3. Therefore, a signal obtained by amplifying the minute level difference between the inputs 4 and 4' is outputted to the flip-flop outputs 2 and 3.

1□ Here, as mentioned above, when both inputs 4 and 4' are at a high level, that is, at a level higher than the MO8T VTR, and for example, when the input 4 side is high, the output 2 of the flip-flop has a high level, and the output 3 has a high level. However, if a level higher than the VTR of MO8T is still applied to the input 4', the transistor Q17 will remain in the ON state, and therefore the charge at the node 2 will be transferred through the transistor Qsy. Therefore, the transistor Q1s with a high level applied to its gate forces the input 4 to be discharged.
' to a low level and cut off the above-mentioned discharge path. Therefore, in a circuit system in which inputs 4 and 4' both become low level from then on, transistor Qss $ Q
lll is unnecessary, and in the above example input 4' is V
Similarly, if TH is at a fairly low level, transistor Q18
゜Qss becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a sense amplifier section in a conventional memory circuit, FIG. 2 is an operating waveform diagram of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing a reference example of the present invention, and FIG. FIGS. 5 and 7 are circuit diagrams showing embodiments of the present invention, respectively. FIGS. 6 and 8 show operating waveform diagrams of the circuits shown in FIG. 17, respectively. In the figure, Ql, Q, s, Qs, and Qo are switching transistors s Qll Q41, Qto and Qll are load transistors, and 2 and 3 are flip-flop outputs. 18-

Claims (1)

[Claims] first and second nodes, means for precharging the first and second nodes, a first load circuit controlled by the potential of the first nodes, and a first field effect transistor. a second series circuit including a second load circuit and a second field effect transistor controlled by the potential of the second node; and a second series circuit including a gate of the first transistor. means for connecting to an intermediate connection point of the second
means for connecting the gate of the transistor to an intermediate connection point of the second series circuit; first and second nodes;
and means for precharging a second node connected to an intermediate connection point of the first node and the first series circuit;
The third voltage controlled by the potential at the intermediate connection point of the series circuit of
and a fourth field effect transistor connected between the second node and an intermediate connection point of the second series circuit and controlled by the potential of the intermediate connection point of the first series circuit. An amplifier circuit characterized in that the first and second transistors operate as a flip-flop circuit to discharge one of the first and second nodes.