JPH01233755A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance the resistance to a hot carrier by a method wherein a gate length of a bidirectional transistor is made at least twice that of an ordinary transistor which is used while a forward current flows between a source and a drain. CONSTITUTION:MOS transistors Q1, Q2 are ordinary transistors, with a standard gate length of 1.0mum, which is used while a forward current flows between a source and a drain, and constitute a first circuit 1. A MOS transistor Q3 is used while a forward and reverse current i1 flows between a source and a drain; it is a bidirectional transistor with a gate length of at least 2.0mum and constitutes a second circuit 2. When the gate length is made longer in this manner, it is possible to enhance the resistance to a hot carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device configured with MOS type transistors.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit device has been manufactured by, for example, IEE Transaction On Electron Devices (IE
EE Transactionon Devices)
, August 1980, Volume ED-27.

As described on pages 1359-1367 etc., LD
There is a method using D, DDD structure.

However, problems remain if such measures are taken only from a process perspective, and measures from a circuit perspective are also required.

As a circuit countermeasure, for the inverter circuit shown in Fig. 4 <a), as shown in Fig. 4 (b), normally-on type MOS transistor (addition of Lo or clock type CM
O3 circuit has been announced. (For example, IEEE International Solid State Circuit Conference Digest on Technical Papers)
Solid-StateCr1rcuits Co
nference, Digest of Tech
nical Papers), February 1985, 2
(See pages 56-257) However, as shown in FIG.

No measures have been taken for the MOS type transistor Qlt whose drain terminal is not fixed and the channel current i1 flows in both directions, and other MOS type transistors Q1. It was formed with the same dimensions and structure as Q2.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the transistor Q11 in which the channel current i1 flows in both directions is different from the transistor Q1. Since it has the same dimensions and structure as Q2, etc., when voltage stress is applied to the transistor, as shown in Figure 6, before voltage stress application (PR
E-STRESS> and when a current is passed in the forward direction to the source train after voltage stress is applied (POST-
5TRESS NORMAL) and when the current is passed in the reverse direction (POST-8TRESS REVER5E), the drain current differs greatly (Reference: IEEE Electron Device Letters (IEEE E
LECTRON DEVICE LETTERS),
1986.

(See Vol. ED-7, No. 7, pp. 451-453) There is a problem in that it is greatly affected by voltage stress and deteriorates circuit characteristics.

An object of the present invention is to provide a semi-integrated circuit GI device that can improve hot carrier resistance for bidirectional transistors and prevent deterioration of circuit characteristics.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention is used by flowing a current in the forward direction between the source and the drain, and has a first circuit configured of a normal transistor having a predetermined gate length, and a connection to the first circuit. and a second circuit configured with a bidirectional transistor that is used by passing current between the source and drain in the forward and reverse directions and has a gate length at least twice that of the normal transistor. are doing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is an example in which the present invention is applied to a precharge section of digit lines D1*D2 of a memory cell array.

MOS type transistor Q1. Q2 is a normal transistor having a standard gate length of 1.0 μm and is used by passing a current in the forward direction between the source and drain, and forms the first circuit 1.

The MOS transistor Q3 is a bidirectional transistor that is used by passing forward and reverse currents 11 between the source and the train, has a gate length of at least 2.0 μm, and forms the second circuit 2. are doing.

Note that even if the gate length of transistor Q3 is increased, transistor Q3 is different from other transistors Q1. The size of each part has been adjusted so that the capacity is almost the same as the Q2, but there is no change in the manufacturing process.

In this way, by increasing the gate length, hot carrier resistance can be improved.

That is, the deterioration of a transistor due to hot carriers is faster as the substrate current per unit area is larger. Therefore, reducing this substrate current improves hot carrier resistance.

Therefore, the inventors conducted repeated research and investigated various gate lengths in the same process, and as a result, as shown in Figure 2, they concluded that the longer the gate length, the smaller the substrate current becomes. applied to.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

P-type transistor Q4 of the first circuit LA, IB. Q8
The gate length is 1.2 μm, and the N-type transistor Q5. Q
9 has a gate length of 1.0 μm, whereas the gate length of the P-type transistor Q6 of the bidirectional second circuit 2A constituting the transfer gate is 2.4 μm.
The gate length of the m, N type transistor Q7 is formed to be 2.0 μm.

〔Effect of the invention〕

As explained above, in the present invention, the gate length of a bidirectional transistor, which is used by passing forward and reverse currents between the source and drain, is changed by using the gate length of a bidirectional transistor, which is used by passing forward currents between the source and drain. By configuring the gate length to be at least twice the gate length of a normal transistor, hot carrier resistance can be improved for a bidirectional transistor, and deterioration of circuit characteristics can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a characteristic diagram of substrate current versus gate length for explaining the present invention in detail, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. A circuit diagram showing an example, FIGS. 4(a) and 4(b) are respectively circuit diagrams for explaining an example of measures to prevent characteristic deterioration caused by hot carriers in a conventional semiconductor integrated circuit device, and FIG. FIG. 6 is a circuit diagram showing an example of a circuit using a bidirectional transistor of a circuit device. FIG. 6 is a characteristic diagram of drain current versus drain voltage for explaining characteristic deterioration of a conventional bidirectional transistor. 1, LA, 1.8...first circuit, 2.2A...second circuit, ■1...inverter, Q1-Q11...
transistor.

Claims (1)

[Claims] Used by passing current in the forward direction between the source and drain,
A first circuit constituted by an ordinary transistor having a predetermined gate length, and a circuit connected to this first circuit to allow current to flow in the forward and reverse directions between the source and the tray, 1. A semiconductor integrated circuit device comprising: a second circuit constituted by a bidirectional transistor having a gate length at least twice that of the second circuit.