JPH0722516A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the speed without enlarging the area of layout by forming metal wiring for input signals through insulation film on a gate electrode. CONSTITUTION:Connections to the source and drain of a MOSFET are made by the wiring layer M1 of a first layer, and wiring for input signal is formed on a gate electrode by using a wiring layer M2 of a second layer. By doing this, respective wiring layers M1 and M2 can be formed in response to the sizes of the source, drain region and gate electrode, thereby reducing effective resistance values. And the input signal supplied to the gate electrode of the MOSFET is input from both the end sides through the wiring layer M2 of the second layer having a small resistance value formed on said electrode, so that the resistance value of equivalent gate electrode can be greatly reduced, by which the switching characteristics can be improved. Also, a wiring layer M3 for input can be formed on the gate electrode so that the cell size in lateral direction can be reduced and the area of layout can be decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when used in a device formed by a MOSFET (insulated gate type field effect transistor).

[0002]

2. Description of the Related Art In a MOSFET, as the channel length (L) becomes shorter or the channel width (W) becomes larger, the influence of the resistance value at the gate electrode cannot be ignored and the switch characteristics deteriorate. Therefore, as shown in FIG. 5, the input signal IN is supplied from both ends of the gate electrode of the MOSFET to reduce the influence of the gate resistance value.

[0003]

In a circuit for supplying an input signal from both ends of the gate electrode of a MOSFET by using a metal wiring having a two-layer structure as described above, a signal line for extracting an output signal from the MOSFET and a power supply voltage are used. In order to avoid the intersection with the wiring for supplying the electric field, it is necessary to lay out the wiring such as bypassing the source / drain diffusion layer as shown by the dotted line in FIG. 5, and the layout area increases. Occurs.

An object of the present invention is to provide a semiconductor integrated circuit device which realizes high speed operation and high integration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the channel length is shortened,
Or MOSFET with a long channel width
A metal wiring layer is formed above the gate electrode via an insulating film, and an input signal is supplied from at least both ends of the gate electrode.

[0006]

According to the above means, since the metal wiring for the input signal is formed on the gate electrode, the speed can be increased without increasing the layout area.

[0007]

1 is a layout diagram of an embodiment of a logic gate circuit mounted on a semiconductor integrated circuit device according to the present invention. In the figure, CMOS (complementary MO
A NAND gate circuit of S) configuration is shown as a representative. The circuit shown in the figure is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, the circuit is constituted by a metal wiring layer having a three-layer structure composed of M1 to M3. Although not particularly limited, the first metal wiring layer M1 is formed mainly of tungsten, and the second and third metal wiring layers M2 and M3 are formed mainly of aluminum.

In the figure, two P-channel MOSFETs are provided in the upper half with two input signal lines consisting of a third wiring layer M3 extending laterally in the central portion sandwiched therebetween.
(PMOS) are arranged in parallel. That is, the diffusion layer L provided at the center is used as a common source region, and the diffusion layers L as drain regions are formed on both sides of the diffusion layer L with the gate electrode made of the polysilicon layer FG sandwiched therebetween. The power supply voltage VCC is supplied to the source region by the first wiring layer M1. The other end of the wiring layer M1 connected to the source region is connected to the second wiring layer M2 through the first through hole TH1 and the third layer through the second through hole TH2. Is connected to the wiring layer M3. Although omitted in the figure, the third wiring layer M3 is extended as a supply line of the power supply voltage VCC. The drains of the two MOSFETs are contact LCNT
Are connected to each other via the first wiring layer M1.

A second wiring layer M2 is formed along the gate electrode formed of two polysilicon layers FG corresponding to the two P-channel MOSFETs, with an insulating film interposed therebetween. . The FG forming the gate electrode is connected to the first wiring layer M1 by the contact FCNT, and is connected to the second wiring layer M2 by the first through hole TH1 with the wiring layer M1 interposed. .

Two N-channel MOSFETs (NMOS) are provided in the lower half with two input signal lines consisting of a third wiring layer M3 extending laterally in the central portion sandwiched therebetween.
Are connected in series. That is, the diffusion layer provided in the center is used as a common source / drain region, and the drain and the source are formed on both sides thereof with the gate electrode made of the polysilicon layer FG interposed therebetween. 2 in series
Of the two N-channel type MOSFETs, the source region of the MOSFET arranged on the left side has a contact LCNT.
Is connected to the wiring layer M1 of the first layer, and the other end side is connected to the ground potential VSS of the circuit. M placed on the right
The drain region of the OSFET is the P-channel type M via the contact LCNT by the first wiring layer M1.
It is connected to the drain of the OSFET. These output nodes are transmitted to the inputs of the next-stage circuit (not shown).

When transmitting to the next-stage circuit using the third wiring layer M3 in the same manner as described above, the third wiring layer M3 is interposed with the second wiring layer M2 interposed. Connected to. Although not particularly limited, the next-stage circuit is the above-mentioned MOSF.
When it is arranged very close to ET, it extends as it is to the gate of the next-stage MOSFET by the first wiring layer M1, and signals are supplied from both ends of the gate electrode by the second wiring layer M2. You may do it.

In this embodiment, the first wiring layer M
1, the source and drain of the MOSFET are connected, and the wiring for the input signal is formed on the gate electrode by using the second wiring layer M2. In this configuration, it is not necessary to provide a max alignment margin between the first and second wiring layers M1 and M2, and each wiring layer is made to correspond to the size of the source / drain region and the gate electrode as shown in FIG. M1, M
2 can be formed, and its effective resistance value can be reduced.

Since the input signal supplied to the gate electrode of the MOSFET is input from both ends via the second wiring layer M2 having a small resistance value formed thereon, an equivalent gate is provided. The resistance value of the electrode can be significantly reduced, the switching characteristics can be improved, and the wiring layer M3 for input can be formed on the gate electrode, so that the cell size in the lateral direction can be reduced, thereby reducing the layout area. You can

FIG. 2 is a layout diagram of another embodiment of the logic gate circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, when the NAND gate circuit as shown in FIG. 1 is formed, the first polysilicon layer F is formed in order to reduce the cell size in the vertical direction.
A contact portion for connecting the gate electrode made of G and the second metal wiring layer is formed by bending in the channel length direction. By doing so, in FIG. 1, the contact hole FG and the through hole TH1 which are arranged side by side in the vertical direction in the central portion of the P channel type MO.
Like the upper side of the SFET and the lower side of the N-channel MOSFET, they are arranged in the lateral direction. Therefore, the cell size in the vertical direction can be reduced. The other configuration is similar to that of FIG. 1, and thus its description is omitted.

FIG. 3 is a sectional view of the element structure of an embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the element structure of the array section and the indirect peripheral section in the dynamic RAM in which the logic gate circuit as described above is mounted is exemplarily shown as a representative.

The storage capacitor of the memory cell uses the second polysilicon layer SG as a storage node and is connected to one of the source and drain of the address selecting MOSFET. The second polysilicon layer has a fin structure and is composed of a plate electrode made of a third polysilicon layer TG with a thin gate insulating film interposed therebetween. The gate of the address selecting MOSFET is composed of the first polysilicon layer FG. The other source and drain of the address selection MOSFET are connected to the first wiring layer M1 with the FG, SG and TG interposed therebetween. The wiring layer M1 constitutes a bit line (or a data line or a digit line).

Two N-channel type Ms are provided in the indirect peripheral portion.
The OSFET is formed. The first wiring layer M1 is
The contact LCNT is connected to the source and drain of the MOSFET. Alternatively, the first layer polysilicon FG
And are connected by a contact FCNT. The first wiring layer M1 and the second wiring layer M2 are connected via a first through hole TH1, and the second wiring layer M2 and the third wiring layer M3 are connected to each other. It is connected through the two through holes TH2.

When an input signal is supplied to both ends of the gate electrode of the MOSFET by the second wiring layer M2 as described above, the dummy first layer is formed via the first through hole TH1 as described above. Drop it on the wiring layer M1
It is connected to the first-layer polysilicon FG as a gate electrode via the wiring layer M1 of the first layer and the contact LCNT.

Third wiring layer M3 for supplying an input signal
Is connected to the second wiring layer M2 via the second through hole TH2. For example, when the output signal is supplied to the circuit of the next stage, the first wiring layer M1 is a dummy second wiring layer M2 via the first through hole TH1.
And is guided to the third wiring layer M3 through the second through hole TH2 with the wiring layer M2 interposed.

FIG. 4 shows an MO for explaining the present invention.
An operating characteristic diagram of the SFET is shown. In the figure, one end side (One en
When the input signal is supplied from d), the gate width and delay time when the input signal is supplied from both ends are shown. The figure is obtained by a circuit modeled by computer simulation, and as is clear from the figure, it is understood that by supplying the input signals on both ends of the MOSFET, the switch characteristics are significantly improved. it can.

The operational effects obtained from the above embodiment are as follows. That is, (1) a metal wiring layer is formed on an upper portion of a gate electrode of a MOSFET having a short channel length or a long channel width via an insulating film, and at least both ends of the gate electrode are formed. By supplying the input signal from the side, it is possible to obtain an effect that the speed can be increased without increasing the layout area.

(2) The second metal wiring layer is formed along the gate electrode of the MOSFET,
By using the wiring layer of the first layer as the wiring layer connected to the source and drain of the MOSFET, it is not necessary to provide a mask alignment margin between the two, and the effective wiring layer of the metal formed on the gate electrode can be obtained. It is possible to obtain the effect that the resistance value can be reduced.

(3) The gate electrode and the second wiring layer are M-shaped at least at one end of the gate electrode.
By bending the OSFET in the channel length direction and providing the contact portion with the first wiring layer interposed therein, the cell size in the channel width direction can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, a MOSFET having a short channel length or a long channel width is not limited to the one that constitutes the NAND gate circuit as in the above-described embodiment, but also one that constitutes an inverter circuit or a NOR gate circuit. It can be used for those requiring switch operation. The wiring layer may be configured by interchanging the second layer M2 and the third layer M3. INDUSTRIAL APPLICABILITY The present invention can be widely used for semiconductor integrated circuit devices configured by using MOSFETs.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the channel length is shortened,
Or MOSFET with a long channel width
By forming a metal wiring layer along the gate electrode of the gate electrode via an insulating film and supplying an input signal from at least both ends of the gate electrode, it is possible to increase the speed without increasing the layout area. Become.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an embodiment of a logic gate circuit mounted on a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a layout diagram showing another embodiment of the logic gate circuit mounted on the semiconductor integrated circuit device according to the present invention.

FIG. 3 is a sectional view of an element structure showing an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 4 is an operational characteristic diagram of a MOSFET for explaining the present invention.

FIG. 5 is a schematic layout diagram for explaining an example of a conventional technique.

[Explanation of symbols]

M1 ... Wiring layer of first layer, M2 ... Wiring layer of second layer, M
3 ... Third wiring layer, TH1, TH2 ... through hole, LCNT, FCNT ... contact, PMOS ... P-channel MOSFET, NMOS ... N-channel M
OSFET, FG ... First layer polysilicon (gate electrode), SG ... Second layer polysilicon (storage node), TG ... Third layer polysilicon (plate), W ... Channel width.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/8242 27/108 7210-4M H01L 27/10 325 P (72) Inventor Hidetoshi Iwai Tokyo 2326 Imai, Ome City, Hitachi, Ltd. Device Development Center (72) Inventor Katsuo Komatsuzaki 2350 Kihara, Miuramura, Inashiki-gun, Ibaraki Prefecture Japan Texas Instruments Co., Ltd.

Claims (3)

[Claims] 1. A MOSFET having a short channel length or a long channel width, comprising:
A semiconductor integrated circuit device characterized in that a metal wiring layer is formed on the gate electrode of an SFET via an insulating film thereabove and an input signal is supplied from at least both ends of the gate electrode. 2. The semiconductor integrated circuit device has three metal wiring layers, wherein a wiring layer corresponding to an output node of a MOSFET is formed by a first wiring layer and a second wiring layer is formed by the above wiring layer. The wiring for supplying an input signal, which is formed along the gate electrode, is supplied, and a relatively long signal wiring for input or output is constituted by the third wiring layer. Semiconductor integrated circuit device. 3. The gate electrode and the second wiring layer are MOS transistors at least at one end of the gate electrode.
3. The semiconductor integrated circuit device according to claim 2, wherein the FET is bent in the channel length direction, a contact portion is provided there, and the FET wiring layer is connected via the first wiring layer.