JPS62117189A - Memory cell - Google Patents

Abstract

PURPOSE:To reduce an area occupied by a memory cell by connecting a drain and the gate of a P-channel and a N-channel MOSFETs, and connecting the P-channel and the N-channel MOSFETs controlled with word wires between each connecting point and a pair of bit wires. CONSTITUTION:The titled device is constituted with two P-channel MOSFETs 5 and 6, and two N-channel MOSFETs 7 and 8. The source of the P-channel MOSFET5 is connected to a power source VDD, and the gate to the drains of the N-channel MOSFETs 7 and 8. Also, the source of the N-channel MOSFET 7 is connected to an earth VSS, and the gate to the drains of the MOSFETs 5 and 6. Meanwhile, the source of the N-channel MOSFET8, the drain used in common with the drain of the N-channel MOSFET7 is connected to a bit wire BL, and the gate to the word wire W. Furthermore,the source of the P- channel MOSFET6, the drain used in common with the drain of the P-channel MOSFET5 is connected to a bit wire, the inverse of BL, and the gate to the word wire, the inverse of W.

Description

DETAILED DESCRIPTION OF THE INVENTION A) Industrial Application Field The present invention relates to a memory cell used in a RAM (Random Access Memory) formed inside a gate array, and particularly to a memory cell that constitutes a basic cell of the gate array. MOS
The present invention relates to a memory cell formed by combining FETs.

(1. Conventional technology) In recent years, basic chips have been created in which a large number of basic cells each consisting of multiple MOSFETs are arranged, and the MOSFETs of each cell are arranged based on the user's request, and aluminum wiring is formed using a 1A pattern mask to form the desired circuit. A large number of gate arrays have been developed that can be used as gate arrays.In addition, as gate arrays become more highly integrated, there are composite gate arrays in which ROM, RAM, PLA, etc. are combined with gate arrays on one chip, and MOS as the basic cell of gate arrays. KAM can be freely placed anywhere on the chip by combining FETs.
A gate array has been created that can create .

Conventionally, gate arrays for making RAM by combining MOSFETs of basic cells have used memory cells having the configuration as shown in FIGS. 6 and 7 on page 120 of Nikkei Electronics, published on February 28, 1981. It is being FIG. 3 shows a circuit diagram of the memory cell.

In FIG. 3, the memory cell is connected to a CMOS inverter +11 (t21) whose input and output are connected to each other, and a connection point between the bit line BL and the CMOS ear (9 (fllf21)) (
It consists of a MOSFET Ti31 provided between the bit line tile and the CMOS inverter tll+21, and a MOSFET (41) provided between the bit line tile and the CMOS inverter tll+21 (bl).

The CMOS inverter fi+ +21 is composed of P-channel inter-channel O5FETs (!), each of which constitutes a basic cell of the gate array.
: Two N-channel MOSFETs are connected in series and T is used.

(/2) Problems to be Solved by the Invention However, since the memory cell shown in FIG. Therefore, one memory cell requires a plurality of basic cells, which increases the occupied area.

2) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and it connects the gate and drain of each of the P-channel O5FET and N-channel MOSFET (7) that constitute the basic cell. (-1 Between the connection point and the bit line BL support BL, the P channel O5F controlled by the word lines W and W, respectively)
This is a memory cell configured by connecting ET and N-channel) vloSFET.

Q) Effect: According to the above-mentioned means, the memory cell consists of four MOSFEs.
Since it is composed of T, O5FET between two P channels
One memory cell can be formed by one basic cell composed of a 2m N++:z channel Mo SFET. Additionally, this memory cell is a P-channel O5FET.
W Hs level, N-channel MOSFET at the gate of
For information where "L# level is applied to the gate of
Information is retained by charges accumulated in the gate capacitance and junction capacitance, and in the opposite case, information is retained by static operation, and is used as a memory cell in dynamic memory (D-RAM). It will be done.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which the memory cell consists of two P-channel MOS FET+51+
61 and two N-channel MOS FET (71
(The Bl type is connected to the power supply ■R, and the gate is connected to the drain of the N-channel MOS FET71f81.The source of the N-channel MOSFET (71) is connected to the ground Vss, and the gate is connected to the P-channel O
5FET +51 (connected to the drain of 61. On the other hand, N-channel MO8FET (N-channel MOSFET whose drain is shared with the drain of 71 (the source of 81 is connected to the bit line BL, and the gate is connected to the word line W) .Furthermore, P channel MOS FET (5
O between P channels that share the drain and drain of 1
5FET (the source of 51 is connected to the bit line BL.

The gate is connected to word line W.

In the memory cell shown in FIG.
When the word line W becomes "H" level and the word line W becomes "L" level, N
Channel MOS FET (81 to P channel MO
S F E T+61 is turned on, the node (Al) and the bit line BL are connected, and the node fBl and the bit line ■1 are connected.At this time, when the bit line BL is at the 1L'' level and the bit line BL is at the 1LHl level. , P channel MO
S F E T+51 and N-channel MOSFET+
71 are both turned on, and the contact (to the contact) is pulled down to the SS level, and the contact fBl is pulled up to the power supply VDD, so the P channel MOS FET ((31 and N channel MOS On the other hand, when P-channel MOSFET (61) and N-channel MOSFET (81) are turned on, the bit line BL becomes 1.
When H' level and bit line BL become @L level, P channel MOS FETf51 and N channel MO
S FET (both 71 are off, but P channel MOSFET + 51 gate 8 stitch and N channel MOSFET
The junction capacitance of the drain region of S F E T+71 (81 is charged with a charge of "H' L//
The junction capacitance in the drain region B of O5FE T+51+61 is charged with "L# level charge, and the P-channel MO
Even if the SFET (6) and the N-channel MOSFET+81 are turned off, this state is maintained for a while, but it is necessary to refresh it periodically. Therefore, the first
The memory cell shown in the figure is a dynamic type memory cell.

FIG. 2 is a wiring pattern diagram for forming the memory cell of FIG. 1 using basic cells of a gate array.

The basic cell has a gate electrode +9 made of polysilicon.
P-type source region (111+1
P-channel MOSFET Q+, Qz formed by providing 21 and drain region l, and a gate electrode iQ41 similarly formed of polysilicon.
It is composed of N-channel inter-channel O5FETQs and Q4 formed by providing an N+W source region αθαT and drain region (18) with u51 as an ask. In this basic cell, the gate electrode (
9) and the drain region αe, and the gate electrode 0S and the drain region (13) are connected by the first layer aluminum wiring 09■.
and the source region (17+) is connected to the first layer aluminum wiring t21+
So connect it. Further, the word lines W and the aluminum wires forming the W are connected to the gate arrays 141 (1011), and the source region openings Z (161 are each drawn out to both sides by aluminum wire supports). Next, (supports) of the bit line BL and the first aluminum wiring of the second IP are provided through the insulating film, and each source region +1
Aluminum wireman connected to 2 weak) connected to vice.

By connecting each element using the first layer and second ft1j aluminum wiring in this manner, the memory cell shown in the circuit diagram shown in FIG. 1 is formed. Note that since the memory cell is a dynamic type, the ends of each bit line BL and BL are connected to a sense amplifier, and this sense amplifier connects the O5FET between the P channels and the N channel M of the basic cell.
A well-known sense amplifier circuit is formed by a combination of OSFETs. Further, the wiring pattern shown in FIG. 2 is an example, and the wiring pattern is not limited to the pattern shown in FIG. 2 as long as it is a pattern for forming the circuit shown in FIG. 1.

(g) Effects of the invention As mentioned above, according to the present invention Φ, the memory cell has four M
Since it can be formed using an OSFET, one memory cell can be formed from one basic cell, which has the advantage of reducing the area occupied by the memory cell. Therefore, it becomes possible to form a large capacity D-RAM in any part of the gate array, which improves the functionality of the gate array.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a pattern diagram of the memory cell shown in FIG. 1, and FIG. 5 is a circuit diagram showing a conventional example. 15+ +61...P channel MOS FET,
(71+81...N channel 7 channel MOSFET, +91
(10) (141 (151-...gate electrode, tll
] u2 (IE (171... source area, 131
(181...Drain region. (1,91-(support)...Aluminum wiring.

Claims (1)

[Claims] 1. In a memory cell formed by combining a plurality of P-channel MOSFETs and a plurality of N-channel MOSFETs constituting a basic cell of a gate array, each drain and gate of the P-channel MOSFET and N-channel MOSFET are connected to each other, A memory cell characterized in that a P-channel MOSFET and an N-channel MOSFET controlled by a word line are connected between each of the connection points and a pair of bit lines.