JPS58210717A - Voltage controlled oscillator circuit - Google Patents

Abstract

PURPOSE:To eliminate the risk of a latch-up state by charging two capacitors through FETs by a current source. CONSTITUTION:When the output of an NOR gate 41 is at a logical level ''1'' and the output of an NOR gate 42 at a logical level ''0'', FETs 21 and 32 turn on and FETs 22 and 31 turn off; and a capacitor C52 contains no charge and a C51 is charged by the current source 11 through the FET21. Then once the capacitor is charged until the drain voltage of the FET31 exceeds the threshold voltage level of the NOR gate 41, the output of the NOR gate 41 is ''0'' and the output of the gate 42 is ''1''. Then, the FETs 22 and 32 turn off and the FETs 21 and 32 turn off. At this time, the C51 is discharged through the FET31 and the C52 is charged by the current source 11 through the FET22. Once the drain of the FET32 exceeds the threshold voltage V of the gate 42, the output of the gate 42 is ''0'' and the output of the gate 41 is ''1'', which is the last state. The C51 and C52 are charged and discharged repeatedly, but a potential lower than the ground level is not generated in the circuit, and there is no risk of the latch-up state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage controlled oscillation circuit using CMOS, which is intended to prevent latch-up when applied to an integrated circuit.

<Prior Art> As a conventionally used voltage controlled oscillation circuit, the circuit shown in FIG. 1 is well known. In Figure 1, NOR gate 4
1 and the NOR gate 42 constitute a set/reset flip-flop. Now suppose that the output of the NOR gate 41 is at logic level @l#, and the output of the NOR gate 42 is 64.
When M level is “0”, P channel MO8FET21,
N channel 5iosFFiT32 is ON, P channel M
O8FET22 and N-channel MO8FET31 are OFF
It has become.

Therefore, the current of the voltage controlled constant current source 11 flows from the voltage terminal 61 to the capacitor 51 through the FET 21.
Charge this. Furthermore, since the FET 32 is turned on, the input terminal of the NOR gate 42 is at ground potential.

When the input of the NOR gate 41 becomes 11" due to charging of the capacitor 51, its output becomes "O". At this time, NO
Since both R gate 420 inputs are "0", its output is @1". Therefore, P channel MO8FET22,
N-channel MO8FET31 is ON, P-channel MO8
F'ET 21, N-channel MO8FET32 is OF
It becomes F. Since the N-channel MO8FET31 is turned on, the drain L@0 of the N-channel MO8F'ET31 is turned on.
``Then, the capacitor 51 is charged from the constant current source 11 through the P-channel MO8FET 22. When the source of the P-channel MO8FET 22 becomes 11# due to this charging, the output of the NOR gate 42 is inverted and becomes @0'', and the NOR The output of gate 41 becomes @1#.

In this operation, the time T from when the P-channel MO8FET 21 or U22 is turned on until the NOR gates 41 and 42 are inverted is as follows.

If the threshold voltage of NOROR141, 42 is V, then
Conden at that time? 51 becomes Q=CV, and if the current of the constant current source 11 is 1, then Q=IT, so ev T=- (2). Therefore, the NORORs 141 and 42 will repeat the inversion again at a time T after the NOROR 1441't 42 is inverted. As can be seen from the above formula, time T
is a function of the current, and the inversion is returned, that is, the frequency of oscillation is controlled by the current. This electrical current is controlled by the applied voltage.

However, the conventional circuit is Nf Yarnel MOS FET.
Since the impedance of the current source 11 is very high compared to the ON resistance of the circuits 31 and 32, there is a drawback that a potential below the ground potential is generated in the circuit during switching, causing latch-up.

For example, N-channel MO8FET32 and P-channel MO8FET21 are 0N1N-channel MO8FET31.
, the charging of the capacitor 51 reaches the threshold value of the NOR gate 41 when the P-channel MO8FET 22 is OFF.
When the voltage reaches V, FETs 32 and 21 turn off,
FET31.22 is turned ON. At this time, N channel MO
The ON resistance of 8IT31 is t1 so 0 compared to the output impedance of current source 11, and the output impedance of current source 11 is considered to be infinite, so the drain of FET31 is ground potential (OV), and the drain of FET32 is -vCv] becomes. When this circuit is used in a CMO8 integrated circuit as described above, there is a problem that a portion below the ground potential is generated, and there is a risk that latch-up may occur using this as a trigger.

<Summary of the Invention> An object of the present invention is to provide a voltage controlled oscillator circuit that does not generate a potential below the ground potential within the circuit and is therefore free from the risk of latch-up.

According to this invention, one end of the constant current source controlled by voltage is connected to the power supply terminal, and the other end is connected to the first terminal. 2nd P channel/
The source of the I/MO8FET is connected, and the drain of the first P-channel MO8FET is connected to the drain of the k41ON channel MO8FET, one end of the first capacitor, and the reset terminal of the set-reset flip 70 tube. When the reset terminal of this 7-lip 70 tube is at a high logic level and the set terminal is at a low logic level, the first output terminal becomes a low logic level, the second output terminal becomes a high logic level, and the reset terminal becomes a low logic level. When the set terminal is at a high logic level, the output terminal of h31 is at a high logic level, and the second output terminal is at a low logic level. The second output terminal of this flip-flop is connected to the gate of the first N-channel MO8FET and the 10th P
It is connected to the gate of channel MO8FET. The drain of the second P-channel MO8FET is connected to the drain of the second N-channel MO8FET, one end of the second capacitor, and the set terminal of the set-reset flip-flop. and the gate of the @20P channel MO8FET are connected to the first output terminal of the set-reset flip-flop. Said 1st. the source of the second N-channel MO8FET; The other ends of the second capacitors are each grounded.

Embodiment> This invention will be briefly explained with reference to the embodiment shown in FIG. One end of the current source 11 is connected to the electric terminal 61,
The other end is a P channel MO8FE T21.

Connected to 22 sources. P channel MO8FE'r
The drains of 21 and 22 are N-channel MO8FETs 31.
32, and is connected to the reset terminal and set terminal of a set-reset flip-flop composed of NOR (NOR) 41 and 42, respectively, and is further connected to a capacitor 5.
Connected to one end of 1.52. N-channel MO8FET
The sources of 31 and 32 and the other ends of capacitors 51 and 52 are respectively grounded, and the outputs of 41 and 42 are FE
T22.32 is connected to each gate of FET21 and FET31.

Now, the output of NOR) 41 is at logic level @1#, N
If the output of OR gate 42 is at logic level @0#, FET21.32 is ON, FET22.31
is off, the charge on the capacitor 52 is zero, and the capacitor 51 is supplied with a stain from the current source 11 through the FET 21. Eventually, charging of the capacitor 51 progresses, and the drain voltage of the FET 31 increases to the level of the two-power NOR gate 4.
When the threshold voltage level of 1 is exceeded, the output of the NOR gate 41 becomes ``0#'' and the output of the gate 42 becomes 11#. Therefore, FET22.31 is turned on and FET21.32 is turned off.
becomes. At this time, the charge of the capacitor 51 is F E Ta
2, the capacitor 52 has a charge of 9FE.
A stain is supplied from the current source 11 through T22. As a result of this charging, when the drain of the FET 32 exceeds the threshold voltage V of the gate 42, the output of the gate 42 becomes ``0'' and the output of the gate 41 becomes ``1'', returning to the previous state. Therefore, although the capacitors 51 and 521d are repeatedly charged and discharged, a potential lower than the ground voltage is not generated on the circuit, and there is no risk of latch-up.

In the operation of this circuit, the charging time of the capacitors 51 and 52 is as follows:
If the current value of the constant current source 11 is E and the threshold voltage of the NOR gate 41.42 is V, then the charging time of the capacitor 51 and the capacitor 52 are as follows. The oscillation frequency obtained from the outputs of NOR gates 41 and 42 is Cl=C! Nara Duty 50chi C*
When the waveform of C1,- is C1 and C2, a waveform of 1 near A of Go or 7 is obtained.

<Effects> As described above, in the circuit according to the present invention, a potential exceeding the power supply voltage range is not generated in the circuit at any time.
It has the advantage that there is no risk of latch-up even when it is incorporated into a MO8IC.

Further, by changing the capacitance ratio of the two capacitors, an arbitrary duty output waveform can be obtained.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing a conventional voltage controlled oscillation circuit, and FIG. 2 is a connection diagram showing an embodiment of the voltage il'i:+0<I oscillation circuit according to the present invention. 11: Voltage open side 1 current source, 21, 22: P channel MO
8FET, 31.32: N-channel MO8FET, 41
, 42: N forming the set-reset flip-flop
OR goo), 51.52: Capacitor, 61: i! source terminal. Patent applicant Taku Kusano, agent for NEC Corporation

Claims (1)

[Claims] (ll'fi!) A power supply terminal is connected to one end of a current source whose flow rate is controlled by pressure, and the first and second conductors are connected to the other end.
The source of the MO8FET'f' is connected to the drain of the first and second one conductivity type MO8FET.
The drain of the second reverse conductivity type MO8FBT, the first, and the second drain
are connected to one end of each of the capacitors of the first and second capacitors.
The source of the second reverse conductivity type MO8FET and the source of the first MO8FET. The other ends of the second capacitors are respectively grounded, and the first and second capacitors are grounded. Second
The two-conductivity type MO8FET and the first one. Second reverse conductivity type MO8
The connection point with the FET is connected to the two input terminals of the set/reset flip 7p tube, and the two output terminals of this flip-flop are connected to the first one-conductivity type MO8FE.
T and each gate of the first reverse conductivity type MO8FET, the second 14% type MO8FET and the second reverse conductivity type MO8F
A voltage controlled oscillator circuit connected to each gate of ET.