JPS58209156A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To increase the quantity of a signal of an MOS memory cell and reduce cell size by bringing the positional relationship of high melting-point metal gate electrode wiring, a through-hole and the Si electrode of an upper layer to self-aligning structure. CONSTITUTION:The MOS memory cell is constituted by an Si semiconductor substrate 1, a thick oxide film 2, a gate oxide film 3, a first layer Si layer 4, an Si oxide film 5, The high melting-point metal gate electrode wiring 6, an inter-layer insulating film 7, the thrugh-hole 16, Al wiring 9, impurity regions 10, an internal Si oxide film 17 and the second Si layer 12. The positional relationship of the wiring 6, the through-hole 16 and the Si layer 12 is self-aligned. Accordingly, spaces among the wiring 6 and both the through-hole 16 and the Si layer 12 can reduce even the thickness of the oxide film 17. Consequently, cell size can be reduced while the quantity of the signal can be increased when cell size is made constant according to such constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS memory cell used in a commercially melting point metal all-gate electrode wiring, and to summerization of a signal signal and reduction in cell size.

In recent years, as MO8LSIs have become smaller and more dense, signal propagation delays due to electrode wiring resistance have become a serious problem; Thieves are attempting to replace the material with point metal silicide. In addition, although the cell size is reduced by so-called scaling down, a reduction in signal amount due to a small change in the electric capacitance part C·m product is also a major problem.

Figure 1 (a) shows the 256 using high melting point metal gate electrode arrangement, which was made four times in 1) MO8RAM cell, where l is S1 semi-substrate, and 2 is thick for insulation isolation. Commercially available film, 3 is gate oxide group, 4 is silicon layer, 5 is Noricon oxide dust, 6 is high melting point metal gate electrode wiring, 7 is interlayer color indicator #, group, 8 is through hole, 9 is A1 powder distribution, 10 is the impurity region. The first problem (the good part of the a+ silicon layer 4 is the part where each blood cell is formed.The area surrounded by the two-point forward line in the figure (8.05x'8.6pm) or 1p) Compatible with C mesori cells. Here, the inside diameter of the metal gate electrode arrangement 6 is 2 μm, the diameter of the through hole 8 is 1 μm, and the distance between the metal gate electrode arrangement 6 and the through hole 8 is 1 μm.
It is m. Also, the m product of the parts forming each electrical type is 2
The thickness is 1.4 μm2 (the skin plate part 11(a)), and the thickness of the layer directly below this is 300A.

Let us now try to find the signal voltage Vsig which is neglected in this cell structure. The cell capacity M is OS, the sum of the threshold fluctuation of the bit Green Rong Xia CB9 MO8 transistor and the fluctuation of the base plate pressure temple is vl, the worst value of the cell's 1 high level [power supply' voltage (4, 5) - equivalent to leakage] minutes] with VH ~ total Vl1
1g can be expressed as 1. Here, V is 140mV,
Assuming the leakage equivalent is 0.5■, VH"i is set as 4.OV, and CB/Cs: 8i is substituted into the above formula to give the positive voltage V.
From a value of about 150 mV as aig to r.

In the future, we will further reduce the size of the cellulose and emit 1M+ MOS memory with a large capacity plate.
One problem, the regulation of changing signal voltages, has been observed over and over again in the RT process circle. One of the ways to do this is to consider using the insulating group under the silicon layer to be formed as a material with a large fat ratio like a silicon layer. Ruru, a sword to be considered. The wise man not only adds to the process, but also attacks the problems of the silicon nitride film itself, such as leakage current and dielectric pressure. It is necessary to form a contact hole for making contact, or this increases the area considerably, and although the increase in the production cost can be made, the electric capacity cannot be greatly increased.

Let us now consider the portion of the conventional cell structure shown in FIG. 1 in which an extra large area is taken up and the capacitance area is significantly limited. This is determined by the distance X between the high melting point metal gate electrode wiring 6 and the through hole 8.

That is, although the high melting point metal gate electrode wiring 6 and the impurity @ region 10 are self-aligned in position using the trufa line technology, the high melting point metal gate electrode wiring 6 and the through hole 8
The positional relationship between the two is not self-aligned, and the distance is usually 1 μm or more. Normal gloss has a high melting point and
If the metal gate electrode 6 and the through hole 8 are not aligned, the high melting point metal gate electrode 6 and the substrate or upper layer electrode will be electrically connected. This distance X is determined from the degree of phosphorography, the side etching depth, etc., and is required to be 1 μm or more. A through hole 8 with a diameter of 1 μm was formed between the two high melting point metal gate electrodes 6.
Even in case 1, a gap of 3 μm or more must be prepared in advance, which poses a big problem in miniaturizing the cell or increasing the electric capacity.

The present invention has been made in order to solve the above-mentioned drawbacks, and the present invention has been made to solve the above-mentioned drawbacks.
Form a layered structure and use the gold-oxide layer as an oxygen source
3i By oxidizing from inside, an insulating film consisting of 81 oxide film is selectively formed only on the surface of the high-melting point metal electrode, and at the same time, the high-melting point metal gate electrode wiring, through-holes, and upper layer C/sl are formed. The present invention relates to a structure and method for self-aligning the positional relationship of poles.

In order to achieve the above object, the present invention provides a semiconductor device having at least one memory cell consisting of one electric capacitance and one MIS field effect transistor connected to the electric capacitance. The field effect transistor is composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a first silicon layer formed on the insulating film, and the gate electrode wiring of the field effect transistor is made of a high melting point metal. ,
A through hole is formed adjacent to the insulating layer selectively formed on the surface of the high melting point metal, and the second silicon layer is electrically connected to the semiconductor substrate via the through hole,
The gist of the invention is a semiconductor device in which the positional relationship between the through hole, the second silicon layer, and the high melting point gate electrode wiring is self-aligned via the insulating layer. . In addition, the present invention includes a step of forming a first silicon layer of a predetermined shape on an insulating film formed on a semiconductor substrate, a step of oxidizing the surface thereof, and a step of forming a first silicon layer on an insulating film other than the first silicon layer 1-. forming a high melting point metal gate electrode wiring in a predetermined shape; forming a high eyelid point metal oxide layer on the surface of the high melting point metal gate electrode wiring; a step of forming through holes in the group; a step of forming a second phosphor layer on the entire surface;
Thereafter, heat treatment is performed in an atmosphere containing hydrogen to oxidize the second silicon bird from within, and a step of selectively forming an insulating layer on the surface of the high melting point metal gate electrode, and processing the second silicon layer. The gist of the invention is a method of manufacturing a semiconductor device characterized by including at least the steps of: Further, the present invention provides a semiconductor integrated device having at least one electric capacity and a memory consisting of one M/S field effect transistor 140 connected to the first electric capacity. is a semiconductor substrate,
It is composed of an insulating film formed on this and a high melting point metal electrode formed on this insulating film, and the second electric capacity is composed of the above mentioned high melting point metal electrode and the insulating film formed on this. The silicon layer formed on the insulating film is electrically connected to the semiconductor substrate through a second through hole opened in the insulating film on the semiconductor substrate. connected, and furthermore, the positional relationship between the second through hole and the silicon layer and the high melting point metal electrode is self-aligned via an insulating layer selectively formed on the surface of the high melting point metal electrode. The gate electrode wiring of the field effect transistor is made of a high melting point metal, and a through hole of Ml is formed in contact with an insulating layer selectively formed on this high melting point metal electrode, and a silicon layer is formed through the through hole. or electrically connected to the semiconductor substrate and in a positional relationship with the first through-hole and the gate electrode made of the silicon layer and the high melting point metal, or via the The gist of the invention is a semiconductor device characterized by being self-aligned. The invention further includes a step of forming a refractory metal gate electrode in a predetermined shape on an insulating film formed on a semiconductor substrate, and a step of forming a refractory metal oxide layer on the surface of the refractory metal gate electrode wiring. , forming vermilion first and second through holes in the disconnection group adjacent to the one-point metal oxide island;
A process step of forming a silicon layer on the entire track, and then heat-treating in an atmosphere containing hydrogen to oxidize the silicon layer from the inside and quickly forming an insulating gold layer on the surface of the island metal electrode; Invention c9 is a method for manufacturing a semiconductor device characterized by including at least a step of processing a silicon layer.

Next, an embodiment of the present invention will be described with reference to a cooling drawing. It should be noted that the embodiments are merely illustrative, and it goes without saying that changes and improvements may be made without departing from the spirit of the present invention.

Figures 5 and 42 show the semiconductor device of the present invention (aJ is a plan view, and (b) is a cross-sectional view taken along the line A-A'. Compatible with memory cells.

Here, 1 is a Si semi-insulator substrate, 2 is a strong oxide group for line isolation, 3 is a gate material, a hole is formed, 4 is a first layer silicon layer, 5 is a silicon oxide layer, and 6 is a silicon oxide layer. High melting point metal gate electrode wiring, 7? 'i-layer rif1 insulating film, 16 is a through hole, 9 is an A1 distribution layer, 10 is an impurity region, 17 is an internal silicon layer, and 12 is a second silicon layer. The oblique shaft part in b is the part forming the turtle volume I. Here, the positional relationship between the high melting point metal gate electrode wiring 6, the through hole 16, and the second silicon hole 120 is self-aligned, and the distance between the high melting point metal gate electrode wiring 6, the through hole 16, and the second silicon N112 or the internal siliconization The floating number of the bladder 17 is about 100λ to 1ooo X) 1, which is small.

Also, in order to compare with the conventional circuit shown in FIG. 1, the cell size is 69.2 μm2, except for the spacing X.

m> The width of the k-point metal gate electrode 6 (2 μm), the diameter of the through hole 8 (Ipm), and the gate film thickness (300″A) are the same.

In the circuit according to the invention, the spacing X is <0.1 μm;
= iLQ's conventional circuit -(21,4 μm2), the capacitance can be increased by 4.5 μm2. Therefore, the signal voltage v obtained by the circuit according to the invention
gig becomes, and it becomes possible to increase the signal type (150 mV) of the conventional circuit with the interval x=1 μm shown in FIG. 1 by about 30%.

Next, an embodiment of the method for manufacturing the semiconductor device of the present invention shown in section A2 will be described using M3[L. Electrode wiring materials that can be used in the present invention are required to have low resistivity, high heat resistance, and be easily reduced by heat treatment in an atmosphere containing hydrogen. Mo,
South melting point metals such as W t' Ta and Ti are optimal. Here, Mo will be explained in detail.

First, as shown in FIG. 3 (Al), a thick selective oxidation group 2 for isolation between elements is formed on the 81 substrate 1 by, for example, a selective oxidation method.
Furthermore, a gate oxide group 3 is formed. In this embodiment, the thickness of the gate oxide film 3 was set to 300 mm.

Next, impurity ions are formed over the entire surface of the silicon film and impurity ions are implanted to lower the resistance, and then a first silicon dove 4' is formed by a normal phosphorography process and an etching process. In this embodiment, the first silicon layer 4' is formed by p 30 by the OVD method.
00
The exposed gate oxide film 3 is then removed by etching to form a new gate oxide group 3' (see FIG. 3 (see Bl). 1. A silicon oxide film 5 is formed on the surface of the silicon layer 4' as an insulating layer.If it is desired to make the silicon oxide film thicker, the surface may be subjected to steam oxidation etc. at the stage where the silicon group is formed on the entire surface. It is a good idea to form a silicon oxide film to some extent beforehand. In this example, gate oxidation was used. Next, as shown in FIG. i) Form the Mo gate electrode wiring 6. In this example, the Mo gate electrode wiring 6 was formed to a thickness of 3000 A by Mo electron beam evaporation.

Next, as shown in FIG. 3 (DJ), a Mo oxide layer 13 is formed at least on the surface of the Mo oxide electrode 6.
and MoO3. MoO3 can be easily obtained by heat-treating Mo at a low temperature in an oxygen-containing atmosphere, but when the temperature reaches a high temperature of about soo'a or higher, it begins to rise and fall.Therefore, MoO3 is formed around the Mo-silicon layer. If heat treatment is performed in an oxygen atmosphere or in a hydrogen atmosphere, peeling of the film may occur.
cormorant. Therefore, the melting point of Mo oxide is about 1900'O
Abe, a must-have sword that uses MoO2, which is delicious and stable at high temperatures.
. However, it is not easy to form KMOO2 on the Mo thin film surface. As a result of various changes, we achieved stable KM.
We found the following two methods to create the o02 layer.

(IJ MO is oxidized at a low temperature below 500°C in an oxygen atmosphere to completely form 1/CM0. It is heat treated and converted into MoO2.

(Mo is heat-treated at a temperature of about 1000 c'C&E in an inert atmosphere containing 21 oxygen (λ gravity ratio of 1 or less).

The MOE compound formed by the first and second methods above is M00□
That being said, X-earnings and paperback diffraction were biased.

In this example, a Mo 2 O layer was formed by the first method. Specifically, horse mackerel, 30,000, 60 in bare atmosphere
After oxidation for 800'0,3 in nitrogen atmosphere
Approximately 40 minutes of heat treatment is performed on the surface of the Mo gate electrode 6.
MOo2 oxide 13 of OA was formed. Furthermore, nest 1 and 2
When comparing the Mo oxide formation methods, the first method is superior in terms of controlling the oxide film thickness and preventing the expansion of oxygen into Mo. Further, in this example, an oxide of Mo was formed as a layer on the surface of Mo, but the present invention can be practiced even if the entire Mo film contains oxygen. However, when Mo oxide is reduced to Mo, a large volumetric contraction occurs. For this reason, it is advantageous to form Mo oxide on the surface.

Next, Mo gate electrode wiring 6. Impurities are ionized using the first silicon layer 4 as a mask to form a source-drain impurity chain plate 10. In this example, As was dosed at 4 × 10 crn-2 at 100 KeV, and 1
Heat treatment was performed at 000°C for 220 minutes. In this example, MO oxide fw1 is formed on the surface of the Mo gate electrode wiring 6.
Although the ion implantation was performed after forming the Mo oxide layer 13, the ion implantation may be performed before the Mo oxide layer 13 is formed. In the case of metal gates, when the crystal grain size is 1000 A or more, when the film thickness approaches the gate electrode, the implanted ions penetrate the metal and enter the gate oxidized m+Si substrate due to the channeling phenomenon. There is a problem. Ion implantation after forming a Mo oxide on the Mo surface has a small effect on improving this channeling phenomenon, since the crystallinity of MO oxide is poor.

Next, after applying a resist film 14 as shown in Fig. 3, an opening 15 for a contact hole can be created in the resist layer 14 by a normal phosphorography process such as photo or electron beam base. . A part of the failure opening 15 may be formed so as to overlap the Mo gate electrode 6 as shown in the figure.

In the process that has been carried out up to now, as explained in the conventional device No. 11i, if the gate electrode and the contact hole overlap, the gate electrode and the through-hole rising electrode will naturally be shortened, so the through-hole will move away from the gate electrode. formed separately. The margin for this distance,
Usually 1 in consideration of side etching etc. during etching.
It is normal to take more than μm.

On the other hand, the present invention has a major disadvantage in that a part of the resist opening 15 may be formed overlapping the Mo gate electrode wiring 6 (as shown in the figure).

Next, the gate oxide film 3' at the resist h opening 15 is removed by diluted hydronic acid or dry etching to form a through hole 16, and then the resist layer 14 is removed.

In this example, since MoO□ is not exposed to dilute hydrofluoric acid, through-hole etching is performed after forming Mo oxide on the surface of the Mo gate electrode wiring 6 for safety reasons. Since resistance to acids is comparatively high, the Mo oxide forming step and the contact hole forming step may be reversed. That is, immediately after the step shown in FIG. 3(C), a bottom portion is formed in the resist layer 14 by a phosphorography step, partially overlapping the Mo gate electrode wiring 6. Next, as shown in FIG.
The resist layer 14 is removed. Next, Mo oxide 13 is formed on the surface of the MO gate electrode. At this time, if the MO@ oxide is formed by the first method described above, the treatment condition for oxidizing MO is 300°C, so the surface of the 81 substrate 1 in the contact area has a natural oxide film thickness. Only an oxide film of ha which is not much different is formed. Therefore, this group 81 oxide can be easily removed by light etching using a dilute heptonic acid solution, which is usually carried out immediately before electrode formation.

Next, after forming the through holes, the 27th recon noodles 12 are formed on the entire surface. In this example, electron beam evaporation was used. ) 35
00N was formed. In order to lower the resistance of Bo1Jsi15, ion implantation was performed on the A day to reduce the resistance of Bo1Jsi15.
“Dose.

Next, as shown in FIG. 3 (G), heat treatment is performed at 800°C to 1000°C in an inert atmosphere containing hydrogen or hydrogen gas to reduce the Mo oxide 13, and the Mo oxide 13 is reduced. The second phosphor layer is oxidized from inside to form an internal silicon oxide film 17 between the Mo gate electrode wiring 6 and the second silicon/11112. In this example, 10
Heat treatment was performed at 00°C for 960 minutes.

FIGS. 4(a) and 4(b) show the depth distribution of constituent elements measured by Auger electron spectroscopy before and after heat treatment in a hydrogen atmosphere. (a) shows the properties before heat treatment, and (b) shows the properties after heat treatment in H2 atmosphere (1000°C, 160 minutes).

That is, the fourth area fa) is the structure of the gate electrode portion after step (F) in FIG. 3, and it is clearly seen that a 51-Mo oxide-Mo-gate 5102 oxide group structure is formed. 4h(b) shows the distribution after step (G) in FIG. I can see it clearly. Oxygen does not enter the Mo, and the pMo gate electrode wiring 6 is not damaged by this process. Further, silicide formation due to the reaction between MO and 81 does not occur at all.

Furthermore, the second silicon dove 12 and the internal silicon oxide group 17
The interface and internal silicon densification group 17 and M.

The interface of the gate electrode wiring 6 shows an extremely steep Auger distribution, and both interfaces are judged to be extremely homogeneous and uniformly formed. The simulation of the present invention is that MoO□ is reduced in a hydrogen atmosphere, probably by the following reaction, and Lipo-17si is oxidized with steam by the generated H2O. Therefore, it is necessary to keep in mind that the thickness of the internal silicon oxide film 17 to be formed is Rk equal to the thickness 13 of the Mo oxide formed in advance.

Next, as shown in FIG.
A silicon electrode 18 is formed. An internal oxide group 17ρ is formed in a selective manner on the surface of the Mo gate electrode wiring 6 in an unsophisticated manner, and the Mo gate electrode wiring 6 and the second silicon electrode 18 can be formed separately in a self-aligned manner. Next, 5000Ai of OVD PSG film was formed as the interlayer insulating film 7, through holes 8 were formed by ordinary phosphor transfer and etching processes, AJ- was formed on the entire surface, and shim L was formed by ordinary phosphorography and etching processes. The device of the present invention is completed by forming the structure @9. In this example, Ai is 2% Si.
500X of J- was formed by sputtering.

Internal silicon failure Th formed by the method of the present invention
+7 film quality is XPS (X-ray photo-el
ectronBpectroaeop7) measurement, rare 7
Evaluation was made based on etching characteristics with tonic acid, withstand voltage, and leakage current. First, regarding the composition of Si & chemical film,
This was investigated by PS measurement. As a result, the binding energy of the 2P electrons of Sl formed by this internal oxidation method and constituting the fp-S1 gland is 103.3θ■, 5102
It was determined that the internal silicon oxide group 17 was sio
did.

When the etching degree of etching with dilute hydrofluoric acid (volume ratio HF:H,O=3:100) was measured, it was found that the etching depth of S1 by this internal oxidation method was about 120ν minutes, which was the same as that of normal po! JSi
It was equivalent to 109 A/min of a film. Pressure resistant.

The leakage current is calculated by forming a 500μ square hole 1Jsi-A-A2 on a 700λ silicon failure film formed by this internal oxidation method.
A shield electrode was formed and measured. As a result, the breakdown voltage was 10 6 - or more, and the leakage current was 10 = 2 A or less in most of the samples.

From the above film quality evaluation, it was concluded that the internal silicon oxide film formed by this internal oxidation method is equivalent to the normal silicon oxide group.In the example shown in FIG. 2 The thickness of silicon no was 3500A,
When the thickness is reduced to about 1=tsooλ or less, thick silicon oxide (k) is no longer formed at the interface between the Mo and silicon layers by heat treatment in a hydrogen atmosphere.

The reason for this is thought to be that as the silicon layer becomes thinner, oxygen escapes to the outside through grain boundaries and pinholes. The thickness of the second silicon layer 12 formed in the step of FIG. 3(F) is 110 OA, and this is
The depth distribution of constituent elements measured by Auger electron spectroscopy after heat treatment at 0°C for 160 minutes is shown for the five causes of flaws. Although the MO corrugated material is completely reduced, no thick internal silicon oxide film is formed at the second silicon layer-Mo interface. As a result of various studies on this issue, we have found that even if the second silicon layer 12 is thin, the silicon bird-MO
Since we have found a method to form a thick internal silicon oxide film at the interface, we will use FIG. 3(G) to loosen the process.

That is, in the step of FIG. 3(F), the second silicon layer 12 was formed to a thickness of 110 H by electron beam evaporation. Next, as shown in FIG. 3(G), about 40 OA of silicon oxide &19 was formed on the surface of the second silicon layer 12.

Next, heat treatment is performed in an atmosphere containing hydrogen to form Mo oxide 1-1.
3 to form an internal silicon oxide group 17 between the second silicon layer 12' and the MO gate electrode wiring 6. In this example, 1000'C in pure hydrogen! , Heat treatment was performed for 60 minutes. The sixth prisoner is silicon oxide 619 formed by this method.
- Polysilicon layer 12 - Internal silicon oxide film 17 - Mo
The phase separation in the depth direction of the constituent elements of the structure of the gate electrode wiring 16 is shown by Auger electron spectroscopy. It can be seen that a thick internal silicon film is formed between the silicon and MO, and each interface is arranged in an orderly manner. Alternatively, the second silicon layer 1
The surface of 2' is directly pirated, but this process makes M
It can also be seen that O is not oxidized. The subsequent steps are exactly the same as those shown in FIG. 3 (after the HJ step), so the explanation will be omitted.

FIG. 7 (al l (b) is another embodiment of the semiconductor device of the present invention, (a) is a plan view, and (b) is a cross-sectional view taken along the line A-A. The area corresponds to a 1-bit memory cell.Here, 1 is the 81st semiconductor base, and 2 is the 81st semiconductor base.
3 is a thick oxide film for insulation isolation, 3 is a gate oxide film, 61 is a gate electrode, 62 is a bulk electrode, 17 is an internal silicon oxide film, 22 is an electrode silicon layer, 201 is a first through hole, and 2o2 is a The second through hole, 17 is an interlayer insulating film, 9 is an A1 wiring, and 1° is an impurity region. Furthermore, Figure 7 (
The oblique part of al is the part that forms each electric sound. In the figure, a indicates the lth capacity and b indicates the second capacity.

Next, the characteristics of the semiconductor device of the present invention will be described.

(1) High melting point metal gate 'fL pole 61 and each heavy electrode 62
The positional relationships between the through holes 201 and 202, the high kA metal gate electrode 61 and the capacitive electrode 62, and the silicon layer 22 are self-aligned, and these electrodes and the sulfo-k 201
, 202 & Hisilico 7 to 22 spacing X is made as small as 400 to 1,000 A degree) in the internal silicone formation group 17.

(IIJ electric capacity includes the upper and lower surfaces of the high-melting-point metal heavy electrode 62, that is, the 1st electric capacity (shown as a in FIG. Electrode 62 - Internal silicon oxide film 17 - Silicon layer 2
2 (already shown in the diagram). Further, in this structure, since the second capacitor is formed on the capacitor electrode 62, there is no need to partially overlap the gate electrode and the capacitor electrode as in the conventional two-layer gate structure.

In addition, the gate electrode 61 and the electrode 62 are connected to the Mo
Of course, it is better to form the gate oxide film only once. The conventional two-layer gate process
Considering that the process consisted of two gate oxide film formation steps and two gate electrode formation steps, it is easy to understand how the process was simplified despite its inventive structural strength, fineness, and high performance. It should be possible.

In addition, in the device shown in FIG. 7 of the present invention, in order to compare with the conventional circuit shown in FIG.
9.2μm2), the width of the metal gate electrode 61 (2μm
m), diameter of through hole 2o (1 μm).

The thickness of the gate oxide film (300λ) is the same.

Let us now calculate the signal voltage vgig obtained by the device of the present invention. In the uninvented device, the spacing Compared to the conventional circuit, the area of the electrical part can be increased. That is, in the case of the conventional circuit shown in FIG. 1, the area of the electric weight part is 21.4 μm2, but in the device of the present invention, the area of the lower f11 IC/)lth weight part is 2o,
The total weight is 50.9 μm2, which is 1 μm2 and the upper second volume m5ao and sμm2.

Therefore, the device of the present invention has two conventional circuits in the same cell'@ building.
This means that it has an electric capacity and surface structure that is more than twice as large. Therefore, the signal voltage v,ig obtained by the device of the present invention is approximately U2.6 times the signal z (150 mV) of the conventional circuit with the same cell size as the conventional circuit shown in FIG. ” signal type will be obtained.

Next, an embodiment of the method for forming the semiconductor device of the present invention shown in FIG. 7 will be described using FIG. 8. First, as shown in FIG. 8 (Al), a selective oxide film 2 with a thick element amount m is formed on the S1 substrate 1 by, for example, selective oxidation method, and then a gate oxide film 3 is formed.In this embodiment, the gate oxide film 3 is Thickness is 300A
And so. Next, as shown in FIG. 3(B), MOJIK is formed on the entire surface, and a Mo gate electrode 61 and a capacitor electrode 62 are formed by a normal phosphorography process and an etching process.

In this example, Mo was deposited at a substrate temperature of 2 by electron beam evaporation.
300OA was formed at 50°C. Furthermore, Ward 8 (C) K
As shown, a Mo oxide layer 13 is formed on at least the surface of the MO electrode. In this embodiment, the first M described above is used.

The M002 layer was formed by an oxide formation method. In fact, after fermenting at 300°C for 160 minutes in an oxygen atmosphere,
After heat treatment at 800°C for 930 minutes in a nitrogen atmosphere, Mo
MoO□ oxide 13 of about 40 OA was formed on the surface of the gate electrode. Next, using the Mo layer as a mask, A8 was
KV at a dose of 4 x 10-" cm-2, and further heat-treated at 1000°C for 220 minutes for activation.
Source/drain impurity regions 10 are formed.

In this example, a Mo #R compound layer 1 is provided on the surface of the MO electrode.
Although the ion implantation was performed after forming the Mo oxide 13, the ion implantation may be performed before the Mo oxide 13 is formed. Next N8
As shown in FIG. fD), openings 15 for through holes are made in the resist 14 using a normal phosphorography process such as photo or electron beam exposure. At this time, a part of the opening 15 may be formed so as to overlap the Mo gate electrode 6 as shown in the figure. In the process that has been carried out up to now, as explained with the conventional apparatus in Fig. 1, the gate electrode and the electrode on the through hole naturally short-circuit, so the through hole is driven from the gate electrode. It is formed by This distance is normally set to 1 μm or more, taking into account margins in the phosphorography process, side etching in etching, and the like. In contrast, the present invention has a major feature in that a part of the opening 15 in the resist is formed over the Mo gate electrode 61, as shown in FIG. Next, the gate oxide film at the resist opening 15 is removed using dilute hydrofluoric acid or dry etching to form through holes 201 and 202, and then the resist layer 14 is removed.
“Remove”.

In this example, since MOO□ is not exposed to dilute hydrofluoric acid, through-hole etching is performed after forming MO oxide on the surface of MO gate electrode coupler 6 for safety reasons. Since the resistance to dilute hydrofluoric acid is comparatively high, the Mo oxide forming step and the through hole forming step may be reversed as roughly explained in FIG. 3 (0).

J3500^ was formed by electron beam evaporation, and then Aθ was changed to lXl016 in order to lower the resistance of 7 Rico/Asahi 21.
Crn-2 ion implantation was performed, and then Fig. 8 (
As shown in Fl, heat treatment is performed at 1000°C for 160 minutes in hydrogen or an inert atmosphere containing hydrogen to oxidize MO! The #j layer 13 is reduced and the supplied oxygen oxidizes the silicon layer 21 from the inside to form an internal silicon oxide group 17 between the MO gate v=polar interconnection 6 and the silicon layer 21.

Next, as shown in FIG. 8(H), the silicon electrode 1 is processed by a normal phosphorography process and an etching process to form an electrode silicon layer 22. Next, as shown in FIG. 8 (HIK), a CVDPBG group '65ooo layer is formed as a film 7 intermittently, a thistle hole 23 is formed by a normal phosphorography process and an etching process, A1 is formed on the entire surface, and a normal glue is applied. I) A1 pattern #j according to the filling process and etching process
9't- is formed and the device of the present invention is charged. In this example, 50% of 2% S1 fi AJ- was sputtered as A1.
0OA was formed.

If the thickness of the silicon layer 21 is as thin as about 1500 A or less, forming a silicon oxide film on the surface in advance and then heat-treating it in an inert atmosphere containing hydrogen to form a thick internal silicon oxide film is as follows. It is as explained in the example of Fig. 3.

Although the present invention has been described above with reference to the application to MO8O8 semiconductor devices, the present invention is not limited to MO8 half-layer elements, but can also be applied to MIS half-layer elements. It goes without saying that this is a technique that can be widely applied to devices in which it is necessary to form positions between electrode wirings and contact holes in a self-aligned manner.

Further, although the embodiments have been explained using MO, the present invention only requires that the metal oxide can be reduced by heat treatment in an atmosphere containing hydrogen.
It is clear that most metals are within the scope of the present invention. However, in order to oxidize Sl and obtain a thick S1 oxide film, the temperature during internal oxidation needs to be 800°C or higher, so it is considered difficult to apply low melting point metals.

Furthermore, it is also possible to form a metal nitride film not only on silicon oxide but also on a metal surface, and then perform aqueous reduction to form an internal silicon-containing film.

As explained above, this technology forms a three-layer structure of Ua=point metal-metal oxide 1PO'J Sl and oxidizes Bol 781 from the inside using the metal oxide as an oxygen supply source. It has the following characteristics:

(1) A structure is formed in which silicon oxide groups are selectively formed only on the high melting point metal surface.

(11) The void IJ Si remaining due to internal oxidation can be used as an upper layer electrode, and at the same time, this silicon electrode and high melting point metal electrode wiring can be connected in a self-aligned manner to the silicon oxide film formed due to internal oxidation. Can be separated.

(iti) Since the stain electrodes are separated by the silicon oxide group caused by internal oxidation, the position between the through hole and the two electrodes can also be formed in a self-aligned manner, and the distance between them can be shortened to several hundred A. be able to.

(1v) Acid cleaning, which is normally performed in silicon gate processes, becomes possible.

(vi) Since a metal oxide layer with poor crystallinity is formed on the surface of the high melting point metal, it is expected that it will have the same masking properties for ion implantation.

Since the present invention has the above-mentioned characteristics, it can realize multilayer electrode wiring, complete self-line contact, folded multilayer capacitors, etc., and will be useful for future LS.
It can be said that this technology has a great impact on the high density and quotient integration of I.

The above-mentioned technology has achieved a complete self-line contact and a self-line multilayer capacitor without any modification, and the semiconductor devices shown in Figures 2 and 71 using these technologies are different from conventional semiconductor devices. This means that the cell size and signal amount can be greatly improved compared to the previous model. Also currently,
LSI machine stringing 0) Maximum lattice lithography process and etching process.In our theory, through-holes and multilayer separation are carried out in a self-alignment line, so phosphorography process and etching process are required. This also has the effect of relaxing the high controllability required for the process and significantly increasing process latitude.

[Brief explanation of the drawing]

The first problem (a), (bl is the same as 256 using the conventional island melting point metal gate electrode arrangement). Plane and cross-sectional views of one embodiment of a semiconductor device, FIG.
A7 to (G) are an example of the method for manufacturing a semiconductor device of the present invention, FIGS. 4(a) + (b) are depth distributions obtained by Auger analysis before and after internal oxidation, and FIG. Figure 6 shows the distribution in the depth direction by Auger analysis after internal oxidation in a thin case, and Figure 7 shows the distribution in the depth direction by Auger analysis after forming a Noricon oxide film on the surface of a thin silicon layer and internally oxidizing it. (bl shows a plan view and a sectional view of another embodiment of the semiconductor device of the present invention, and FIGS. 8(N to f) and Q show another embodiment of the method for manufacturing the semiconductor device. 1...81 and a half Body substrate, 2...Thick oxide film, 3.3.
...Gate oxide film, 4...Silicon layer, 5...Silicon oxide group, 6...High melting point metal gate electrode wiring, 7.
・Layer gap group, 8...Through hole, 9...A1 arrangement, lO...Impurity region, 4...First silicon pigeon, 12
．． 12'... 27th silicon ~, 13... Mo oxide pigeon, 14... resist, to layer, z, s... opening,
16...Through hole, 17...Internal silicon oxide group (insulating layer), 18...Silicon electrode, 19...Silicon oxide group, 61...Kate electrode, 62...Volume electrode, 2
0...Through hole, 201...Brown 1 Through hole, 2
02...Second through hole, 21...Silicon layer, 22
...Electrode silicon layer, 23...Through hole % measurement Patent attorney Satoshi Takayama, representative of Nippon Telegraph and Telephone Public Corporation (1 IP person) (- Figure 1 (b) Figure 2 (a) (b) Figure 4 Su/l” Izuta Gin 1vl (minutes) Mataba...opens at 7am (minutes) Figure 5 Suba Tsukukan=! Vl (intermediate) Figure 7 (a) (b) Figure 8 Written amendment (method) % formula % 2. Title of the invention: Semiconductor device and its manufacturing method 3. Telephone number of the person making the amendment (03j365-1932 Name: Patent attorney 16108) Takayama
Toshio 5. Date of amendment order: July 13, 1975 (Shipping date: August 31, 1980)
3. Subject of amendment 2) Attached drawing Middle East Figure 3 (G') 2. Contents of the amendment As shown in the attached sheet 1. Specification, page 24, line 16, r (
G ") Correct I to '(J)." 2 Akira 1jI] 35 @ line 14 “To Figure 3 (A)-
(G')'' is corrected as Figure 1: S, △1~(, Jl+. 3. Correct Figure 3 (G') as Figure 3 (J).

Claims (1)

[Scope of Claims] (υ In a semiconductor device having at least one memory cell consisting of eight electrical capacitors and one M/S field effect transistor connected to the memory cells, the electrical capacitors are is a semiconductor substrate and an isolated I# formed on this semiconductor substrate.
, a film 7, and a first silicon layer formed on this wire-free group, the gate electrode wiring of the field effect transistor is made of a melting point metal, and is selectively formed on the surface of the melting point metal. A null hole is formed adjacent to the disconnected wire group, and the second silicon layer is electrically connected to the semiconductor substrate via the through hole.
A semiconductor device characterized in that the positional relationship between the silicon layer and the gastric melting point with respect to the gate electrode arrangement is self-aligned via the above-mentioned wire. (2) A step of forming a first silicon layer of a predetermined shape on an insulating film formed on a semiconductor substrate, a step of oxidizing the surface thereof, and a step of forming a first silicon layer of a predetermined shape on an insulating film other than the first silicon layer A step of forming a melting point metal gate electrode wiring, a step of forming a full melting point metal oxide layer on the ff surface for disposing the high melting point metal gate electrode, and forming the insulating group VC through hole adjacent to the metal oxide layer. a step of forming a second silicon layer on the entire surface, and then a heat treatment in an atmosphere containing hydrogen to oxidize the second silicon layer from inside,
A semiconductor device characterized in that the step of forming a disconnection group on the high melting point metal layer and the step of processing the second silicon layer do not contain at least L. manufacturing method. In the semiconductor integrated device rIt, the first O electric capacitor is composed of a semiconductor substrate, an insulated wire group formed thereon, and a high melting point gold 11i electrode formed on this insulating film, and the second The electric capacitor is composed of the above-mentioned high-melting point metal electrode, the lees, IW, and film formed on this, and the silicon layer formed on this layer, and the above-mentioned 7 silicon layers are formed on the above-mentioned electrically connected to the semiconductor substrate through a second through hole opened at an absolute distance on the semiconductor substrate;
Furthermore, the positional relationship between the second through hole, the silicon layer, and the high melting point metal electrode is self-aligned via an insulating layer selectively formed on the surface of the high melting point metal electrode, The gate cage of the electric field infant transistor is made of a high melting point metal, and a first through hole is formed selectively around the Takashima point gold nugget, and a first through hole is formed adjacent to the layer. The silicon layer is electrically connected to the semiconductor substrate at dC through the null hole, and the positional relationship between the first through hole, the silicon layer, and the foot electric wire made of the melting point metal is established. (4) ξ melting point metal gate electrode axis arranged in a predetermined shape on an insulating film formed on a semiconductor substrate; forming a high melting point metal electrode surface on the high melting point metal gate electrode proboscis surface, and forming first and second through holes in the above film adjacent to the high melting point metal electrode surface. a step of forming a silicon layer over the entire track; and a step of heat-treating in a hydrogen-rich atmosphere to oxidize the silicon layer from inside and selectively form an insulator on the surface of the high melting point metal electrode. , a method of manufacturing a semiconductor surface mount characterized by including at least a step of processing a silicon layer.