JPS58207722A - Logical circuit - Google Patents

Abstract

PURPOSE:To decrease a voltage applied between the emitter and the base of an emitter coupled type logical circuit transistor (TR), by providing a TR whose base is connected to the emitter coupling section of the emitter coupling type logical circuit TR and whose emitter is connected to the base of the emitter coupled logical circuit TR via a resistor. CONSTITUTION:The emitter coupled logical circuit is constituted by connecting emitters of the TRs Q1, Q2 mutually, the emitter of a TRQ3 of emitter follower operation is connected to the base of the TRQ1, and an input signal is applied to the base of a TRQ3 via a resistor RB. Further, a reference voltage VR is applied to the base of the TRQ2. Moreover, the base of the TRQ4 is connected to the emitter coupling section of the TRs Q1, Q2 and the emitter of the TRQ4 is connected to the base of the TRQ1 via a resistor R'E. An emitter-base voltage of the TRQ1 when an input terminal IN in short-circuited with a power supply voltage VEE', is decreased with the emitter-base voltage of the TRQ4, allowing to use a high performance TR having low emitter-base dielectric voltage without breaking down the emitter and the base.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to logic circuits, and more particularly to emitter-coupled logic circuits.

Conventionally, an emitter-coupled logic circuit (hereinafter abbreviated as Eel) having an emitter follower input as shown in FIG. 1 has been used extensively in 1cKit's. During normal logic operation in such an ECL1 path, a high level ()iig is applied to the IN terminal.
h-Level) -〇, 9 Lower V/I/
(LIOW -Level) A voltage of -1.7V is applied. Now, if the forward voltage VBE between the base and emitter of the transistor is 0.8V, when operating at such a normal logic level, a potential of about -2.1V is usually selected as the reference 4-voltage VR, so the base of 1eQs : There is no reverse bias between the emitters.

However, as is common practice, if there is an input terminal that is not used, the input terminal is used by shorting it to the oven or the power supply terminal (VICI).

When such a single-use state occurs, the four pressures between the emitter and the base of Qx are as follows. In other words, since VB is -2,1V, the emitter potential of Ql is Q1's VnlOO,8
V t + L Chi 2.9 V Tofx Ri s look 1
The base of is at the same level as VEE via RIB. This is the emitter of Q1; the pressure between the base is lVggl-
12.9V l'5.2V - 2°9V = 2.3VK. Considering that VKI normally fluctuates by about ±0.5 V, the voltage between Q1 and the transmitter and base is 2.8 Va.
It will be applied up to a certain degree.

By the way, due to recent remarkable advances in semiconductor technology, the cutoff frequency fT of bipolar transistors has increased to 5 (3)
Iz-10(jHz) are being put into practical use, and in such high-performance transistors, the emitter;
The withstand voltage between the bases is 2V to 3■. When using such an element, in the circuit example shown in Figure 1, if the input terminal is connected to VimK4, a reverse bias of ~2.8μ will be applied between the emitter and base of Ql as described above, and the ?
The following current Path occurs at t: where the base junction breaks down, resulting in an abnormal operating level on the circuit. That is, the emitter of Ql: As a result of the base breakdown, the current is RC- + Q 1 → Emitter of Qt:
Since the current flows through the path from base junction to kLE, a current other than the constant current 1 flows through aC.

The present invention provides a circuit that can use such a high performance transistor with low emitter:base breakdown voltage without causing emitter:base breakdown.

The logic circuit according to the present invention includes first and second transistors whose emitters are coupled to each other, the emitter-coupled iJ, which constitutes the logic circuit, and whose base receives an external signal.
In a logic circuit consisting of a third transistor that is connected to the base of the transistor ff1t2 and operates as an emitter follower, and a reference (pressure generating circuit) connected to the base of the second transistor, the beetle 1 is connected to the base of the transistor. The present invention is characterized in that a @4 transistor is provided which is connected to the emitter coupling portions of the first and second transistors and connected to the base of the first transistor via an emitter resistor.

According to the present invention, the voltage applied between the emitter and the base is
Narita can be significantly reduced.

FIG. 2 shows an embodiment according to the invention. Similar to the explanation in Figure 1, if the input terminal IN is shorted to the vg iris, calculate the emitter:base voltage of Ql, and now Rg = 7'Ql
@VEBQI = (l Viegl - (1VRI+2
X0.8V))=0.75+0.8=1.55V, which is 0.75V lower than the aforementioned 2.3V applied in the conventional example shown in FIG.

However, in the embodiment shown in FIG. 2, it is also necessary to consider the emitter-base distance of Qs. If we perform the same total of 4 for Qs as for Ql, we get = (5, z - (2,, t + z) xo, s ) ) x - =
Since it is 0.75V, there is no problem.

FIG. 3 shows another embodiment of the invention. In this example, the base of Q4 is connected to Vn. detailed total,
11. is the same as Figure @2, so it will be omitted, but in this case, by appropriately selecting the ratio of Rm and kLyr,', Qt-Q
S's emitter, ri: The normal air pressure between the bases is 1v~1
．． It can be applied to about 5 V.

[Brief explanation of the drawing]

FIG. 1 shows an example of a conventional ECL logic circuit. FIG. 2 shows an embodiment of the invention. FIG. 3 is a diagram showing another embodiment of the present invention. Q1~See 4...Transistor.

Claims (2)

[Claims] (1) Emitter coupling i
first and second transistors forming a J1 logic circuit;
A third transistor whose base receives an external signal and whose emitter is connected to the base of the first transistor and operates as an emitter follower, and a circuit that applies a reference magnetic pressure to the base of the second transistor. The circuit is characterized in that the fourth transistor has a base connected to the nioscillator portions of the first and second transistors and an emitter connected to the base of the first transistor via a resistor. t@buried circuit. (2) In the semiconductor logic circuit described in M range l. 2. The logic circuit according to claim 1, wherein the base of the fourth transistor is connected to the base of the second transistor.