JP3682801B2 - Switch circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a switch circuit using a MOS transistor, and more particularly to its well potential setting circuit. The switch circuit of the present invention is applied to, for example, a CMOS analog switch circuit or a circuit using the same.
[0002]
[Prior art]
A conventional CMOS analog switch circuit is shown in FIG.
Q10 and Q20 constituting the CMOS analog switch are MOS transistors each forming a transfer gate, Q10 is a P-channel MOS transistor (PMOST), and Q20 is an N-channel MOS transistor (NMOST). INV1 is an inverting buffer that amplifies the input signal voltage, and INV2 is an inverter that further inverts the output of INV1, and has a known circuit configuration.
[0003]
Here, a positive surge (positive surge voltage) is input to the input terminal IN, and the input main electrode of Q10 is based on an N-type substrate (which may naturally be an N-type well region) immediately below the channel of Q10. When a parasitic transistor Ty consisting of a lateral pnp bipolar transistor having the P-type region formed as an emitter and the P-type region forming the output main electrode of Q10 as a collector becomes conductive, the influence of this positive surge is affected even when the CMOS analog switch is cut off. It appears as a potential change at the output terminal OUT of the analog switch.
[0004]
Similarly, a negative surge (negative surge voltage) is input to the input terminal IN, the P-type well just below the channel of Q20 is used as a base, the N-type region forming the input-side main electrode of Q20 is used as the emitter, and Q20 When a parasitic transistor Tx composed of a lateral npn bipolar transistor having an N-type region as a collector on the output side main electrode is turned on, the negative surge influences the potential change at the output terminal OUT of the CMOS analog switch even when the CMOS analog switch is cut off. Appears.
[0005]
FIG. 13 shows another example of a conventional CMOS analog switch circuit. A CMOS transfer gate (analog switch) Q30 and Q40 is used as a load element, and a modified MOS inverter having a source-grounded NMOS transistor Q50 as a driver element is input. It is connected between the terminal IN and the ground potential Vss. In the modified MOS inverter, when the potential of the control terminal G of the analog switch is Hi and Q20 is turned on, the P-well potential of Q20 substantially follows the potential of the input terminal IN, so The on-characteristics of Q20 are improved by reducing the channel conductance modulation effect. However, in the circuit of FIG. 13, as in the circuit of FIG. 12, when a positive surge enters the input terminal IN, the effect of the positive surge appears on the output terminal OUT due to the action of the parasitic transistor.
[0006]
In Japanese Patent Publication No. 6-103733, in order to solve the above problem, two stages of CMOS analog switches are connected in cascade, and a first-stage semiconductor area in which the first-stage analog switches are integrated and a next-stage semiconductor in which the next-stage analog switches are integrated. A charge absorption region of the opposite conductivity type is formed on the surface of the substrate of one conductivity type along the boundary between the regions. In this way, a surge voltage is introduced into the input terminal of the first-stage analog switch so that a surge voltage is formed between the surface region of the opposite conductivity type formed on the substrate surface and connected to the input terminal of the first-stage analog switch. Even if the pn junction is forward-biased and, as a result, minority carrier charges are injected from the surface region of the opposite conductivity type into the substrate, the influence of the minority carrier charges on the output terminal of the next-stage analog switch can be eliminated. .
[0007]
[Problems to be solved by the invention]
However, when the above-described analog switches (transfer gates) are cascaded in two stages, the operation delays of the analog switches (transfer gates) overlap and the delay of the output signal increases. In particular, since the parasitic capacitance at the connection point of both analog switches is discharged through the channel resistance of the first-stage analog switch and the output resistance of the external amplifier connected to the first-stage analog switch, the parasitic capacitance and the CR time constant of the resistance are discharged. Dependent on the analog switch (transfer switch), signal transmission delay and wave distortion (high-frequency attenuation) occur.
[0008]
If the on-resistance value of the analog switch circuit as a whole is made equal to that of a single stage in order to connect analog switches in two stages in cascade, the first stage and the next stage require twice the area. The cascaded analog switch circuit has a problem that it requires four times as much chip area as that of a single stage.
The present invention has been made in view of the above problems, and an object of the present invention is to improve the surge cutoff of a MOS switch while suppressing an increase in chip area.
[0009]
[Means for Solving the Problems]
The following first and second inventions The circuit will be described below.
First, a switch circuit composed of PMOS transistors will be described. The pn junction between the n-type substrate which is the semiconductor region immediately below the gate and the p-type input-side semiconductor region (or output-side semiconductor region) is reverse-biased by the potential setting of the n-type substrate by the potential setting means. . In particular, in the present circuit, this potential setting means is composed of a unidirectional power supply (power supply circuit in which current flows only in one direction) that supplies power to the n-type substrate only in the direction in which the pn junction is reverse-biased. .
[0010]
In this way, even if a large positive surge enters the p-type input-side semiconductor region, the pn junction is continuously forward-biased and current (base current) flows from the n-type substrate to the potential setting means. Therefore, the collector current of the pnp bipolar parasitic transistor based on both the p-type regions as the emitter and collector and the base of the n-type substrate can be reduced by the suppression of the base current, and as a result, when the transfer gate is cut off. The current (collector current) flowing from the input-side semiconductor region to the output-side semiconductor region can be reduced.
[0011]
Similarly, a switch circuit composed of NMOS transistors will be described. The pn junction between the p-type substrate, which is the semiconductor region immediately below the gate, and the n-type input-side semiconductor region (or output-side semiconductor region) is reverse-biased by the potential setting of the p-type well by the potential setting means. . In particular, in this circuit, this potential setting means is constituted by a unidirectional power supply (power supply circuit in which current flows only in one direction) that supplies power to the p-type well only in the direction in which the pn junction is reverse-biased. . In this case, however, the current value in the direction of reverse-biasing the pn junction has a negative sign. That is, current is attracted to the outside from the p-type well.
[0012]
In this way, even if a large negative surge enters the n-type input side semiconductor region, the pn junction is continuously forward-biased and current (base current) flows from the potential setting means to the p-type well region. Therefore, the collector current of the npn bipolar parasitic transistor having both the n-type regions as emitters and collectors and the p-type well region as a base can be reduced by the suppression of the base current. It is possible to reduce the current (collector current) flowing from the input side semiconductor region to the output side semiconductor region at the time of interruption.
[0013]
According to the first invention Furthermore, since the current is supplied from the high-level power supply to the n-type substrate (that is, the semiconductor region immediately below the gate of the PMOST) through the npn emitter follower transistor, the unidirectional power supply can be easily configured. That is, when the positive surge input to the p-type input side semiconductor region of the PMOST is large and the potential of the n-type substrate exceeds the high power supply voltage, the base current flows from the high power supply to the n-type substrate through the npn emitter follower transistor. Can be prevented without causing the collector current to flow to the p-type output side semiconductor region of the PMOST through the pnp lateral parasitic transistor.
[0014]
According to a preferred embodiment Even if the potential of the n-type substrate increases due to the positive surge input, the base potential of the npn emitter follower transistor rises accordingly, so that the potential increase of the n-type substrate can be suppressed.
When a high power supply voltage is applied to the n-type substrate from the beginning as in the prior art, the reverse bias of the pn junction increases during normal operation when no positive surge is input to the p-type input side semiconductor region. Although there was a drawback that the characteristics of the PMOS transistor forming the gate deteriorated, this configuration can also solve this problem.
[0015]
According to a preferred embodiment, The control input terminal of the second transistor of the differential amplifier circuit is connected to the input terminal of the transfer gate (that is, the input-side semiconductor region), a predetermined reference voltage is applied to the control input terminal of the first transistor, A voltage at the collector (or drain) of the transistor is applied to the base of the npn emitter follower transistor. However, the potential level of the input terminal of the transfer gate when no positive surge is input is less than the reference voltage.
[0016]
In this way, when no positive surge is input to the input terminal (that is, the input-side semiconductor region) of the transfer gate, the first transistor is turned on, and the npn emitter holo by the voltage drop of the load element of the first transistor. The base potential of the transistor is lowered, and the PMOS transistor operates as a transfer gate (analog switch) in this potential state.
[0017]
On the other hand, when a positive surge is input to the input terminal (that is, the input-side semiconductor region) of the transfer gate and the potential rises, the second transistor is turned on, the first transistor is turned off, and the load element of the first transistor , The base potential of the npn emitter follower transistor rises rapidly, and the n-type substrate potential of the PMOS transistor forming the transfer gate rises rapidly. Therefore, forward bias of the pn junction at the time of positive surge input can be suppressed.
[0018]
According to the second invention Since the current is attracted from the p-type well region (ie, the semiconductor region immediately below the gate of the NMOST) to the lower power source through the pnp emitter follower transistor, the unidirectional power source can be easily configured. That is, when the negative surge input to the n-type input side semiconductor region of the NMOST is large and the potential of the p-type well region is lower than the low-level power supply voltage, the low-level power source is connected to the base from the p-type well region through the pnp emitter follower transistor. The problem that the collector current flows to the n-type output side semiconductor region of the NMOST through the npn lateral parasitic transistor can be suppressed without attracting current. Even when the negative surge input to the n-type input side semiconductor region of the NMOST is large and the potential of the p-type well region exceeds the low power supply voltage, the base current is attracted from the p-type well region to the low power supply, resulting in a large collector current. Can flow to the p-type output side semiconductor region through the pnp parasitic transistor.
[0019]
According to a preferred embodiment Even if the potential of the p-type well region is lowered due to the input of the negative surge, the base potential of the pnp emitter follower transistor is lowered accordingly, so that the potential rise of the p-type well region can be suppressed.
Note that when a p-type well region low power supply voltage is applied from the beginning as in the prior art, the reverse bias of the pn junction increases during normal operation when no negative surge is input to the n-type input side semiconductor region. Although there was a drawback that the characteristics of the NMOS transistor forming the gate deteriorated, this configuration can also solve this problem.
[0020]
According to a preferred embodiment The control input terminal of the second transistor of the differential amplifier circuit is connected to the input terminal of the transfer gate, that is, the input-side semiconductor region, and a predetermined reference voltage is applied to the control input terminal of the first transistor. The voltage at the collector (or drain) of the first transistor is applied to the base of the pnp emitter follower transistor. However, it is assumed that the potential level at the input terminal of the transfer gate when no negative surge is input exceeds the reference voltage (large in the positive direction).
[0021]
If no negative surge is input to the input-side semiconductor region of the transfer gate, the second transistor is turned off, the first transistor is turned on, and the base of the pnp emitter follower transistor is the voltage drop of the load element of the first transistor. The potential rises, and in this potential state, the NMOS transistor operates as a transfer gate (analog switch).
[0022]
On the other hand, when a negative surge is input to the input side semiconductor region of the transfer gate, the second transistor is turned on, the first transistor is turned off, the voltage drop of the load element of the first transistor becomes 0, and the pnp emitter follower is turned on. The base potential of the transistor is suddenly lowered, and the potential of the p-type well region of the NMOS transistor forming the transfer gate is suddenly lowered. Therefore, the forward bias of the pn junction at the time of negative surge input can be suppressed.
[0023]
【Example】
(Example 1)
An analog switch circuit will be described below as an example of the switch circuit of the present invention. A first embodiment will be described with reference to FIG.
This analog switch circuit includes a CMOS analog switch (CMOS transfer gate) 1 and a potential setting circuit (potential setting means) 2.
[0024]
The CMOS analog switch 1 includes a PMOS transistor Q10 and an NMOS transistor Q20 connected in parallel to each other. IN is an input terminal connected to the P-type input side semiconductor region 101 of the PMOS transistor Q10 and the N-type input side semiconductor region 201 of the NMOS transistor Q20. OUT is an output terminal connected to the P-type output side semiconductor region 102 of the PMOS transistor Q10 and the N-type output side semiconductor region 202 of the NMOS transistor Q20.
[0025]
INV1 is a CMOS inverter that inverts the control signal voltage applied to the control input terminal G, and INV2 is a CMOS inverter that further inverts the output voltage of INV1.
The basic operation of the CMOS analog switch 1 is as follows.
When the control signal voltage applied to the control input terminal G becomes Lo, both transistors Q10 and Q20 are turned on, and the CMOS analog switch 1 is turned on. More specifically, if the potential at the input terminal IN is higher than the potential at the output terminal OUT, the input-side semiconductor region 101 of the transistor Q10 and the output-side semiconductor region 202 of the transistor Q20 serve as sources and carrier movement occurs. When the potential of the terminal IN is Lo than the potential of the output terminal OUT, the output side semiconductor region 102 of the transistor Q10 and the input side semiconductor region 201 of the transistor Q20 serve as sources to cause carrier movement. The potential matches the potential of the input terminal IN.
[0026]
However, if the potential of the input terminal IN is Hi, the current flows mainly through the PMOS transistor Q10 due to the increase of the threshold voltage of the NMOS transistor Q20 and its on-resistance, and conversely if the potential of the input terminal IN is Lo. In order to increase the threshold voltage of the PMOS transistor Q10 and its on-resistance, current flows mainly through the NMOS transistor Q20. Reference numeral 103 denotes an N-type substrate region (semiconductor region immediately under the gate) of the PMOS transistor Q10, and 203 denotes a p-type well region (semiconductor region immediately under the gate) of the NMOS transistor Q20.
[0027]
The CMOS analog switch 1 has a built-in NMOST potential setting circuit unit 3 for setting the potential of the transistor Q20.
The NMOST potential setting circuit unit 3 includes a modified MOS inverter circuit having a PMOS transistor Q30 and an NMOS transistor Q40 constituting a CMOS transfer gate (analog switch) as load elements and a source-grounded NMOS transistor Q50 as a driver element as an input terminal IN. And a low power supply voltage (also simply referred to as a low power supply) Vss.
[0028]
In this modified MOS inverter circuit, when the potential of the control terminal G of the analog switch is Lo and the transistor Q20 is turned on, the potential of the P-well region of the transistor Q20 is changed to the potential of the input terminal IN (input signal voltage Vi). This is to improve the on-characteristic of the transistor Q20 by reducing the channel conductance modulation effect of the transistor Q20 due to the change of the input signal voltage Vi by substantially following.
[0029]
When the potential of the control input terminal G is Hi, the transistor Q50 is turned on, the transistors Q30 and Q40 are turned off, and the potential of the P well region 203 is set to the low power supply voltage Vss. At this time, the NMOS transistor Q20 is off, and even if the potential of the input terminal IN (input signal voltage Vi) becomes Lo, the n-type input side semiconductor region 201 and the p-type well region 203 of the NMOS transistor Q20 are not connected. The pn junction is not forward biased.
[0030]
When the potential of the control input terminal G is Lo, the transistor Q50 is turned off and the transistors Q30 and Q40 are turned on. Since the transistors Q30 and Q40 constitute a CMOS analog switch (transfer gate), their channel conductance is maintained at a large value regardless of fluctuations in the potential of the input terminal IN (input signal voltage Vi). As a result, the potential of the p-type well region 203 of the NMOS transistor Q20 follows the potential of the input terminal IN (input signal voltage Vi) through the transistors Q30 and Q40, thereby the n-type input side semiconductor region of the NMOS transistor Q20. The channel conductance modulation effect due to the potential fluctuation of 201 is reduced, and the on-characteristic of transistor Q20 is improved.
[0031]
The potential setting circuit 2 constitutes the potential setting means referred to in the present invention, and is a collector resistor 22 for connecting the npn emitter follower transistor 21 and its collector to a high power supply voltage (also simply referred to as a high power supply) Vcc. And a base current setting circuit unit 24 constituting the base current setting means in the present invention. The emitter of the npn emitter follower transistor 21 may be connected to the low power supply voltage Vss through a predetermined emitter load element. This emitter load element can be constituted by a resistance element, a Zener diode whose breakdown voltage is set to be higher than at least the reference potential V1, and the like.
[0032]
The base current setting circuit unit 24 includes a constant current source 241 (feeding means) interposed between the high-level power supply voltage Vcc and the common connection point C, and the base connection point C and the npn emitter follower transistor 21. A resistor 242 interposed between the common connection point C and the base current from the common connection point C to the base; a resistor 243 (differential current suction means) for connecting the common connection point C to the reference potential point V1 through the diode D1; Consists of.
[0033]
The operation of the potential setting circuit 2 will be described below.
In a state where no positive surge is input to the input terminal IN, the npn emitter follower transistor 21 supplies a leakage current of each pn junction of the CMOS analog switch 1. At this time, the base current setting circuit unit 24 uses the base current ib that is 1 / k (k is the current amplification factor) times the emitter current of the npn emitter follower transistor 21 as the base of the npn emitter follower transistor 21. Supply. The constant current source 241 supplies a constant current ic to the common connection point C, and the remaining current ic-ib is discharged to a reference voltage point (also simply referred to as a reference voltage) V1.
[0034]
Now, the resistance value of the resistor 242 is Z2, the resistance value of the resistor 243 is Z3, the output voltage of the potential setting circuit 2, that is, the potential of the n-type substrate 103 which is the semiconductor region immediately below the gate of the MOS transistor Q10 is Vx, and the npn emitter follower transistor. If the forward voltage drop between the emitter and base of 21 = the forward voltage drop of the diode D1 = ΔV, the following equation is established.
[0035]
[Expression 1]
Z3 · (ic−ib) + ΔV + V1 = Z2 · ib + ΔV + Vx
From the above formula
[0036]
[Expression 2]
Vx = Z3.ic- (Z3 + Z2) .ib + V1
That is, Vx is determined by V1, assuming that ib is constant. If the potential at the common connection point C is Vc, the following equation is established.
[0037]
[Equation 3]
Vc = ib · Z2 + ΔV + Vx
[0038]
[Expression 4]
Vc = V1-ib.Z3 + ic.Z3 + .DELTA.V
From Equation 4,
[0039]
[Equation 5]
ib = (V1−Vc + ic · Z3 + ΔV) / Z3
From Equation 5,
[0040]
[Formula 6]
Vc = Z2 · (V1−Vc + ic · Z3 + ΔV) / Z3 + ΔV + Vx
Is established. From Equation 5,
[0041]
[Expression 7]
Vc (1 + Z2 / Z3)
= Z2 · (V1 + ic · Z3 + ΔV) / Z3 + ΔV + Vx
Is established. From Equation 6, it can be seen that when the emitter potential Vx of the npn emitter follower transistor 21 is increased by the positive surge, the potential Vc of the common connection point C is also increased accordingly.
[0042]
Furthermore, since the potential Vc at the common connection point C follows and rises in accordance with such an increase in the emitter potential Vx, the pn junction between the emitter and base of the npn emitter follower transistor 21 is reverse-biased by a positive surge. Can be prevented from surrendering.
Note that the base potential of the npn emitter follower transistor 21 may be a constant potential. In this case, there is a possibility that the emitter potential of the npn emitter follower transistor 21 rises due to the input of the positive surge and the pn junction between the emitter and the base breaks down.
[0043]
Further, it is possible to directly apply the high power supply voltage Vcc to the base of the npn emitter follower transistor 21, but in this case, even when no positive surge is input to the input terminal IN, Vcc− is applied to the n-type substrate 103. A high potential of about 0.7 V is always input, which is not preferable. In other words, when the high power supply voltage Vcc is directly applied to the n-type substrate 103 as in the prior art, if the potential of the n-type substrate 103 becomes higher than that due to a positive surge, the breakdown emitter-base of the npn emitter follower transistor 21 is generated. The base current of the npn lateral parasitic transistor is attracted from the n-type substrate 103 to the high-level power supply Vcc through the pn junction between the npn substrate and the collector current of the npn lateral parasitic transistor increases abnormally. These problems are solved by the potential setting circuit (unidirectional power source referred to in the present invention) 2 of this embodiment.
(Example 2)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0044]
This potential setting circuit 2a omits the collector resistor 22 in the potential setting circuit 2 shown in FIG. 1, and instead of the diode D1, a predetermined number of cascaded junction diodes 25 are connected between the resistor 243 and the lower power supply voltage Vss. It is arranged. In this way, the constant voltage circuit for creating the reference voltage V1 can be simplified.
In this embodiment, the constant current source 241 is constituted by a grounded source type PMOST in which the low power supply voltage Vss is applied to the gate, but a pnp transistor is used and the high power supply voltage Vcc is applied to the emitter thereof. Then, the collector may be connected to the common connection point C, and the base may be connected to the low potential power supply Vss through the base current limiting resistor.
(Example 3)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0045]
This potential setting circuit 2 b is formed by arranging three junction diodes 26 connected in cascade between the high power supply voltage Vcc and the n-type substrate 103. In this case, even if the potential of the n-type substrate 103 is considerably higher than the high power supply voltage Vcc, the breakdown of the junction diode 26 can be suppressed by the amount of the junction diode 26 cascaded.
(Example 4)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0046]
The potential setting circuit 2 c includes a differential amplifier circuit 4, a constant voltage generation circuit 5, and an npn emitter follower transistor 21.
The differential amplifier circuit 4 includes a pair of npn transistors 41, 42, a common emitter load element 43, and collector resistors 44, 45. The emitters of the transistors 41 and 42 are connected to a low power supply Vss through a common emitter load element (common load element) 43. The collector of the transistor 41 (second transistor) is connected to the high power supply Vcc through the collector resistor 44, and the collector of the transistor 42 (first transistor) is connected to the high power supply Vcc through the collector resistor 45.
[0047]
The common emitter load element 43 is composed of an NMOST in which a p-type region, which is a semiconductor region directly under the gate, is connected to the low power supply voltage Vss and a gate electrode is connected to the high power supply Vcc. The n-type region, which is a region, is composed of an NMOST having a gate electrode connected to a low power supply voltage Vss and a gate electrode connected to the high power supply Vcc. Of course, the elements 43, 44 and 45 can be constituted by simple resistance elements, and the common emitter load element 43 can be a constant current source. The base of the transistor 41 is connected to the input terminal IN, and the base of the transistor 42 is connected to the output terminal of the constant voltage generating circuit 5.
[0048]
The constant voltage generation circuit 5 includes a multi-stage cascaded voltage drop pn junction diode 51, and a discharge resistor 52 that connects the cathode of the diode 51 at the lowest potential end to the low power supply Vss. Make the output. The discharge resistor 52 can be omitted. In addition, a simple resistance element can be employed instead of the pn junction diode 51 for voltage drop connected in cascade, and a Zener diode can also be employed.
[0049]
The collector of the transistor 42 is connected to the base of the npn emitter follower transistor 21. The constant voltage generation circuit 5 outputs a reference voltage V2.
Hereinafter, the operation of the potential setting circuit 2c will be described. It is assumed that the reference voltage V2 is more positive than the potential of the input terminal IN in a state where no positive surge is input to the input terminal IN.
[0050]
When no positive surge is input to the input terminal IN, the transistor 42 is turned on and its collector potential becomes (Vcc-i · r). i is a current defined by the common source transistor 43, and r is a resistance value of the collector resistor 45. Therefore, the output voltage of the npn emitter follower transistor 21 is (Vcc−i · r−ΔV). ΔV is a forward voltage drop at the pn junction between the emitter and base of the npn emitter follower transistor 21.
[0051]
When a positive surge is input to the input terminal IN and the potential of the input terminal IN exceeds the reference voltage V2, the transistor 41 is turned on, the transistor 42 is turned off, and the base of the npn emitter follower transistor 21 has a substantially higher power supply voltage Vcc. Is applied, and the npn emitter follower transistor 21 raises the potential of the n-type substrate 103 of the MOS transistor Q10 to Vcc−ΔV. That is, the potential of the n-type substrate 103 is increased by i · r than before. As a result, the potential of the n-type substrate 103 rises against the potential rise of the p-type region 101 of the MOS transistor Q10 due to the positive surge, so that the pn junction between them does not forward bias.
[0052]
Furthermore, an important advantage of this embodiment is that the potential of the n-type substrate 103 can be raised before the pn junction between the p-type region 101 and the n-type substrate 103 is in a forward bias state. The collector current of the lateral pnp parasitic transistor whose base current is the forward bias current of the junction, that is, the current that reaches the output-side semiconductor region 102 can be cut off.
(Example 5)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0053]
The potential setting circuit 2 d is configured such that the anode of the diode D 2 is connected to the high power source Vcc through the resistance element 46 and the cathode is connected to the n-type substrate 103.
When no positive surge is input to the input terminal IN, the potential setting circuit 2d supplies a pn junction leakage current to the n-type substrate 103, and the voltage drop ΔV of the resistance element 46 is the resistance value of the resistance element 46 and the leakage current. It is the value multiplied by.
[0054]
When a positive surge is input to the input terminal IN and the potential of the n-type substrate 103 increases through the p-type region 101, the voltage drop ΔV of the resistance element 46 decreases or disappears due to the decrease or disappearance of the leakage current, and the n The potential of the mold substrate 103 increases. Further, when the positive surge applied to the input terminal IN further increases, the diode D2 cuts the base current of the pnp parasitic lateral transistor from the n-type substrate 103 to the high-level power supply Vcc, and the collector current flows to the p-type region 102. Stop.
(Example 6)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0055]
The potential setting circuit 2e of this embodiment is similar to the potential setting circuit 2 of FIG. 1 in order to prevent the breakdown of the pn junction between the emitter and base of the npn emitter follower transistor 21 due to the positive surge described above. A zener diode 23 is provided between the emitter 21 and the lower power supply Vss. In this way, even if an excessive positive surge is input to the input terminal IN and the voltage of the n-type substrate 103 rises via the pn junction between the source or drain of the transistor Q10 and the n-type substrate 103, Since the Zener diode 23 breaks down before the pn junction between the base and emitter of the npn emitter follower transistor 21 breaks down, breakdown of the pn junction between the emitter and base of the npn emitter follower transistor 21 can be prevented.
(Example 7)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0056]
The potential setting circuit 2f of this embodiment is obtained by adding junction diodes D3, D4, and D5 and omitting the collector resistor 22 in the potential setting circuit 2 of FIG. The junction diode D3 is interposed between the base of the transistor 21 and the resistor 242, the junction diode D4 is interposed between the collector of the transistor 21 and the high-level power supply Vcc, and the junction diode D5 includes the junction diode D1 and the resistor 243. It is interposed between.
[0057]
In this case, even if the pn junction between the emitter and base of the npn emitter follower transistor 21 breaks down due to an excessive positive surge, the presence of the junction diodes D3 and D4 having a high breakdown voltage causes the emitter of the npn emitter follower transistor 21 to exist. An excessive breakdown current does not flow in the pn junction between the bases, so that the pn junction between the emitter and the base of the npn emitter follower transistor 21 is not broken. D5 is provided for balance with D3.
(Example 8)
Another embodiment of the potential setting circuit 2 shown in FIG. 1 will be described with reference to FIG.
[0058]
The analog switch circuit includes a CMOS analog switch (CMOS transfer gate) 1g and potential setting circuits (potential setting means) 2 and 2g.
In the analog switch 1g of FIG. 1, the CMOS analog switch 1g connects the input terminal IN and the high level power supply V3 through the impedance element Z5, connects the input terminal IN and the low level power supply V5 through the impedance element Z6, and connects the output terminal OUT and the high level power supply. The power supply V4 is connected through the impedance element Z7, and the output terminal OUT and the low-level power supply V6 are connected through the impedance element Z8.
[0059]
These impedance elements Z5 to Z8 are elements for suppressing a surge voltage superimposed on the input terminal IN or the output terminal OUT.
The potential setting circuit 2g of this embodiment has the same configuration and operation as the potential setting circuit 2 shown in FIG.
The potential setting circuit 2g constitutes the potential setting means referred to in the present invention, and is a collector resistor 22a for connecting the pnp emitter follower transistor 21a and its collector to a low power supply voltage (also simply referred to as a low power supply) Vss2. And a base current setting circuit unit 24a which constitutes a base current setting means in the present invention, and the emitter of the emitter follower transistor 21a forms a low power supply voltage input terminal of the analog switch 1g through the output terminal Vy. It is connected to the source region of Q50. The base current setting circuit unit 24a includes a constant current source 241a (feeding means) interposed between the low power supply voltage Vss2 and the common connection point C ′, and the common connection point C ′ and the emitter follower transistor 21a. A resistor 242a interposed between the base and the common connection point C ′ for attracting the base current from the base, and a resistor 243a (differential current suction) for connecting the common connection point C ′ to the reference potential point Vss1 through the diode D8. Means). The operation of this potential setting circuit 2g will be described below.
[0060]
In a state where no negative surge is input to the input terminal IN, the emitter follower transistor 21a supplies a leakage current of each pn junction of the CMOS analog switch 1g. At this time, the base current setting circuit unit 24a attracts the base current ib that is 1 / k (k is the current amplification factor) times the emitter current of the emitter follower transistor 21a from the base of the emitter follower transistor 21a. . The constant current source 241a draws the constant current ic from the common connection point C ′, and the remaining current ic-ib is supplied from the reference voltage point (also simply referred to as reference voltage) Vss1 to the common connection point C ′.
[0061]
Now, the resistance value of the resistor 242a is Z2, the resistance value of the resistor 243a is Z3, the output voltage of the potential setting circuit 2g, that is, the potential of the p-type well region 203, which is the semiconductor region immediately under the gate of the MOS transistor Q20, is Vy. Assuming that the forward voltage drop between the emitter and the base of 21a = the forward voltage drop of the diode D8 = ΔV, the emitter of the emitter follower transistor 21a is caused by a negative surge as in the case of the potential setting circuit 2 of the first embodiment. It can be seen that when the potential Vy decreases, the potential Vc ′ at the common connection point C ′ also decreases accordingly.
[0062]
Accordingly, since the potential Vc ′ at the common connection point C ′ decreases following the decrease in the emitter potential Vy, the pn junction between the emitter and the base of the emitter follower transistor 21a is reverse-biased by a negative surge and breakdown occurs. Can be prevented.
Note that the base potential of the emitter follower transistor 21a can be set to a constant potential. In this case, there is a possibility that the emitter potential of the emitter follower transistor 21a drops due to the input of the negative surge, and the pn junction between the emitter and the base breaks down. Further, it is possible to directly apply the low power supply voltage Vss2 to the base of the emitter follower transistor 21a.
[0063]
Note that a ground voltage can be adopted as the reference voltage Vss1, and the lower power supply voltage Vss2 that is more negative than that can be generated by a switched capacitor circuit 300 as shown in FIG. 9, for example. This switched capacitor circuit 300 is well known, and switches S1 and S3 are opened and closed by a clock voltage Vc1 output from an oscillation circuit 301 that oscillates a rectangular pulse voltage at a constant frequency, and the clock voltage Vc1 is converted by an inverter 302. The switches S2 and S4 are opened and closed by the inverted clock voltage Vc2 to form a negative low power supply voltage Vss2.
Example 9
Another embodiment of the potential setting circuit 2g shown in FIG. 8 will be described with reference to FIG.
[0064]
This potential setting circuit 2h holds the base potential of the emitter follower transistor 21a substantially constant, whereby a negative surge is applied to the n-type region 201 (or 202) of the transfer gate Q20, and the n-type region 201 and the p-type Even if the pn junction with the well region 203 is forward-biased and the potential of the p-type well region 203 is lowered, the base potential of the pnp emitter follower transistor 21a is held substantially constant. The emitter current of the transistor 21a is cut off, so that the forward bias current does not flow continuously in the pn junction, thereby blocking the collector current of the lateral npn transistor formed parasitic to the transfer gate Q20. It has been granted.
[0065]
In this embodiment, in order to apply a substantially constant voltage to the base of the pnp emitter follower transistor 21a, a current mirror circuit composed of the transistors T100 and T101 is used. Further, the base of the emitter follower transistor 21a and the high-level power supply Vcc are used. A Zener diode D102 is provided between them. A diode D100, a Zener diode 101, and resistors R100, R101, R102, and R103 are load elements of the transistor T100 and are supplied with power from a high-level power supply Vcc. Note that a power supply of another potential may be employed instead of the high power supply Vcc. In this way, since a constant potential higher than the ground potential can be applied to the base of the emitter follower transistor 21a, the collector of the emitter follower transistor 21a can be grounded.
(Example 10)
Another embodiment of the analog switch circuit of the present invention will be described with reference to FIG.
[0066]
The analog switch circuit includes a CMOS analog switch (CMOS transfer gate) 1 and potential setting circuits (potential setting means) 2i and 2j.
The potential setting circuit 2i uses a resistance element 430 as a common emitter load element in the differential amplifier type potential setting circuit 2c shown in FIG. 4, and uses a resistance element 401 instead of the Zener diode 51. The junction diode D3 in FIG. , D4 are provided for protecting the emitter follower transistor 21.
[0067]
The potential setting circuit 2j is obtained by replacing the lower potential setting circuit 2g shown in FIG. 8 with the differential amplifier type potential setting circuit shown in the potential setting circuit 2i.
The potential setting circuit 2i includes a differential amplifier circuit 4a and a pnp emitter follower transistor 21a.
The differential amplifier circuit 4a includes a pair of pnp transistors 41a and 42a, a common emitter resistor (common load element) 430a, and collector resistors 44a and 45a. The emitters of the transistors 41a and 42a are connected to the high power supply line Vcc through a common emitter resistor 430a. The collector of the transistor 41a (second transistor) is connected to the low potential power source Vss2 through the collector resistor 44a, and the collector of the transistor 42a (first transistor) is connected to the low potential power source Vss2 through the collector resistor 45a. The base of the transistor 41a is connected to the input terminal IN, and the divided voltage V3 output from the voltage dividing circuit composed of resistors 401a and 52a connected in series is applied to the base of the transistor 42a. The collector of the transistor 42a is connected to the base of the emitter follower transistor 21a through the diode D3a, and the collector of the emitter follower transistor 21a is connected to the low power supply Vcc2 through the diode D4a.
[0068]
Hereinafter, the operation of the potential setting circuit 2j will be described. It is assumed that the divided voltage V3 is more negative than the potential of the input terminal IN in a state where no negative surge is input to the input terminal IN (or output terminal OUT).
When no negative surge is input to the input terminal IN, the transistor 41a is turned off, the transistor 42a is turned on, and the base potential of the emitter follower transistor 21a is Vss2 + i · r + ΔVd. i · r is a voltage drop of the resistor 45a, and ΔVd is a forward voltage drop of the diode D3a.
[0069]
When a negative surge is input to the input terminal IN and the potential at the input terminal IN falls below the divided voltage V3, the transistor 41a is turned on, the transistor 42a is turned off, and the base potential of the emitter follower transistor 21a becomes approximately Vss2 + ΔVd. Therefore, when a negative surge is input to the input terminal IN, the emitter follower transistor 21a reduces the potential of the p-type well region 203 of the transistor Q20 by the voltage drop i · r of the resistor 45a, and turns on the parasitic lateral npn transistor. Is suppressed. That is, since the potential of the p-type well region 203 is also reduced against the potential drop of the n-type region 201 or 202a of the MOS transistor Q20 due to the negative surge, the pn junction between them is not forward-biased.
[0070]
Further, in this embodiment, since the potential of the p-type well region 203 can be lowered before the pn junction between the n-type region 201 and the p-type well region 203 is in a forward bias state, the lateral pnp parasitic transistor Excellent barrier properties.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing Example 1 of a switch circuit of the present invention.
FIG. 2 is a circuit diagram showing Example 2 of the switch circuit of the present invention.
FIG. 3 is a circuit diagram showing Example 3 of the switch circuit of the present invention.
FIG. 4 is a circuit diagram showing Example 4 of the switch circuit of the present invention.
FIG. 5 is a circuit diagram showing Example 5 of the switch circuit of the present invention.
FIG. 6 is a circuit diagram showing Example 6 of the switch circuit of the present invention.
FIG. 7 is a circuit diagram showing Example 7 of the switch circuit of the present invention.
FIG. 8 is a circuit diagram showing Example 8 of the switch circuit of the present invention.
9 is a circuit diagram illustrating an example of a circuit that generates the low power supply voltage Vss2 of FIG. 8;
FIG. 10 is a circuit diagram showing Example 9 of the switch circuit of the present invention.
FIG. 11 is a circuit diagram showing Example 10 of the switch circuit of the present invention.
FIG. 12 is a circuit diagram showing a conventional MOS analog switch circuit.
FIG. 13 is a circuit diagram showing a conventional MOS analog switch circuit.
[Explanation of symbols]
Reference numeral 101 denotes a p-type input-side semiconductor region (one-conductivity-type semiconductor region), 102 denotes a p-type output-side semiconductor region (one-conductivity-type semiconductor region), and 103 denotes an n-type substrate (a semiconductor region directly under the n-type gate, opposite conductivity). 201 is an n-type input side semiconductor region (one conductivity type semiconductor region), 202 is an n type output side semiconductor region (one conductivity type semiconductor region), and 203 is a p type well region (p type gate). 1 is a transfer gate (analog switch), 2 is a potential setting circuit (potential setting means, unidirectional power supply), 21 and 21a are npn emitter follower transistors, and 24 is a base. Current setting means, C and C ′ are common connection points, 241 is a power supply means, 242 is a base current power supply means, 243 is a differential current suction means, D1 is a diode, 41 is a second transistor, 42 Is a first transistor, 44 and 45 are load elements, 43 is a common load element, 241a is power supply means, 242a is base current power supply means, and 243a is differential current power supply means.

Claims (6)

The one-conductivity-type input-side semiconductor region is connected to the signal input terminal, the one-conductivity-type output-side semiconductor region is connected to the signal output terminal, and both the one-conductivity-type semiconductor regions are in contact with the opposite-conductivity-type semiconductor region directly under the gate. In addition, a reverse bias voltage is applied to a pn junction between the MOS transistor that is conducted through an inversion channel formed on the surface of the opposite conductivity type semiconductor region and the opposite conductivity type semiconductor region and the one conductivity type semiconductor region. In a switch circuit comprising a potential setting means,
The potential setting means comprises a unidirectional power supply that supplies only current in a direction to reverse bias a pn junction between the opposite conductivity type semiconductor region and the one conductivity type semiconductor region to the opposite conductivity type semiconductor region. ,
The potential setting means is interposed between a predetermined high-level power supply and the opposite conductivity type semiconductor region as an n-type, a collector is connected to the high-level power supply side, and an emitter is on the opposite conductivity type semiconductor region side A switch circuit comprising an npn emitter follower transistor connected to the switch. The potential setting means includes base current setting means for setting a base current of the npn emitter follower transistor, and the base current setting means is provided between the high-level power supply and a predetermined common connection point. A power supply means for supplying a predetermined reference current to the common connection point; and a base between the common connection point and the base of the npn emitter follower transistor. A base current supply means for supplying a base current to the base current; and a difference current suction means interposed between the common connection point and a predetermined reference potential point for sucking a difference component between the two currents. The switch circuit according to 1 . The potential setting means is connected to a first transistor having a control terminal to which a predetermined reference potential is applied and whose high-side main electrode is connected to a high-level power supply through a predetermined load element, and to the input terminal of the transfer gate. A high-side main electrode having a control terminal and a high-side power supply fed from a high-level power supply, and a low-side main electrode of both the transistors and a low-level power supply terminal interposed between the two transistors. A differential amplifier circuit having a common load element for limiting the sum to a predetermined value, and the connection point between the high-order main electrode of the first transistor and the load element is the base of the npn emitter follower transistor. The switch circuit according to claim 1 , wherein the switch circuit is connected to the switch. The one-conductivity-type input-side semiconductor region is connected to the signal input terminal, the one-conductivity-type output-side semiconductor region is connected to the signal output terminal, and both the one-conductivity-type semiconductor regions are in contact with the opposite-conductivity-type semiconductor region directly under the gate. In addition, a reverse bias voltage is applied to a pn junction between the MOS transistor that is conducted through an inversion channel formed on the surface of the opposite conductivity type semiconductor region and the opposite conductivity type semiconductor region and the one conductivity type semiconductor region. In a switch circuit comprising a potential setting means,
The potential setting means comprises a unidirectional power supply that supplies only current in a direction to reverse bias a pn junction between the opposite conductivity type semiconductor region and the one conductivity type semiconductor region to the opposite conductivity type semiconductor region. ,
The potential setting means is interposed between a predetermined low power supply and the opposite conductivity type semiconductor region as a p-type, a collector is connected to the low power supply side, and an emitter is on the opposite conductivity semiconductor region side A pnp emitter follower transistor connected to the switch circuit. The potential setting means includes base current setting means for setting a base current of the pnp emitter follower transistor, and the base current setting means is provided between the low-level power source and a predetermined common connection point. Between the base and the common connection point interposed between the common connection point and the base of the pnp emitter follower transistor. sucking the base current base - scan current and suction means, according to claim 4 and a differential current feed means is interposed feeding the difference component of the two current between said common connection point and a predetermined reference potential point The switch circuit described. The potential setting means is connected to a first transistor having a control terminal to which a predetermined reference potential is applied and having a lower main electrode connected to a lower power supply through a predetermined load element, and an input terminal of the transfer gate. A low-side main electrode having a control terminal and a low-side power supply fed from a low-level power supply, and a high-side main electrode of both the transistors and a high-level power supply terminal interposed between the two transistors. A differential amplifying circuit including a common load element for limiting the sum to a predetermined value, and a connection point between the lower main electrode of the first transistor and the load element is a base of the pnp emitter follower transistor. The switch circuit according to claim 4 , wherein the switch circuit is connected to the switch.

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