JPS58207665A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58207665A
JPS58207665A JP9095482A JP9095482A JPS58207665A JP S58207665 A JPS58207665 A JP S58207665A JP 9095482 A JP9095482 A JP 9095482A JP 9095482 A JP9095482 A JP 9095482A JP S58207665 A JPS58207665 A JP S58207665A
Authority
JP
Japan
Prior art keywords
wiring layer
inclined surface
layer
recess
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9095482A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
茂 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9095482A priority Critical patent/JPS58207665A/en
Publication of JPS58207665A publication Critical patent/JPS58207665A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To fuse away wiring layers with a low power by forming a recess having the inclined surface at the surface of semiconductor substrate, extending wiring layer crossing said recess, and melting away the wiring layer with a heating means and by fusing away it through flowing along the inclined surface. CONSTITUTION:A wiring layer 16 is formed in such a way as extending along the inclined surface of a recess 12 crossing it formed at the surface of semiconductor substrate. When it is judged that a defect is generated in the circuit by test, it is requested to irradiate a laser beam of comparatively low power, for example, with an energy of 0.3muJ to a part of wiring layer 16 located on the inclined surface for 200ns. Thereby, the wiring layer 16 partly fuses and flows along the inclined surface 17 and is disconnected. Thereby, a redundancy circuit operates. When the angle of inclined surface 17 is too gentle, the fused wiring layer 16 does not flow, while when it is too steep, the disconnection at the stepped portion occurs at the wiring layer 16.

Description

【発明の詳細な説明】 (発明の技術分野) この発明は半導体装1道に係り、特に冗長回路を備えた
半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with a redundant circuit.

(発明の技術的背景) 主回路の他にその主回路を保護するための冗長回路を備
えた半導体装置として従来第1図(al 、 (b)に
示す借造のものが知られている。P型半導体導板10表
面に主回路とこの主回路に対応する予備回路におのおの
接続するn 型の拡散層2a 、 2bが形成されてい
る。基板1上には、拡散層2a。
(Technical Background of the Invention) A semiconductor device shown in FIGS. 1A and 1B is conventionally known as a semiconductor device that includes a main circuit and a redundant circuit for protecting the main circuit. N-type diffusion layers 2a and 2b are formed on the surface of the P-type semiconductor conductor plate 10 to connect to a main circuit and a spare circuit corresponding to the main circuit, respectively.On the substrate 1, a diffusion layer 2a is formed.

2b の一部に対応する部分に開孔部3a 、 3bを
有する絶縁嘆4が被覆されている。
An insulating shell 4 having openings 3a and 3b is coated on a portion corresponding to a part of 2b.

さらに、酌縁膜4上の一部には拡散1−2a 、 2b
と開孔部3a 、 3bを介して接続されるn 型の多
結晶シリコンヒユーズ5が形成されている。このような
冗長回路を備えた半導体装置において、主回路が正常な
動作をしている時にはヒユーズ5は拡散層2a 、 2
b K接続された状態で使用されるが、不良を確認した
時は、レーザービームをヒューズ50削部6に1)は射
し、拡散層2a、2bの成気的切断をおこなうことによ
り冗長回路を作動させて半導体装(着の不良を救済する
Furthermore, diffusion 1-2a, 2b is formed on a part of the tunic membrane 4.
An n-type polycrystalline silicon fuse 5 is formed which is connected to the openings 3a and 3b through the openings 3a and 3b. In a semiconductor device equipped with such a redundant circuit, when the main circuit is operating normally, the fuse 5 is connected to the diffusion layers 2a, 2.
b It is used in a K-connected state, but if a defect is confirmed, a laser beam is irradiated on the cut portion 6 of the fuse 50 (1), and the diffusion layers 2a and 2b are chemically cut off, thereby creating a redundant circuit. Activates to relieve defects in semiconductor devices.

(h量技・釘の間i&i点) しかし、IIE米の半導体装置では、溶断に対してノヮ
ー〇)大きいレーザービームを照射する必要があるため
、周辺の素子に熱的な悪影響を与えたり、多結晶シリコ
ンヒユーズ直下の拡tftliが再拡散したり結晶欠陥
を起したりして半導体装置の特性が劣化してしまうとい
う欠点があった。
(I&I points between the nails) However, in IIE's semiconductor devices, it is necessary to irradiate a large laser beam to prevent fusing, which may have an adverse thermal effect on surrounding elements. There is a drawback that the expanded tftli directly under the polycrystalline silicon fuse re-diffuses or causes crystal defects, deteriorating the characteristics of the semiconductor device.

(発明Q)目的) この発明は、配線層の溶断を低・ぞノーでおCなえるよ
うな、し゛ト!造をHする半導体装1泊を提供するにあ
る。
(Invention Q) Purpose) This invention is an object that can eliminate the fusing of wiring layers at low cost! We offer one-night stays for semiconductor equipment that will be used for construction purposes.

(発明σ)慨安) この発明は、上記目的を達成するために、半導体基板表
面に傾斜面を有する凹部を形成し、この四部を横切って
配線層を延在させ、この傾斜面角度を111J記配線層
を加熱手段により溶融せしめた際、[」II記配線層が
14fJ記傾斜面に清って流動して溶断するように設定
したことゲ待藏とする。
(Invention σ) Summary) In order to achieve the above object, the present invention forms a recessed portion having an inclined surface on the surface of a semiconductor substrate, extends a wiring layer across the four portions, and adjusts the angle of the inclined surface to 111J. When the wiring layer is melted by the heating means, the wiring layer II is set so that it flows along the inclined surface of 14fJ and is fused.

以下この発明の寿i、’itj例を1.41j’jに基
づいて、i(’ :1.iE ’z’c、説明する。
Hereinafter, an example of the life i, 'itj of this invention will be explained based on 1.41j'j.

(発明の処施列) 第2図〜m4図は、この発明の一部7崩例に1系る半導
体装1にの1ノ造工程を示す工程別素子断面図である。
(Processing of the Invention) FIGS. 2 to 4 are cross-sectional views of elements according to each step, showing one manufacturing process of a semiconductor device 1 according to a partial example of the present invention.

まず半導体基板11の表面に、異方性エツチングにより
凹部12を形1戊し、続いて基板11の表面に主回路お
よび予備回路に接続する拡散+g 13 、14ケ形成
する。
First, one recess 12 is formed on the surface of the semiconductor substrate 11 by anisotropic etching, and then 14 diffusions +g 13 are formed on the surface of the substrate 11 to connect to the main circuit and the auxiliary circuit.

次に基板11の表面に絶縁7515を形成する。なお半
導体基板11に凹部12を形成するに際しては<1.1
)、t)>面馨有する基板11&用い、アルカリエツチ
ング等を行なえばよい。
Next, an insulator 7515 is formed on the surface of the substrate 11. In addition, when forming the recess 12 in the semiconductor substrate 11, <1.1
), t)>Using the substrate 11& having a surface roughness, alkali etching or the like may be performed.

マタ凹部12の深さはほぼ4μ程度とするのがよい。絶
縁層15にはたとえば酸化シリコンj臭を1μ程度Q)
厚さに形晟:□すればよい。
The depth of the base recess 12 is preferably approximately 4 μm. For example, the insulating layer 15 has a silicon oxide odor of about 1μQ).
Shape to thickness: □.

次に、写真蝕刻法により拡散層13 、14の一部ンて
対しC,lする部分の絶縁膜15を除去し、開孔を形成
し続いて溶融11■能な配線層(ヒユーズ)16乞被着
する。このような配線層材料として多結晶シリコンが用
いられ、そσ)際配線層の原藻は約4000λ程iと−
するのが’Mましい。配線層16として多結晶シリコン
1換を用い定場合には被着後にオキシ塩化燐(POCl
2)雰囲気中で1000°Cで10分程度熱処理してシ
リコン嗅中にリン拡散をおこない配線層16の抵抗1直
を下げる必要がある。
Next, the insulating film 15 is removed from the portions of the diffusion layers 13 and 14 by photolithography to form openings, and then the wiring layer (fuse) 16 is melted. to adhere to. Polycrystalline silicon is used as the material for such wiring layers, and the original material of the wiring layer is about 4000λ and -
It's masochistic to do that. If polycrystalline silicon is used as the wiring layer 16, phosphorous oxychloride (POCl) is used after deposition.
2) It is necessary to perform a heat treatment at 1000° C. for about 10 minutes in an atmosphere to diffuse phosphorus into the silicon to lower the resistance of the wiring layer 16.

このような処理をおこなった配l[一層16に対して写
真蝕刻法により配、’tdJIIn )ξクーンを形成
する。
A layer 16 subjected to such processing is then deposited by photolithography to form a layer 16.

なお、配、尿層161C便用される材料膜として多結晶
シリコンの池にモリブデンシリサイド(MoSi2)ま
たはアルミニウム(Al )等が同様に用いることがで
きる。
It should be noted that molybdenum silicide (MoSi2) or aluminum (Al2) or the like can be similarly used for the polycrystalline silicon layer as the material film used for the urine layer 161C.

なおモリブデンシリサイドやアルミニウム等を用いfこ
、)M合には燐拡散等の熱処理によって配、峠層16σ
〕抵抗1直を下げる公安がない。
If molybdenum silicide, aluminum, etc. are used, heat treatment such as phosphorus diffusion is applied to form a pass layer of 16σ.
] There is no public security to lower the resistance.

このように形成すると半畳体系板表面に形成され1こ凹
部12ケ横切って配置線1−16が延在する工うな14
造ができ土る。とくに凹部12上では配+im層16が
そのIL頁カ、斗面に(Hつでy山荘した噸・イ遺とな
7D。
When formed in this way, a groove 14 is formed on the surface of the semi-concave body plate, and the arrangement line 1-16 extends across the 12 recesses.
The construction is completed and the soil is built. In particular, on the concave portion 12, the layer 16 is on the IL page, and on the dou surface (7D).

このようなト(1η造を有すΦ半tit体模1直におい
て装置の1ぺ能または性能乞試翳すゐことにより回1塔
に不良が生じたとト:]断した時は、唄γ[面の土に立
f(1する配薩層160)一部に例えばエネルギlJ、
3μJのレーザビームを20Qns 畷、射すると第4
図に示した。J、5に配線層I6の一部が溶融して:′
頃斜mロアに省って++lu励し、明断されて冗長回路
が動作することになる。
When it is determined that a defect has occurred in the 1st column due to the 1st performance or performance test of the equipment in 1st shift of Φ half tit body with 1η structure, [For example, energy lJ is applied to a part of the soil on the surface f (1 layer 160),
When a 3μJ laser beam is emitted for 20Qns, the fourth
Shown in the figure. A part of the wiring layer I6 is melted at J, 5:'
The redundant circuit is activated by excitation ++lu by omitting it to the lower diagonal m and disconnecting it.

なお、傾斜面の角度はレーザビームの照射時に配線層が
溶7gしてそ17)傾斜にτ實って流動して切断されろ
↑“を展の角度にする必要がある。角度が75まりなだ
らかすぎると溶融した配線層16が0’II動化せずま
たあまり角度が急すぎろと配、宵層の段切れンおこして
しまう。
In addition, the angle of the inclined surface must be such that the wiring layer melts 7g when irradiated with the laser beam, and then 17) ↑'' is the unfolding angle. If the angle is too steep, the melted wiring layer 16 will not move to 0'II, and if the angle is too steep, it will cause a break in the layer.

したがってY1閥しfこヒユーズ材料がびこ動するに必
要な傾斜を与えろ下地構造として凹部r形成する必要が
ある。
Therefore, it is necessary to form a recess r as an underlying structure to provide the slope necessary for the movement of the fuse material in the Y1 section.

また配線層のd融はレーザービーム照射に限らず成子ビ
ーム照射またはこの配線ノー16に4眠することにより
ジュール熱により寸になりようにしてもよい。
Further, the d-melting of the wiring layer is not limited to laser beam irradiation, but may be caused by Joule heat by irradiation with a laser beam or by immersing the wiring layer in the wiring layer 16.

(発明σ)効果) 以上実桶例に基づいて詳細に一湿間したように、Cの発
明では加熱手段により溶鷹された配?9層材料が流q(
Q化して配線を切断−J−るように構成したσ]で、低
ノξワーで下容融が可能であり、このため近傍σ)素子
への熱的悪影響を低減できるといつ利点がある。
(Invention σ) Effect) As described above in detail based on the actual bucket example, in the invention C, the liquid is melted by heating means. The 9-layer material flows q(
It is possible to melt the lower layer at a low ξ power with a σ] configured to cut the wiring by converting it into a .

したがって、配線層と素子間とり)距1柚を従来α)半
導体装置に比べて短くできろため素子の小fR度を高め
ることができる。
Therefore, since the distance between the wiring layer and the element can be made shorter than that of the conventional semiconductor device, the small fR of the element can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体装1(のくIt造を示す断面図
および平面図、第2図、第3図、第4図はこQ)発明の
−−バ剣例に係る千尋体装置ρの製造工程を示す工程別
素子断面図である。 11・・・半導体基板、12・・・四部、13 、14
・・・拡散層、15・・・触縁層、16・・・配・Tイ
層、17・・・傾斜面。 弗1 図 3°)    フ 花2図 2 4− 第3図 4− 市4図
FIG. 1 shows a conventional semiconductor device 1 (a sectional view and a plan view showing the structure of the semiconductor device, and FIGS. 2, 3, and 4 are shown in FIG. 4). FIG. 3 is a step-by-step device cross-sectional view showing the manufacturing process of ρ. 11... Semiconductor substrate, 12... Four parts, 13, 14
. . . Diffusion layer, 15 . . . Edge layer, 16 . . . T layer, 17 . . . Slanted surface.弗 1 fig. 3°) Fuhana 2 fig. 2 4- fig. 3 4- ichi fig. 4

Claims (1)

【特許請求の範囲】 ■、半導体基板表面に形成された傾斜面を仔する凹部と
、この凹部を横切って延在する配線層とを有する半導体
装置において、前記傾斜面角度を前記配線層を加熱手段
により溶融せしめた際前記配線層が前記傾斜面にそって
流動して断線するように設定した事を特徴とする半導体
装置。 2、前記配a層が多結晶シリコン層、MOSi2または
AI 層であることを特徴とする特許請求の範囲第1項
記載の半導体装置。 3前記加熱手段がレーザビーム照射、電子ビーム照射ま
たは前記配線層に対する通電によりおこなわれることを
特徴とする特許請求の範囲第1項記載の半導体装置。
[Scope of Claims] (2) In a semiconductor device having a recess having an inclined surface formed on a surface of a semiconductor substrate, and a wiring layer extending across the recess, the wiring layer is heated to adjust the angle of the inclined surface. A semiconductor device characterized in that the wiring layer is configured to flow along the slope and break when melted by means. 2. The semiconductor device according to claim 1, wherein the a-layer is a polycrystalline silicon layer, a MOSi2 layer, or an AI layer. 3. The semiconductor device according to claim 1, wherein the heating means is performed by laser beam irradiation, electron beam irradiation, or energization of the wiring layer.
JP9095482A 1982-05-28 1982-05-28 Semiconductor device Pending JPS58207665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9095482A JPS58207665A (en) 1982-05-28 1982-05-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9095482A JPS58207665A (en) 1982-05-28 1982-05-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58207665A true JPS58207665A (en) 1983-12-03

Family

ID=14012874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9095482A Pending JPS58207665A (en) 1982-05-28 1982-05-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58207665A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0083211A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Semiconductor device with fuse
JPS6344738A (en) * 1986-08-12 1988-02-25 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0083211A2 (en) * 1981-12-28 1983-07-06 Fujitsu Limited Semiconductor device with fuse
JPS6344738A (en) * 1986-08-12 1988-02-25 Fujitsu Ltd Manufacture of semiconductor device

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