JPS62119938A - Semiconductor device provided with redundancy circuit - Google Patents
Semiconductor device provided with redundancy circuitInfo
- Publication number
- JPS62119938A JPS62119938A JP26019485A JP26019485A JPS62119938A JP S62119938 A JPS62119938 A JP S62119938A JP 26019485 A JP26019485 A JP 26019485A JP 26019485 A JP26019485 A JP 26019485A JP S62119938 A JPS62119938 A JP S62119938A
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- semiconductor device
- redundancy circuit
- melting point
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は大規模集積回路(VLSI)に関し、特に高
集積記憶素子における冗長性回路の構造に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to large scale integrated circuits (VLSI), and more particularly to the structure of redundancy circuits in highly integrated memory devices.
第2図は従来の冗長性回路を備えた半導体装置を示す断
面図である。図において、lは例えばシリコン(St)
などの基板、2は該基板1上に形成された例えばシリコ
ン酸化膜(SIO□膜)などの絶縁膜、3は冗長性回路
のためのヒユーズ用配線であり、これは多結晶シリコン
膜(ポリシリコン膜)3aあるいは高融点金属シリサイ
ド膜(以下、Rメタルシリサイド膜と記す)3bからな
る単層膜であり、これは第2図(b)に示すような上記
の両者からなる2層膜でもよい。5は眉間絶縁用の例え
ばCVD法などで形成される絶縁膜で、これはリン、ボ
ロンなどを含むstow膜からなっている。8はヒユー
ズ用配線3を溶断するためのレーザー光、6は該レーザ
ー光8などによりヒユーズ用配線3を切断するために形
成された絶縁膜5の開口部、9は上記レーザー光8によ
り溶断されたヒユーズ用配線3の部分である。FIG. 2 is a sectional view showing a semiconductor device equipped with a conventional redundancy circuit. In the figure, l is silicon (St), for example.
2 is an insulating film such as a silicon oxide film (SIO□ film) formed on the substrate 1; 3 is a fuse wiring for a redundancy circuit; this is a polycrystalline silicon film (polycrystalline silicon film); It is a single layer film consisting of a silicon film) 3a or a high melting point metal silicide film (hereinafter referred to as R metal silicide film) 3b, and it can also be a two-layer film consisting of both of the above as shown in FIG. 2(b). good. Reference numeral 5 denotes an insulating film formed by, for example, a CVD method for insulating between the eyebrows, and is made of a stow film containing phosphorus, boron, etc. 8 is a laser beam for cutting the fuse wiring 3; 6 is an opening in the insulating film 5 formed to cut the fuse wiring 3 by the laser beam 8; and 9 is an opening for cutting the fuse wiring 3 by the laser beam 8. This is the part of the fuse wiring 3.
次に動作について説明する。第2図(C)に示す如くヒ
ユーズ用配線3の所望の部分を溶断するには、上記ヒユ
ーズ用配vA3に電流を流し、そのジュール熱により溶
断するか、又はレーザー光8を絶縁膜5の開口部6を通
してヒユーズ用配線3の表面に照射し、そのエネルギー
により溶断する。こうして所望の不良ビット線、不良ワ
ード線を切断する。Next, the operation will be explained. In order to blow out a desired portion of the fuse wiring 3 as shown in FIG. The surface of the fuse wiring 3 is irradiated through the opening 6 and blown by the energy. In this way, desired defective bit lines and defective word lines are cut.
従来の冗長性回路に用いるヒユーズ用配線は以上のよう
にポリシリコンあるいはRメタルシリサイドからなる単
層膜、またはポリシリコンとRメタルシリサイドからな
る2層膜であったが、このような冗長性回路を備えた半
導体装置において、実際にヒユーズを切断し冗長性回路
を有する素子の歩留を向上させるためには、電気又はレ
ーザー光のどちらを用いるにしても、ある閾値以上の十
分なエネルギーを所望のヒユーズ用配線部分に与えて溶
断させる事が必要である。しかしヒユーズ切断の際の単
位面積当りの印加エネルギー密度には最低限度があるだ
けでなく、最高限度もある。As mentioned above, fuse wiring used in conventional redundancy circuits has been a single-layer film made of polysilicon or R-metal silicide, or a two-layer film made of polysilicon and R-metal silicide. In order to actually cut fuses and improve the yield of devices with redundant circuits in semiconductor devices equipped with It is necessary to apply it to the fuse wiring part to blow it out. However, there is not only a minimum limit but also a maximum limit to the applied energy density per unit area when cutting a fuse.
これは過剰なエネルギーをヒユーズに印加すると、ヒユ
ーズ下の絶縁膜2さらには基板1また周辺の素子や設計
パターンにまでダメージを与え、結局そのチップを不良
とするか、もしくは良品となっても信頼性上悪影響を与
えるためである。This means that if excessive energy is applied to the fuse, it will damage the insulating film 2 under the fuse, the substrate 1, and the surrounding elements and design patterns, resulting in the chip becoming defective, or even if it is a good chip, it is not reliable. This is because it has an adverse effect on sex.
即ち、従来のヒユーズ材料にはポリシリコンやRメタル
シリサイド等の非常に融点の高い物質(表−1にその代
表的な材料の融点、を示す。)を用いており、特にRメ
タルシリサイドを用いた場合は、印加エネルギー密度の
最低限度が高い。一方、素子の高密度、高集積化が進む
に従い、横方向および縦方向構造の微細化が進行する結
果、ヒユーズ間同志やヒユーズと近接する配線、接合。In other words, conventional fuse materials use materials with extremely high melting points such as polysilicon and R metal silicide (Table 1 shows the melting points of typical materials). If so, the minimum applied energy density is high. On the other hand, as the density and integration of devices progresses, the horizontal and vertical structures become finer, resulting in smaller wiring and junctions between fuses and in close proximity to fuses.
トランジスタ電極又は素子間分離絶縁膜との間隔が短く
なり、またヒユーズ下の1!l縁膜2の膜厚も薄くなる
ため、ヒユーズ切断におけるダメージを低減する必要が
生じてきており、従って印加エネルギー密度の最高限度
は低下しつつある。以上のような理由により、従来の冗
長性回路においては、ヒユーズ切断のための適正印加エ
ネルギー密度に対する許容範囲が非常に狭くなるという
問題点があった。The distance between the transistor electrode or the element isolation insulating film is shortened, and the 1! As the thickness of the edge film 2 becomes thinner, it becomes necessary to reduce damage caused by fuse cutting, and therefore the maximum applied energy density is being lowered. For the above reasons, the conventional redundancy circuit has a problem in that the allowable range for the appropriate applied energy density for cutting the fuse is extremely narrow.
この発明は上記のような問題点を解消するためになされ
たもので、印加エネルギー密度に対する許容範囲が非常
に広く、VLSIにおいてもヒユーズ切断の際に周辺の
素子等にダメージを与えることのない冗長性回路を備え
た半導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and has a very wide tolerance range for applied energy density, and even in VLSI, it is a redundant system that does not damage surrounding elements when cutting a fuse. The purpose of the present invention is to obtain a semiconductor device equipped with a functional circuit.
この発明に係る冗長性回路を備えた半導体装置は、ヒユ
ーズ材料としてMo、W、Cr又はVを用いたものであ
る。A semiconductor device equipped with a redundancy circuit according to the present invention uses Mo, W, Cr, or V as a fuse material.
この発明においては、Mo、W、Cr又はVからなるヒ
ユーズ用配線は、通電又はレーザー光照射により加熱さ
れると同時に酸化性雰囲気に置かれることにより非常に
低融点の酸化物を形成するので、これは本来単体金属と
しては非常に融点の高い物質であるにもかかわらず、酸
化物となって比較的印加エネルギー密度の低い条件で融
解、除去され、切断される。In this invention, the fuse wiring made of Mo, W, Cr, or V forms an oxide with a very low melting point by being heated by electricity or laser beam irradiation and at the same time being placed in an oxidizing atmosphere. Although this substance originally has a very high melting point as a single metal, it becomes an oxide and is melted, removed, and cut under conditions of relatively low applied energy density.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例による冗長性回路を備えた半
導体装置の断面構造を示し、図において、第2図と同一
符号は同一部分を示す。7はM o 。FIG. 1 shows a cross-sectional structure of a semiconductor device equipped with a redundancy circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 2 indicate the same parts. 7 is Mo.
W、Cr又はVからなるヒユーズ用配線である。This is fuse wiring made of W, Cr, or V.
表−1に示すように、これらMo、W、Cr又はVは高
融点金属の一種であり、融点の非常に高い物質であるが
、その酸化物であるMoO,、WO。As shown in Table 1, these Mo, W, Cr or V are a type of refractory metal and are substances with very high melting points, and their oxides MoO, WO.
(x = 2 + 3 ) 、Cr 02又はVtO
,の融点は低く、しかもMO02、’NOsは揮発性物
質である。(x = 2 + 3) , Cr 02 or VtO
, has a low melting point, and MO02,'NOs is a volatile substance.
次に作用効果について説明する。ヒユーズ用配線3の所
望の部分に酸化性雰囲気中でレーザー光8を照射すると
、該部分のMo、W、Cr又はVは酸化されてそれぞれ
融点の低い酸化物であるMo 03 、 WOX、
Cr Os 、 Vt Osに変化するとともに上記レ
ーザー光の照射により融解・除去される。この時、上記
酸化物の融点は従来のヒユーズ材料の融点よりも低いの
で、従来に比ベヒューズ切断に必要な最低印加エネルギ
ー密度値は小さくなる。従って、ヒユーズ切断のための
適正印加エネルギー密度の許容範囲は非常に大きくなり
、ヒユーズ周辺の素子や設計パターンに与えるダメ表−
1
−ジを十分抑えることができる。Next, the effects will be explained. When a desired part of the fuse wiring 3 is irradiated with laser light 8 in an oxidizing atmosphere, Mo, W, Cr, or V in the part is oxidized and becomes an oxide with a low melting point such as Mo 03 , WOX,
It changes into CrOs and VtOs, and is melted and removed by irradiation with the laser beam. At this time, since the melting point of the oxide is lower than the melting point of conventional fuse materials, the minimum applied energy density value required for cutting the fuse becomes smaller than in the past. Therefore, the allowable range of the appropriate applied energy density for cutting the fuse is very large, and the damage caused to the elements and design patterns around the fuse is very large.
1 - can be sufficiently suppressed.
以上のように、この発明によれば冗長性回路のためのヒ
ユーズ用配線の材料として、Mo、W。As described above, according to the present invention, Mo and W can be used as materials for fuse wiring for redundancy circuits.
Cr又は■を用いたので、このヒユーズ材料は切断の際
酸化性雰囲気で加熱されて融点の低い酸化物となること
となり、このため非常な低エネルギーでヒユーズの切断
が可能となって素子に与えるダメージを低減でき、かつ
ヒユーズ周辺の設計パターンマージンを向上できる効果
がある。Since Cr or ■ is used, this fuse material is heated in an oxidizing atmosphere during cutting and turns into an oxide with a low melting point, which makes it possible to cut the fuse with very low energy, which gives less energy to the device. This has the effect of reducing damage and improving the design pattern margin around the fuse.
第1図はこの発明の一実施例による冗長性回路を備えた
半導体装置を示す断面側面図、第2図は従来の冗長性回
路を備えた半導体装置を示す断面側面図である。
図において、7はMo、W、Cr又は■からなるヒユー
ズ用配線である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional side view showing a semiconductor device equipped with a redundancy circuit according to an embodiment of the present invention, and FIG. 2 is a cross-sectional side view showing a semiconductor device equipped with a conventional redundancy circuit. In the figure, 7 is a fuse wiring made of Mo, W, Cr, or ■. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (2)
配線材料が、高融点金属からなることを特徴とする冗長
性回路を備えた半導体装置。(1) A semiconductor device equipped with a redundancy circuit, characterized in that the wiring material of a fuse for the redundancy circuit of a semiconductor memory element is made of a high melting point metal.
ン(W)、クロム(Cr)又はバナジウム(V)である
ことを特徴する特許請求の範囲第1項記載の冗長性回路
を備えた半導体装置。(2) A semiconductor device equipped with a redundancy circuit according to claim 1, wherein the high melting point metal is molybdenum (Mo), tungsten (W), chromium (Cr), or vanadium (V). .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26019485A JPS62119938A (en) | 1985-11-20 | 1985-11-20 | Semiconductor device provided with redundancy circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26019485A JPS62119938A (en) | 1985-11-20 | 1985-11-20 | Semiconductor device provided with redundancy circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62119938A true JPS62119938A (en) | 1987-06-01 |
Family
ID=17344634
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26019485A Pending JPS62119938A (en) | 1985-11-20 | 1985-11-20 | Semiconductor device provided with redundancy circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62119938A (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0249450A (en) * | 1988-03-18 | 1990-02-19 | Digital Equip Corp <Dec> | Integrated circuit having metallized layer reformable by laser |
JPH03106055A (en) * | 1989-09-20 | 1991-05-02 | Nippondenso Co Ltd | Semiconductor device and manufacture thereof |
JPH03138963A (en) * | 1989-10-24 | 1991-06-13 | Seikosha Co Ltd | Semiconductor device |
US5025300A (en) * | 1989-06-30 | 1991-06-18 | At&T Bell Laboratories | Integrated circuits having improved fusible links |
US5070392A (en) * | 1988-03-18 | 1991-12-03 | Digital Equipment Corporation | Integrated circuit having laser-alterable metallization layer |
US5360988A (en) * | 1991-06-27 | 1994-11-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and methods for production thereof |
JPH0846050A (en) * | 1994-08-01 | 1996-02-16 | Nec Corp | Semiconductor memory and its manufacture |
US6078091A (en) * | 1998-04-22 | 2000-06-20 | Clear Logic, Inc. | Inter-conductive layer fuse for integrated circuits |
US20130066294A1 (en) * | 2011-09-08 | 2013-03-14 | Kiyohiro WAKE | Antimicrobial pouch |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5892252A (en) * | 1981-11-27 | 1983-06-01 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS5918658A (en) * | 1982-07-22 | 1984-01-31 | Nec Corp | Semiconductor integrated circuit device |
-
1985
- 1985-11-20 JP JP26019485A patent/JPS62119938A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5892252A (en) * | 1981-11-27 | 1983-06-01 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS5918658A (en) * | 1982-07-22 | 1984-01-31 | Nec Corp | Semiconductor integrated circuit device |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0249450A (en) * | 1988-03-18 | 1990-02-19 | Digital Equip Corp <Dec> | Integrated circuit having metallized layer reformable by laser |
US5070392A (en) * | 1988-03-18 | 1991-12-03 | Digital Equipment Corporation | Integrated circuit having laser-alterable metallization layer |
US5025300A (en) * | 1989-06-30 | 1991-06-18 | At&T Bell Laboratories | Integrated circuits having improved fusible links |
JPH03106055A (en) * | 1989-09-20 | 1991-05-02 | Nippondenso Co Ltd | Semiconductor device and manufacture thereof |
JPH03138963A (en) * | 1989-10-24 | 1991-06-13 | Seikosha Co Ltd | Semiconductor device |
US5360988A (en) * | 1991-06-27 | 1994-11-01 | Hitachi, Ltd. | Semiconductor integrated circuit device and methods for production thereof |
US5519658A (en) * | 1991-06-27 | 1996-05-21 | Hitachi, Ltd. | Semiconductor integrated circuit device and methods for production thereof |
JPH0846050A (en) * | 1994-08-01 | 1996-02-16 | Nec Corp | Semiconductor memory and its manufacture |
US5627400A (en) * | 1994-08-01 | 1997-05-06 | Nec Corporation | Semiconductor memory device |
US6078091A (en) * | 1998-04-22 | 2000-06-20 | Clear Logic, Inc. | Inter-conductive layer fuse for integrated circuits |
US20130066294A1 (en) * | 2011-09-08 | 2013-03-14 | Kiyohiro WAKE | Antimicrobial pouch |
US9078434B2 (en) * | 2011-09-08 | 2015-07-14 | Kiyohiro WAKE | Antimicrobial pouch |
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