JPS58182851A - Semiconductor device for connecting redundancy circuit - Google Patents
Semiconductor device for connecting redundancy circuitInfo
- Publication number
- JPS58182851A JPS58182851A JP57068222A JP6822282A JPS58182851A JP S58182851 A JPS58182851 A JP S58182851A JP 57068222 A JP57068222 A JP 57068222A JP 6822282 A JP6822282 A JP 6822282A JP S58182851 A JPS58182851 A JP S58182851A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- film
- circuit
- layer
- redundancy circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 230000002950 deficient Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000009413 insulation Methods 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、大容量半導体メモリにおいて使用される不良
ビットを救済するための冗長回路の接続を、レーザ光を
用いてできるようにした冗長ＩＩ−Ｉ回路接回路接続用
半導体開直るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a redundant II-I circuit connection circuit that uses laser light to connect redundant circuits for relieving defective bits used in large-capacity semiconductor memories. This is a revolution in semiconductors.
従来、大容量半導体メモリにおいて不良ビット発生個所
を分離するための装置として第１図、第２図に示すもの
があった。第１図において′ｒ１〜Ｔ４はＭＯＳトラン
ジスタ、Ａ１−Ａ３は入力信号で、点線で囲った部分Ｆ
は従来レーザプログラムされている、即ちレーザ光によ
り切断できるポリシリコン配線で節ＮとＷｉＰとを分離
する。第２図はこのポリシリコン配線Ｆの平面図であり
、この中央部をレーザ光によって切断することによって
節ＰとＮとを分離できる。Conventionally, there have been devices shown in FIGS. 1 and 2 as devices for isolating locations where defective bits occur in large-capacity semiconductor memories. In Figure 1, 'r1 to T4 are MOS transistors, A1 to A3 are input signals, and the part F surrounded by a dotted line
The node N and the WiP are separated by a polysilicon wiring which is conventionally laser programmed, that is, can be cut by a laser beam. FIG. 2 is a plan view of this polysilicon wiring F, and nodes P and N can be separated by cutting the central portion with a laser beam.
第１図はＮＯＲ回路であるが、これはデコーダ回路とし
て多用されている。このデコーダ回路の動作説明は省略
するが、このデコーダ回路の一部またはこのデコーダ四
路ｌこよって選択されるメモリセルか欠陥により不良と
なる場合、このデコーダ回路を切り離す必要がある。こ
のため点線で囲んだ部分にポリシリコン等の金属配線Ｆ
を設けて、この部分にレーザ光を当て切断する。そして
あらかじめ設けておいたスペア（冗長）デコーダ回路と
そわに接続されたメモリセルに直き換えることによって
不良チップを救済する。FIG. 1 shows a NOR circuit, which is often used as a decoder circuit. Although a description of the operation of this decoder circuit will be omitted, if a part of this decoder circuit or a memory cell selected by this decoder circuit becomes defective due to a defect, it is necessary to disconnect this decoder circuit. For this reason, metal wiring F such as polysilicon is placed in the area surrounded by the dotted line.
A laser beam is applied to this part to cut it. The defective chip is then rescued by directly replacing it with a memory cell that is connected to a spare (redundant) decoder circuit that has been provided in advance.
従来の第２図の方式は以上のように構成されており、不
良個所を分離するには非常に便利であるが、それと直換
するための回路を接続するためには第１■１のように面
早にはいかす、回路が複雑となっていた。The conventional method shown in Figure 2 is configured as described above, and is very convenient for isolating defective parts, but in order to connect a circuit for direct replacement, it is necessary to However, the circuit quickly became complicated.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、拡散１曽と配線との間を薄いＳ
ｉ Ｏ，絶縁膜で分離しておき、レーザー光によりこの
絶縁１−膜を破壊することにより、拡散１曽と配線とを
接続して不良個所を冗長回路と直換することのできる冗
長回路接続用半導体装置を提供することを目的としてい
る。This invention was made in order to eliminate the drawbacks of the conventional ones as described above.
i O, redundant circuit connection that connects the diffusion layer and the wiring by separating it with an insulating film and destroying this insulation film with laser light, and directly replacing the defective part with a redundant circuit. The purpose is to provide semiconductor devices for
以上、この発明の一実施例を図について説明する。An embodiment of the present invention will be described above with reference to the drawings.
％３図は本発明の一実施イ※りによる冗長回路接続用半
導体装置を示す。図において、Ｐはポリシリコン配置３
、ＳはＰ５ンリコン基板、ＮはＮ＋拡散−１０は酸化膜
、Ｚは薄い絶縁１曽膜である。Figure 3 shows a semiconductor device for redundant circuit connection according to one embodiment of the present invention. In the figure, P is polysilicon arrangement 3
, S is a P5 silicon substrate, N is an N+ diffusion, -10 is an oxide film, and Z is a thin insulating film.
第４ ｒ＋は第３図１の構造を用いたスペアデコーダ回
路であり、拡ｈ＋ｔｉＮとポリシリコン配線Ｐとは分離
されている。冗長回路］妾続時には第３図のＰｌ−とｚ
ｒｔｍとＮ喘とが小なっている部分（こレーザ光を当
て絶縁＋＋＊ ｚを破壊し、Ｎ Ｋ散１曽Ｎとポリシリ
コン配線Ｐとを接続する。The fourth r+ is a spare decoder circuit using the structure shown in FIG. 3, and the expanded h+tiN and polysilicon wiring P are separated. Redundant circuit] When concubinage, Pl- and z in Figure 3
The part where rtm and N are small (this part is irradiated with a laser beam to destroy the insulation ++*z, and the NK dispersion 1 and the polysilicon wiring P are connected.
以上のように、この発明］こよれは、拡散層と配線との
曲に薄い絶縁１山膜を形成し、レーザ光によりこの絶縁
１一般を破壊することにより拡散−と配線とを接続する
ようにしたので、不良ビットの救済を行う回路を容易に
構成することができる効果がある。As described above, the present invention is to form a thin insulating film on the curve between the diffusion layer and the wiring, and to connect the diffusion layer and the wiring by destroying this insulation 1 with laser light. Therefore, it is possible to easily configure a circuit for repairing defective bits.
第１図は従来の半４体メモリに使用されるデコーダ回路
の回路図、第２図は絶縁膜上に形成されたポリシリコン
配線の平面図、第３図は本発明の一実施例による冗長回
路接続用半導体装−を示す断面図、第４図は第３図の構
造を用いたスペアデコーダを示す回路図である。
Ｓ・・・シリコン基板、Ｎ・・・Ｎ＋拡散１％、Ｐ・・
・ポリシリコン配線、Ｚ・・・絶縁１餉膜（薄い絶縁膜
）。
なお図中同一符号は同−又は相当部分を示す。
代理人 鴎野 信−
第１図
第２図
第３図
第４図FIG. 1 is a circuit diagram of a decoder circuit used in a conventional half-quad memory, FIG. 2 is a plan view of polysilicon wiring formed on an insulating film, and FIG. 3 is a redundant circuit according to an embodiment of the present invention. 4 is a sectional view showing a semiconductor device for circuit connection, and FIG. 4 is a circuit diagram showing a spare decoder using the structure of FIG. 3. S...Silicon substrate, N...N+ diffusion 1%, P...
・Polysilicon wiring, Z...Insulation 1 layer (thin insulation film). Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Makoto Kamino - Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
された拡散−と、この拡散−十に形成された薄い絶縁膜
と、この薄い絶縁膜上に形成された配線とを備え、冗長
回路接続時に上記薄い絶縁膜をレーザ光で破壊して上記
拡散層と上記配線とを接続するようにしたことを特徴と
する冗長回路接続用半導体装置。(1) A four-layer substrate, a diffusion layer formed on the substrate, a thin insulating film formed on the diffusion layer, and wiring formed on the thin insulating film. . A semiconductor device for connecting a redundant circuit, characterized in that the thin insulating film is destroyed by laser light to connect the diffusion layer and the wiring when connecting the redundant circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068222A JPS58182851A (en) | 1982-04-21 | 1982-04-21 | Semiconductor device for connecting redundancy circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57068222A JPS58182851A (en) | 1982-04-21 | 1982-04-21 | Semiconductor device for connecting redundancy circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58182851A true JPS58182851A (en) | 1983-10-25 |
Family
ID=13367559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57068222A Pending JPS58182851A (en) | 1982-04-21 | 1982-04-21 | Semiconductor device for connecting redundancy circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182851A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489538A (en) * | 1987-07-02 | 1989-04-04 | Bull Sa | Method of connecting conductor to doped region of ic substrate by laser, and ics in the method |
| US5231050A (en) * | 1987-07-02 | 1993-07-27 | Bull, S.A. | Method of laser connection of a conductor to a doped region of the substrate of an integrated circuit |
| US5281553A (en) * | 1987-07-02 | 1994-01-25 | Bull, S.A. | Method for controlling the state of conduction of an MOS transistor of an integrated circuit |
| US5528072A (en) * | 1987-07-02 | 1996-06-18 | Bull, S.A. | Integrated circuit having a laser connection of a conductor to a doped region of the integrated circuit |
-
1982
- 1982-04-21 JP JP57068222A patent/JPS58182851A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489538A (en) * | 1987-07-02 | 1989-04-04 | Bull Sa | Method of connecting conductor to doped region of ic substrate by laser, and ics in the method |
| US5231050A (en) * | 1987-07-02 | 1993-07-27 | Bull, S.A. | Method of laser connection of a conductor to a doped region of the substrate of an integrated circuit |
| US5281553A (en) * | 1987-07-02 | 1994-01-25 | Bull, S.A. | Method for controlling the state of conduction of an MOS transistor of an integrated circuit |
| US5528072A (en) * | 1987-07-02 | 1996-06-18 | Bull, S.A. | Integrated circuit having a laser connection of a conductor to a doped region of the integrated circuit |
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