JPS5892252A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5892252A JPS5892252A JP56190353A JP19035381A JPS5892252A JP S5892252 A JPS5892252 A JP S5892252A JP 56190353 A JP56190353 A JP 56190353A JP 19035381 A JP19035381 A JP 19035381A JP S5892252 A JPS5892252 A JP S5892252A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- cutting
- insulation film
- semiconductor device
- cut
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
【発明の詳細な説明】
(1)発明の技術分野
本発明は半導体装置、特に配線を選択的に切断すること
にエリプログラミングされる読出し専用記憶装置(FR
OM)、及び冗長ビットを切断する記憶装置の製造方法
に関す。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, particularly a read-only memory device (FR) that is reprogrammed by selectively cutting wiring.
OM) and a method for manufacturing a storage device that cuts redundant bits.
(2)従来技術と問題点
従来技術においてFROMのプログラミングを行う方法
の一つに、ピッ)fstたはツー11m配−を大1゛流
に↓り溶断する方法がある。この場合には切断ぐべき位
置において例えば多結晶シリコン層エリなる配線は予め
細°〈薄く形成されるが、かかるシリコン層を溶断する
ためには一般の使用例に比較してかなり大きい電力が必
要とされて、しかも必要なiir流の値が確定的でない
ために処理の再現性が乏しい。丈にシリコン層は熔融に
よって切断されるために、切断位置の周囲にシリコンが
飛散付着して場合にLっでは短絡の危険を伴う。(2) Prior Art and Problems One of the methods for programming FROM in the prior art is to fuse the pin/fst or two 11m wiring in a large scale. In this case, the wiring, such as the polycrystalline silicon layer area, is formed in advance to be thin at the location where it is to be cut, but in order to melt such a silicon layer, a considerably larger amount of power is required than in the case of general use. Moreover, since the value of the necessary iir flow is not definite, the reproducibility of the process is poor. Since the silicon layer is cut by melting, there is a risk of a short circuit in L if the silicon scatters and adheres around the cut position.
父、前記FROMの他にメモリ書換え機能を有する記憶
装置(RWM)においても、予め冗長ビットを形成して
おき、]E!tlt紫子製造工程の終りに余剰の冗長ビ
ットを選択的に切断することが行われるが、この場合の
配線の切断に関しても前PFROMの配線の切断上同様
の方法が従来行われている。Father, in addition to the above-mentioned FROM, a memory device (RWM) having a memory rewriting function also has redundant bits formed in advance,]E! At the end of the tlt purple manufacturing process, surplus redundant bits are selectively cut off, and the same method used for cutting the wires of the previous PFROM has been conventionally used for cutting the wires in this case.
また例えばFROMについて、そのプログラミングを素
子製造工程の流れを一部プールして実施する場合等にお
いて、配線パターン等の保護のために、配線形成俵速に
絶縁膜にて被覆することが望ましいが、絶#l1il被
覆下で前記従来の方法により配線の切断を行った場合に
は1線の切断の信頼度が低く、通常は絶l#膿による配
線パターンの波長以前に、もしくは、絶縁膜の所要部分
に開口を設けて前記従来技術による配線の切断を行って
いる、
(3)発明の目的
本発明の目的は、配線パターンの形成後読配線の一部を
選択的に切断する半導体装置の製造方法において、し配
線を絶縁膜にエリ破覆した後に、切断に要するパワーを
蚊半導体装董を構成する他の素子を介することなく切断
部に与えて、該配線の切断に伴う飛敗物を該半導体装置
に付着させることのない、該配線の切断方法を得るとと
にある。Furthermore, for example, when programming a FROM by pooling part of the flow of the element manufacturing process, it is desirable to cover the wiring pattern with an insulating film as soon as the wiring is formed, in order to protect the wiring pattern, etc. When wiring is cut using the conventional method described above under a high-temperature coating, the reliability of cutting a single wire is low, and usually the wavelength of the wiring pattern due to high-temperature pus is reached or the required amount of the insulating film is cut. (3) Object of the Invention An object of the present invention is to manufacture a semiconductor device in which a part of the wiring is selectively cut after formation of a wiring pattern. In this method, after the wiring is blown into the insulating film, the power required for cutting is applied to the cutting part without going through other elements constituting the mosquito semiconductor device, thereby eliminating debris caused by cutting the wiring. An object of the present invention is to obtain a method for cutting the wiring without causing the wiring to adhere to the semiconductor device.
(4)発明の構成
本発明の前記目的は、切断する可能性のある配線の少く
とも一部をモリブデン(Mo)、タンクン
スゝヂでW)、チタン(Ti )、バナジウム(V)。(4) Structure of the Invention The object of the present invention is to remove at least a portion of the wiring that may be cut using materials such as molybdenum (Mo), titanium (Ti), and vanadium (V).
クロム(Cr)、鉄(Fe )、コバルト(Co)。Chromium (Cr), iron (Fe), cobalt (Co).
ニッケル(NI)、ジルコニウム(Zr)、ニオブ(N
b)、ルテニウム(Ru)、ロジウム(Rh)、パラジ
ウム(Pd )、ハフニウム(Hf)。Nickel (NI), zirconium (Zr), niobium (N
b), Ruthenium (Ru), Rhodium (Rh), Palladium (Pd), Hafnium (Hf).
タンタル(Ta)、オスミウム(Os )、イリジウム
(Ir)、白金(Pt )のうちから選ばれた少なくと
も一種の金属又は該金属の合金により形成し、該配線を
被覆する絶縁膜を形成した後に、該絶縁Bを介してエネ
ルギSを湘射することにより、該金属又は合金の少くと
も一部を選択的に加熱して化合物として昇華せしめて核
配線を切断することにエリ連取される。After forming an insulating film made of at least one metal selected from tantalum (Ta), osmium (Os), iridium (Ir), and platinum (Pt) or an alloy of the metal, and covering the wiring, By injecting energy S through the insulation B, at least a portion of the metal or alloy is selectively heated and sublimated as a compound, which is effective in cutting the nuclear wiring.
(5) 発明の実施例
以下、本発明を実施例により図面を参照して具体的に説
明する。(5) Embodiments of the Invention The present invention will be specifically described below using embodiments with reference to the drawings.
第1図1こ本発明の実施例の断面図を示す。第1図にお
いて、1は下地である二酸化シリコン(SiOl)層で
あり、選択的に切断する可能性のある配@2は、化学気
相成長法(ehemicatvapordeposit
ion +以下CVDと略称する)により形成された厚
さ200乃至400nm程度の多結晶シリコン層をパタ
ーニングすることにより、幅を3μms度とし、該配線
の切断予定位置において切断され、該切断部分の関FJ
Gが1乃至3μm程度に形成されている。この多結晶シ
リコンよりなる配[2の該間隙G部分はMo配線3によ
り接続されている。このMe配#!3は厚さ100乃至
300nmli度のMo層よりバターニングサレ、多結
晶シリコン配ls2とはその重なり部分においてオーミ
ック接触する〇
所要の配線パターン形成後、燐珪酸ガラス(ph−om
pho 51ticate gtass ; 以下PS
Gと略 □称する)、810mもしくは窒化シリコン(
SisN4)等よりなる絶縁1[i4に工り骸配線パタ
ーンを被覆するが、絶縁1i114の厚さは従来技術と
(ロ)様に1μm程度以下とする。FIG. 1 shows a sectional view of an embodiment of the present invention. In FIG. 1, 1 is the underlying silicon dioxide (SiOl) layer, and the layer 2, which can be selectively cut, is formed by chemical vapor deposition (ehemica vapor deposition).
By patterning a polycrystalline silicon layer with a thickness of about 200 to 400 nm formed by ion + CVD (hereinafter abbreviated as CVD), the wiring is cut at the planned cutting position with a width of about 3 μm, and the connection between the cut portions is cut. F.J.
G is formed to have a thickness of about 1 to 3 μm. The gap G portion of the wiring [2 made of polycrystalline silicon] is connected by a Mo wiring 3. This Me distribution #! 3 is a 100 to 300 nm thick Mo layer with a buttering solder and makes ohmic contact with the polycrystalline silicon metal ls2 at the overlapping part. After forming the required wiring pattern, phosphosilicate glass (ph-om
pho 51ticate gtass; PS below
G (abbreviated as □), 810m or silicon nitride (
The insulation 1[i4 made of SisN4) or the like is coated with the patterned wiring pattern, but the thickness of the insulation 1i114 is about 1 μm or less as in the prior art (b).
配線の切断は該絶lij膜4を介して前記Mo配線3に
エネルギS+選択的に朋射することにエリ実施される。The wiring is cut by selectively transmitting energy S+ to the Mo wiring 3 through the insulation film 4.
即ち、エネルギ線としては絶縁膜4には殆んど吸収され
ず、Mo配線3に吸収されるレーザ光として例えばアル
ゴン(Ar )レーザ(波長λ=488.2nm、51
4.5nm)ffiいt′1YAGレーザ(波長λ=1
.06μm)の連続波又はバ]OmA程度のビームのビ
ーム径を、通常に前rMo配線3の長さ以下として使用
する。またフラッジ−ライトを集光したものも使用可能
であるがスポット径を前記ビーム径と同様に制御する。That is, the energy beam is hardly absorbed by the insulating film 4, and the laser beam absorbed by the Mo wiring 3 is, for example, an argon (Ar) laser (wavelength λ=488.2 nm, 51 nm).
4.5nm) ffit'1YAG laser (wavelength λ=1
.. A continuous wave of 0.06 μm or a beam diameter of about 0.06 μm is normally used, with the beam diameter being equal to or less than the length of the front rMo wiring 3. It is also possible to use a condensed flood light, but the spot diameter is controlled in the same way as the beam diameter.
本エネルギ線照射処理を実施する雰囲気は、絶縁膜4が
PSGもしくは5101等の酸化物であるときは通常の
9気であってもよいが、雰囲気が酸化性であるときには
少いパワーで目的を達成することかでき、絶縁膜4が8
1sN4等であって酸素を含まないときは通常酸化性雰
囲シ中で実施する。The atmosphere in which this energy beam irradiation process is carried out may be normal 9Q when the insulating film 4 is made of PSG or an oxide such as 5101, but when the atmosphere is oxidizing, the purpose can be achieved with less power. It can be achieved that the insulating film 4 is 8
When it is 1sN4 or the like and does not contain oxygen, it is usually carried out in an oxidizing atmosphere.
創配エネルギ#照射にエリ、MOを約500℃以上に加
熱するとき、MOは急激に酸化物M −Osとなって昇
華し、絶縁膜4を通過して雰囲気中に拡散する。この結
果第2図に示す如く多結晶シリコン配線2は前記間隙G
においてW気的接続が切断され、空洞部5を生ずる−
M 00gの昇華に工りMo配lll3はきれいに消滅
し、多結晶シリコンの溶断において経験された飛散物の
付着は全く現われない。When MO is heated to approximately 500° C. or higher for irradiation with generated energy, MO rapidly becomes an oxide M-Os, sublimates, passes through the insulating film 4, and diffuses into the atmosphere. As a result, as shown in FIG. 2, the polycrystalline silicon wiring 2 is
The W air connection is severed at , creating a cavity 5 -
As a result of the sublimation of M00g, the Mo alloy disappears completely, and the adhesion of scattered particles that was experienced in the melt cutting of polycrystalline silicon does not appear at all.
上述したMO配fIs3の加熱は、切断場所を選択した
後にプログラムし、例えばマイクロコンピュータによっ
て制御されるXY方向走行テーブルを用いることに工っ
ですべて自動的に行うことができる。かかる自動操作に
おいて、Moの酸化、昇華が短時間にきれいに行われる
ことll″it!わめて有効である。The above-mentioned heating of the MO arrangement fIs3 can be programmed after selecting the cutting location and can be carried out entirely automatically, for example by using an XY-direction traveling table controlled by a microcomputer. In such an automatic operation, it is extremely effective that the oxidation and sublimation of Mo be carried out in a short time and cleanly.
前記実施例においては多結晶シリコン配線2の間隙Gを
Mo配線3にLって接続したが、MOに代えてタングス
テン(W)を用いて骸間隙Gを接続しても前記実施例と
同様に酸化物WOIの昇華に工り回路の切断がなされる
。In the embodiment described above, the gap G of the polycrystalline silicon wiring 2 was connected to the Mo interconnection 3 by L, but even if the skeleton gap G was connected using tungsten (W) instead of MO, the same effect as in the embodiment described above can be obtained. Cutting of the engineered circuit occurs upon sublimation of the oxide WOI.
更に前記実施例においては、配Is2を多結晶シリコン
によって形成したが、この配線2は多結晶シII コン
以外の導体であっても工く、前記Mo%しくはWに工つ
て配線2を前記の如き関11Gを特に設けることなく形
成し、切断位置のみに選択的にエネルギ線照射を行って
も同等の効果を得ることが可能である。Further, in the above embodiment, the wiring Is2 is formed of polycrystalline silicon, but the wiring 2 may be formed of a conductor other than polycrystalline silicon. It is possible to obtain the same effect even if the barrier 11G is formed without being particularly provided and the energy beam is selectively irradiated only at the cutting position.
又、間隙Gを接続する材料としては、前記M。Moreover, as a material for connecting the gap G, the above-mentioned M is used.
もしくはWのみならずその酸化物その他の化合物が10
00℃程度以下の温度において昇華するもので4りでも
よく、チタン(Ti)、バナジウム(V)、クロム(C
r)、鉄(Fe)、コバルト(Co)、ニッケル(Ni
)、ジルコニウム(2rLニオブ(Nb)、ルテニウム
(Ru)、ロジウム(Rh)、パラジウム(Pd )、
ハフニラA(Hf )、メンタル(Ta )、オスミラ
A (01)。Or not only W but also its oxides and other compounds are 10
It sublimates at a temperature of about 00°C or less and may be 4-carbon, such as titanium (Ti), vanadium (V), or chromium (C).
r), iron (Fe), cobalt (Co), nickel (Ni
), zirconium (2rL niobium (Nb), ruthenium (Ru), rhodium (Rh), palladium (Pd),
Hafnira A (Hf), Mental (Ta), Osmira A (01).
イリジウム(I r )、白金(Pt)又はその合金が
あげられる。Examples include iridium (I r ), platinum (Pt), or alloys thereof.
(6)発明の効果
本発明は配線パターンの一部を選択的に切断する半導体
装置の製造方法において、切断する可能性のある配線の
少くとも一部をM o + Wその他前記の金属又は該
金属の合金にエリ形成し、骸配線を被覆する絶縁膜を介
して、該金属又は合金部0:の少くとも一部をエネルギ
線の照射により化合物として昇華せしめて該配線を切断
する製造方法を提供するものであって、該半導体装置を
槽底する他の素子に大電流を通ずる必要はなく、又、配
・線切断のみのためのパッド等を設ける必要もなく、絶
縁膜によって保護された状襲で短時間にかつきれいに・
配線の切断処理を行うことが可能であって、しかも本発
明の切断処理はコンピュータに制御される自動処理によ
くなじむものであって、該半導体装置の歩留りの改善及
び信頼度の向上に大きい効果を有する。(6) Effects of the Invention The present invention provides a method for manufacturing a semiconductor device in which a part of a wiring pattern is selectively cut. A manufacturing method in which an edge is formed on a metal alloy, and at least a part of the metal or alloy part 0: is sublimated as a compound by irradiation with an energy beam through an insulating film covering the skeleton wiring, and the wiring is cut. There is no need to pass a large current to other elements on the bottom of the semiconductor device, there is no need to provide pads for wiring and cutting, and the semiconductor device is protected by an insulating film. Quickly and cleanly
It is possible to perform wiring cutting processing, and the cutting processing of the present invention is well suited to automatic processing controlled by a computer, and is highly effective in improving the yield and reliability of the semiconductor device. has.
第1図及び第2図は本発明の実施例を示す断面図である
。
図において、1は5iot層、2は多結晶シリコンより
なる配線、3はMo配線、4は絶縁膜、5は空洞部を示
す。FIGS. 1 and 2 are cross-sectional views showing embodiments of the present invention. In the figure, 1 is a 5-iot layer, 2 is a wiring made of polycrystalline silicon, 3 is a Mo wiring, 4 is an insulating film, and 5 is a cavity.
Claims (1)
半導体装置の製造方法において、該配線の少くとも一部
をモリブテン(Mo)、タングステン(W)、チタン(
Ti )、バナジウム(V)。 りo A (Cr ) +鉄(Fe )、コバルト(C
o)。 ニッケル(Ni)、ジルコニウム(Zr )、ニオブ(
Nb)、ルテニウム(Ru)+ ロジウム(Rh)。 パラジウム(Pd)、ハフニウム(Hf)、メンタル(
Ta )、オスミウム(Os )、イリジウム(Ir)
、白金(pt)のうちから選ばれた少なくとも一種の金
属又は該金属の合金にエリ形成し、該配線を被覆する絶
縁膜を形成した後に、1絶縁IgIIを介してエネルギ
線を照射することにエリ、計金属又は該合金の少くとも
一部を選択的に加熱して化合物として昇華せしめて該配
線を切断することを特徴とする半導体装置の製造方法。[Scope of Claims] In a method of manufacturing a semiconductor device, in which a part of the wiring is selectively cut after forming a wiring pattern, at least a part of the wiring is made of molybdenum (Mo), tungsten (W), titanium (
Ti), vanadium (V). Rio A (Cr) + iron (Fe), cobalt (C
o). Nickel (Ni), zirconium (Zr), niobium (
Nb), ruthenium (Ru) + rhodium (Rh). Palladium (Pd), Hafnium (Hf), Mental (
Ta), osmium (Os), iridium (Ir)
, forming an edge on at least one metal selected from platinum (PT) or an alloy of the metal, forming an insulating film covering the wiring, and then irradiating an energy beam through one insulating IgII. 1. A method for manufacturing a semiconductor device, which comprises selectively heating at least a portion of the metal or the alloy to sublimate it as a compound and cutting the wiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56190353A JPS5892252A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56190353A JPS5892252A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5892252A true JPS5892252A (en) | 1983-06-01 |
JPS611903B2 JPS611903B2 (en) | 1986-01-21 |
Family
ID=16256774
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56190353A Granted JPS5892252A (en) | 1981-11-27 | 1981-11-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5892252A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5918658A (en) * | 1982-07-22 | 1984-01-31 | Nec Corp | Semiconductor integrated circuit device |
JPS6231156A (en) * | 1985-08-02 | 1987-02-10 | Nec Corp | Semiconductor device and manufacture thereof |
JPS62119938A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Semiconductor device provided with redundancy circuit |
JPH0249450A (en) * | 1988-03-18 | 1990-02-19 | Digital Equip Corp <Dec> | Integrated circuit having metallized layer reformable by laser |
EP0405849A2 (en) * | 1989-06-30 | 1991-01-02 | AT&T Corp. | Severable conductive path in an integrated-circuit device |
US6163062A (en) * | 1997-10-27 | 2000-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a metallic fuse member and cutting method thereof with laser light |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06310917A (en) * | 1993-04-22 | 1994-11-04 | Mitsubishi Electric Corp | Microstrip line device |
-
1981
- 1981-11-27 JP JP56190353A patent/JPS5892252A/en active Granted
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5918658A (en) * | 1982-07-22 | 1984-01-31 | Nec Corp | Semiconductor integrated circuit device |
JPS6231156A (en) * | 1985-08-02 | 1987-02-10 | Nec Corp | Semiconductor device and manufacture thereof |
JPS62119938A (en) * | 1985-11-20 | 1987-06-01 | Mitsubishi Electric Corp | Semiconductor device provided with redundancy circuit |
JPH0249450A (en) * | 1988-03-18 | 1990-02-19 | Digital Equip Corp <Dec> | Integrated circuit having metallized layer reformable by laser |
EP0405849A2 (en) * | 1989-06-30 | 1991-01-02 | AT&T Corp. | Severable conductive path in an integrated-circuit device |
EP0405849A3 (en) * | 1989-06-30 | 1991-05-02 | American Telephone And Telegraph Company | Severable conductive path in an integrated-circuit device |
US6163062A (en) * | 1997-10-27 | 2000-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a metallic fuse member and cutting method thereof with laser light |
Also Published As
Publication number | Publication date |
---|---|
JPS611903B2 (en) | 1986-01-21 |
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