JP3489088B2 - Semiconductor device having redundant means and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having redundant means and a method of manufacturing the same, and particularly, to prevent cracks from occurring in an insulating layer in the vicinity of a connection portion or a disconnection portion with a redundant circuit portion. The present invention relates to a semiconductor device having redundant means whose reliability is improved by preventing the same and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been improved in integration degree in semiconductor integrated circuit devices such as VLSIs and provided with redundant means so that a good product can be obtained even if a part of a circuit element is defective. It has improved the yield of integrated circuit devices.

For example, a redundant means in a cache RAM (random access memory) used in a microprocessor has a redundant bit cell provided in a part of a memory circuit, and when a defective bit cell occurs, The defective bit cell is switched to a non-defective redundant bit cell by fusing the previously formed Al fuse wiring layer with laser light or the like.

[0004] Figure 1 1 reference redundant means comprising the Al fuse interconnect layer, for example,
In the case of the four-layer wiring structure, as shown in FIG. 11, the first wiring layer to the third wiring layer are separated from each other on the silicon substrate 21 through the base insulating layer 22. The first interlayer insulating layer 65, the second interlayer insulating layer 66, and the third interlayer insulating layer 67 are provided, and the Al layer is deposited on the third interlayer insulating layer 67 and then patterned to form the fourth layer wiring. The structure is such that the Al fuse wiring layer 68 is formed together with the layer and is covered with the cover film 31, and the Al fuse wiring layer 68 is melted by irradiating the necessary portions with laser light.

In this case, when the Al fuse wiring layer 68 is irradiated with laser light, a part of the Al fuse wiring layer 68 is melted and vaporized. However, since the Al fuse wiring layer 68 is covered with the cover film 31, the pressure increases and the cover film is covered. 31 blows off and leads to cutting.
If the cover film 31 does not exist, the Al fuse wiring layer 68 simply melts and does not cut.

[0006]

However, since the phenomenon of blowing a part of the Al fuse wiring layer 68 together with the cover film 31 is used for cutting the redundant means, an insulating layer near the cut portion, for example, the cover film 31 is used. And the third interlayer insulating layer 67
There is a problem that a crack is generated in the inner part, and as a result, there is a problem that the reliability of the peripheral uncut Al fuse wiring layer 68 is deteriorated.

At the cut portion of the Al fuse wiring layer 68, a hole is formed in the cover film 31, moisture enters from that portion, and corrosion progresses from the cut portion of the Al fuse wiring layer 68. There is a problem that a crack is generated in the peripheral cover film 31 and the third interlayer insulating layer 38, and the reliability of the uncut peripheral Al fuse wiring layer 68 is deteriorated.

Further, Al that constitutes the Al fuse wiring layer 68 has a low absorptance with respect to infrared light from the YAG laser used for laser processing, and it is necessary to increase the laser energy in order to perform reliable cutting. However, when the laser energy is set high, there is a drawback that damages the vicinity of the cut portion and also causes cracks.

Further, it has good corrosion resistance to moisture,
In addition, if a redundant means is to be formed by using a wiring layer having a high absorption rate for infrared light from the YAG laser, a wiring layer different from the normally used Al-based wiring layer is required, and the manufacturing process is There is a problem that the cost increases due to the increase.

Therefore, according to the present invention, in the same industrial application field of the redundancy mechanism of the semiconductor device, the disconnectability of the redundant means is improved without increasing the manufacturing process, or the connection is not the disconnect type. The purpose is to solve the same problem of preventing the occurrence of cracks in the insulating layer by using the type redundancy means.

[0011]

FIG. 1 is an explanatory view of the principle structure of the present invention, and means for solving the problems will be described with reference to FIG. FIG. 1 is an explanatory view of a truncated form of the redundancy means, In Fig 1, reference numeral 1 and 12, respectively the substrate, a base insulating layer, and represent a cutting unit.

FIG. 1 (a) (1) The present invention is a semiconductor device having redundant means, in which a contact embedded in a hole 5 connecting upper and lower wiring layers 3 and 9 provided via an interlayer insulating layer 4 is provided. It is characterized by having a fuse wiring layer 7 formed of the same conductor as the conductor 6 and formed in an insulating layer including at least the same interlayer insulating layer 4 in which the holes 5 are formed.

(2) Further, the present invention is characterized in that in the above (1), the contact conductor 6 is thicker than the fuse wiring layer 7.

(3) Further, the present invention is characterized in that, in the above (1) or (2), a width of a part of the fuse wiring layer 7 has a narrower width detail than the other part.

(4) Further, in the present invention according to any one of the above (1) to (3), the thickness of the insulating film 10 is more than that of the surrounding insulating film 10 on at least a part of the fuse wiring layer. It is also characterized in that a concave portion which is thin is provided.

(5) Further, the present invention is characterized in that in any one of the above (1) to (3), at least a part of the upper surface of the fuse wiring layer is exposed.

(6) Further, according to the present invention, in the method of manufacturing a semiconductor device having the redundant means, the hole 5 and the groove 8 for the fuse wiring layer 7 are formed in the interlayer insulating layer 4 for separating the upper and lower wiring layers 3, 9. Step of forming, step of simultaneously filling hole 5 and groove 8 for fuse wiring layer 7 with a conductor, insulating film 1 on the conductor
It is characterized by including a step of setting 0.

(7) Further, in the present invention, in the above-mentioned (6), the step of simultaneously filling the hole 5 and the groove 8 for the fuse wiring layer 7 with a conductor is to etch back after depositing the conductor on the entire surface. Alternatively, it is characterized by comprising a step of removing the conductor other than inside the hole 5 and the groove 8 for the fuse wiring layer 7 by a chemical mechanical polishing method.

(8) Further, the present invention is characterized in that, in the above (6) or (7), the groove 8 for the fuse wiring layer 7 is formed in the same step as the hole 5.

(9) Further, according to the present invention, in the above (6) or (7), a recess or an opening is provided in the insulating film 10 on the fuse wiring layer 7 simultaneously with the step of providing a contact hole in the insulating film 10. It is characterized by that.

[0021]

[0022]

[0023]

[0024]

(1 0 ) Further, the present invention has a redundant means.
In the method for manufacturing a semiconductor device according to the above, a step of providing two grooves separated by an isolation barrier provided in a portion corresponding to the slit 14 in the interlayer insulating layer 4 for separating the upper and lower wiring layers, and a step of filling the groove with a conductor. A redundant wiring layer 13 consisting of
The process of dividing by the slit 14 and the separated redundancy
By electrically connecting the wiring layer 13 for
A switch to a redundant bit .

(1 1 ) The present invention also provides the above (1 0 )
In the above, the step of forming the groove is the same as the step of forming a hole in the interlayer insulating layer 4 for connecting the upper and lower wiring layers,
Further, the step of filling the groove with the conductor is the same as the step of filling the hole with the contact conductor.

(1 2 ) The present invention also provides the above (1 0 )
Alternatively, (1 1 ) is characterized in that the redundant wiring layer 13 is electrically connected by the melted connection portion 15 obtained by melting a part of the redundant wiring layer near the slit.

(1 3 ) Further, the present invention provides the above (1 0 )
Alternatively, (1 1 ) is characterized in that the redundant wiring layer 13 is electrically connected by locally growing a conductor in the vicinity of the slit 14.

[0029]

The fuse wiring layer 7 is made of the same conductor as the contact conductor 6 embedded in the hole 5 for connecting the upper and lower wiring layers 3 and 9 provided via the interlayer insulating layer 4, and this interlayer insulating layer is formed. Since the fuse wiring layer 7 can be formed in the same step as that of the contact conductor by forming it in the insulating layer containing 4, it is possible to increase the number of manufacturing steps without increasing the number of manufacturing steps. Since a conductor having a higher light absorptivity for laser light than the body can be used, the laser energy of the laser light irradiated for fusing can be reduced, whereby cracks in the insulating layer can be suppressed. it can.

For example, FIG. 2 shows a W fuse having a width of 0.6 μm with a cover film and a thickness of 1.0 μm, and a width of 0.6 μ with a cover film.
Laser irradiation energy dependence of cutting yield when infrared laser light is irradiated to an Al fuse with a thickness of 0.7 μm and a thickness of 0.7 μm and a W fuse with a width of 0.6 μm and a thickness of 1.0 μm It is understood that the cutting yield of the W fuse shown by the solid line is higher than the cutting yield of the Al fuse shown by the broken line at the same laser energy.

Further, the W fuse shown in FIG. 2 has a larger film thickness than the Al fuse, and it is generally difficult to cut the fuse having a large film thickness. Cutting becomes easier.

Further, by making the thickness of the fuse wiring layer 7 smaller than that of the contact conductor 6, it becomes easier to cut the fuse wiring layer 7, so that the irradiation laser energy is reduced and the insulating layer is cracked. Can be suppressed.

Further, by providing a part of the fuse wiring layer 7 with a width smaller than that of the other parts of the fuse wiring layer 7, it becomes easier to cut the fuse wiring layer 7.
The irradiation laser energy can be reduced to effectively suppress the occurrence of cracks in the insulating layer.

Further, the insulating film 1 is thinned by providing a concave portion in which the thickness of the insulating film 10 is thinner than the thickness of the surrounding insulating film 10 in at least a part of the fuse wiring layer 7.
Since the laser beam 11 is emitted via 0, the laser energy can be reduced, and thereby the generation of cracks in the insulating layer can be suppressed.

By exposing at least a part of the upper surface of the fuse wiring layer 7, the fuse wiring layer 7 is exposed.
When W is composed of W, cutting can be performed with lower energy, and since it is not necessary to blow off the insulating film 10, it is possible to suppress the occurrence of cracks in the insulating layer.

See FIG. 2. W differs from Al in that it has a high light absorptivity to infrared light and is easily vaporized, so that it can be cut without a cover film as shown by the one-dot chain line, and the W fuse shown by the solid line. From the comparison with the cutting yield of No. 3, in the case of the W fuse, it is possible to cut at low energy without the cover film.

Further, by simultaneously filling the hole 5 and the groove 8 for the fuse wiring layer 7 with the same conductor in the interlayer insulating layer 4 for separating the upper and lower wiring layers 3 and 9, it is possible to prevent an increase in manufacturing steps. .

Further, the hole 5 and the groove 8 for the fuse wiring layer 7 are formed.
Etch back,
Alternatively, a chemical mechanical polishing method (Chemical Mechanical
By using an organic polishing (CMP), a wiring layer excellent in flatness can be formed, and a conductor not suitable for RIE (reactive ion etching) can be used.

Further, by forming the groove 8 for the fuse wiring layer 7 in the same process as the hole 5, it is possible to prevent an increase in the number of manufacturing processes.

By forming a recess or an opening in the insulating film 10 on the fuse wiring layer 7 simultaneously with the step of forming the contact hole in the insulating film 10, the fuse wiring exposed through the thinned insulating film 10 or exposed. Since the layer 7 is directly irradiated with the laser beam 11, the laser energy can be reduced, and thus the generation of cracks in the insulating layer can be suppressed.

[0041]

[0042]

[0043]

[0044]

In addition, the separated redundant wiring layer 13 is electrically charged.
Make bad bits into redundant bits by connecting them
By using the switching method, a disconnect type redundant hand
You can reduce the damage to the insulating layer compared to the step
Therefore, it is possible to prevent the occurrence of cracks. Particularly, by forming the redundant wiring layer 13 in the step of filling the groove with a conductor, a material having a higher light absorptivity than the Al-based conductor as the conductor is formed. Can be used and the surface can be planarized.

Further, at the same time as the step of forming a hole in the interlayer insulating layer 4 for connecting the upper and lower wiring layers, the groove for the redundant wiring layer 13 is formed, and at the same time as the step of filling the hole with the contact conductor, the groove is formed. By embedding with a conductor, the redundant wiring layer 13 can be formed using a material having a higher light absorption rate than the Al-based conductor without increasing the manufacturing process.

The electrical connection of the redundant wiring layer 13 is
By performing a part of the redundant wiring layer 13 in the vicinity of the slit 14 with the melted connection part 15 which is melted, the redundancy can be performed with lower energy than the cutting of the redundant wiring layer by vaporization, and on the melted connection part 15. Since there is no insulating layer, it is possible to suppress the occurrence of cracks in the insulating layer.

The electrical connection of the redundant wiring layer 13 is
By locally growing the conductor in the vicinity of the slit 14, thermal damage can be reduced, and cracking of the insulating layer can be suppressed.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. FIGS. 3 (a) see First, on a silicon substrate 21, then provided with an Al wiring layer 23 having a thickness of 1μm over the base insulating layer 22 such as SiO ₂ film, a SiO ₂ film and SOG (spin on glass ) An interlayer insulating layer 24 having a total thickness of 1 μm is formed of a composite film of films.

In this case, since the fluidity of the SOG film is extremely high, the SOG film on the Al wiring layer 23 flows out between the Al wiring layers 23 and fills the entire step portion having a height of 1 μm by the Al wiring layer 23. Between the wiring layers 23, the thickness of the interlayer insulating layer 24 becomes 1 μm or more, and this tendency is Al
The higher the degree of integration, the closer the space between the wiring layers 23 becomes, and the more remarkable it becomes.

Next, as shown in FIG. 3B, the RIE method is used to form the via hole 25 for connecting the Al wiring layer 23 to the upper wiring layer and simultaneously form the groove 26 for the fuse wiring layer. In this case, the width of the groove 26 for the fuse wiring layer is 0.5 μm, and the depth thereof is 1.3 μm together with the overetching for securing the etching margin of the via hole 25.

Next, as shown in FIG. 3C, a thin TiN film (not shown) is deposited by a sputtering method in order to improve the adhesion to the interlayer insulating layer 24, and then the CVD method (chemical vapor deposition method) is used. Using W
Is deposited on the entire surface, and the entire surface is polished by using a chemical mechanical polishing method (CMP method) to remove W except in the via hole 25 and the groove 26 for the fuse wiring layer, thereby forming the W contact conductor 2
7 and W fuse wiring layer 28 is formed.

The CMP method is a polishing method in which a slurry containing fine particles such as Al ₂ O ₃ powder is used for chemical polishing, and is applicable to a conductor without an appropriate etching gas. This is a method useful for forming fine wiring with a conductor such as Cu that is not suitable for the RIE method.

Next, referring to FIG. 4 (d), an Al film having a thickness of 1 μm is deposited on the entire surface and then patterned to be connected to the upper wiring layer 29 connected to the W contact conductor 27 and the W fuse wiring layer 28. The upper wiring layer 30 is formed, and then a 0.5 μm SiN film and a 0.5 μm SiO ₂ film are sequentially deposited to form a cover film 31.

In the patterning process of the upper wiring layer 30, the surface of the W fuse wiring layer 28 is also ground by 0.2 to 0.3 μm by the over-etching for ensuring the etching margin, and is embedded in the groove. W
The thickness of the fuse wiring layer 28 is 1.0 to 1.1 μm.

Next, when a defective bit is found as a result of the electrical test of the internal circuit element, a predetermined broken line of the W fuse wiring layer 28 is used to switch the redundant bit to a good one. The laser beam 32 of 0.5 to 1.0 μJ, preferably 0.7 μJ, is applied to the cutting portion 33 shown through the cover film 31 for 10 to 30 ns (nanosecond), preferably 20 ns.

In the irradiation portion of the reference laser beam 32 shown in FIG. 4 (f), W is melted and vaporized,
The cutting portion 33 is blown off together with the cover film 31.
Is formed, and the defective bit is switched.

In the first embodiment, the fuse wiring layer has a higher W absorption rate for infrared light than the Al wiring layer.
Since the laser energy of the laser light 32 to be applied can be made smaller than that in the conventional case, the damage given to the cover film 31 and the interlayer insulating layer 24 can be reduced, and thus the occurrence of cracks can be prevented. Can be suppressed.

Further, since W has a better corrosion resistance to moisture than the Al-based wiring layer, there is a hole in a part of the cover film 31 near the cut W-fuse wiring layer 28 so that moisture enters. However, the corrosion does not progress and the reliability of the W fuse wiring layer 28 does not decrease.

Next, a second embodiment of the present invention will be described with reference to FIG. 5A, first, as in the first embodiment, an Al wiring layer 23 having a thickness of 1 μm is formed on a silicon substrate 21 with an underlying insulating layer 22 interposed therebetween, and then a SiN film having a thickness of 0.1 μm is formed. Etching stopper film 34 made of a film and an interlayer insulating layer 2 made of a composite film of a SiO ₂ film and an SOG film and having a total thickness of 0.9 μm.
4 is formed.

Then, using a parallel plate RIE device having an internal volume of 8000 cm ³ , conditions under which a selective ratio of SiN and SiO ₂ can be obtained, that is, C ₄ F ₈ as an etching gas is set to 50
0.1 Tor by flowing 200 sccm of sccm and CO
In the state of r, by applying electric power of 400 W, only the interlayer insulating layer 24 in the portion located in the via hole 25 and the groove 26 for the fuse wiring layer is selectively etched.

Next, referring to FIG. 5B, the etching stopper film 34 made of SiN exposed by RIE etching under normal conditions is removed to form a via hole 25 and a groove 26 for a fuse wiring layer.

Next, as shown in FIG. 5C, as in the first embodiment, by embedding W using the CMP method, the W contact conductors 27 and W are formed.
After forming the fuse wiring layer 28, upper wiring layers 29 and 30 made of Al or the like are formed.

Next, after forming a cover film (not shown), laser light is irradiated to the W fuse wiring layer 28 at the location where the defective bit needs to be switched to irradiate the W fuse wiring layer 28.
Disconnect.

Since the etching stopper film 34 is used in the second embodiment, the W fuse wiring layer 28 is used.
Since the depth of the groove for forming the groove can be accurately formed, that is, the total thickness of the interlayer insulating layer 24 and the etching stopper film 34 can be set, it is easy to set the laser light irradiation conditions. become.

The etching stopper film 34 is
The etching stopper film 34 is not limited to the SiN film and may be a SiON film or a film having a selective etching property with respect to the SiO ₂ film such as an Al ₂ O ₃ film. SOG comprising layer 24
It also functions as a moisture resistance improving film when the film is formed.

Next, a third embodiment of the present invention will be described with reference to FIG. 6A, first, as in the first embodiment, an Al wiring layer 23 having a thickness of 1 μm is formed on the silicon substrate 21 with the underlying insulating layer 22 interposed therebetween, and then the SiO ₂ film and the SOG film are formed. An interlayer insulating layer 24 made of a composite film and having a total thickness of 1.0 μm is formed, and then a via hole 25 is formed.

Next, referring to FIG. 6B, a groove 26 for the fuse wiring layer having a width of 0.5 μm and a depth of 0.5 μm is formed by etching using a new photoresist mask.

Next, as shown in FIG. 6C, as in the first embodiment, by embedding W using the CMP method, the W contact conductors 27 and W are formed.
After forming the fuse wiring layer 28, upper wiring layers 29 and 30 made of Al or the like are formed.

Next, after forming a cover film (not shown), laser light is irradiated to the W fuse wiring layer 28 at the location where the defective bit needs to be switched, and the W fuse wiring layer 28 is then irradiated.
Disconnect.

In the third embodiment, since the step of forming the via hole 25 and the step of forming the groove 26 for the W fuse wiring layer 28 are separate steps, the depth of the groove 26 can be set to an arbitrary depth. Therefore, the range of laser irradiation conditions can be widened. The groove 2 for the W fuse wiring layer 28
The step of forming 6 may be performed before the step of forming the via hole 25.

Next, a fourth embodiment of the present invention, which is a modification of the first embodiment, will be described with reference to FIG. 7 (a). First, after forming the laminated structure shown in FIG. 4 (d), when the bonding window 35 for the bonding pad 37 connected to the upper wiring layer 29 is formed, it is positioned on the W fuse wiring layer 28. A part of the W fuse wiring layer 28 is exposed by the opening 36 formed by etching a part of the cover film 31.

Next, referring to FIG. 7B, the exposed W fuse wiring layer 28 is irradiated with laser light 32 to melt, vaporize, and cut the W fuse wiring layer 28.

Incidentally, the W fuse wiring layer 28 is made of conventional Al.
The absorption rate of infrared laser light is higher than that of the fuse wiring layer, and W
Even if there is no cover film 31 on the fuse wiring layer 28, it can be easily vaporized so that laser cutting can be performed, and if the cover film 31 is not provided, cutting can be performed with low energy.
The cover film 31 may remain thin on the W fuse wiring layer 28 in the opening 36.

In the fourth embodiment, only one insulating layer provided on the upper wiring layers 29 and 30 is shown as the cover film 31, but the fuse wiring layer is arranged in the lower wiring layer. When the wiring is provided, the upper wiring layer 29,
A multilayer cover film or interlayer insulating layer and a wiring layer are further provided on the layer 30, and the multilayer cover film or interlayer insulating layer is etched to form the opening 36. In this case also, the opening 36 is formed. The cover film 31 may remain thin on the W fuse wiring layer 28.

Next, a fifth embodiment of the present invention will be described with reference to FIG. Note that FIG. 8B is a cross-sectional view taken along the alternate long and short dash line AA ′ in the plan view of FIG. 8A.

8 (a) and 8 (b) First, similarly to the first embodiment, an Al wiring layer 23 having a thickness of 1 μm is formed on a silicon substrate 21 with a base insulating layer 22 interposed therebetween. An interlayer insulating layer 24 made of a composite film of a SiO ₂ film and an SOG film and having a total thickness of 1.0 μm is formed.

Next, an opening for the via hole 25 and a groove 2 for the W fuse wiring layer 28 in the photoresist mask.
The contact portion 39 of No. 6 has a width of 0.6 μm □, and the width of the width portion 38 at the center of the groove 26 for the W fuse wiring layer 28 is 0.4.
Etching is performed with a thickness of μm to form a via hole 25 and a W fuse wiring layer 28.

In this case, the contact portion 39 of the via hole 25 and the groove 26 for the W fuse wiring layer 28 is formed by the loading effect due to the difference in the pattern width to be etched.
Of the W fuse wiring layer 28 progresses faster than the etching of the central width 38 of the groove 26 for the W fuse wiring layer 28, so that the depth of the contact portion 39 becomes deeper than the depth of the central width 38.

For example, when etching is performed including the etching margin of the via hole 25, the W fuse wiring layer 2
The depth of the contact portion 39 and the depth of the width portion 38 at the center of the groove 26 for 8 can be 1.3 μm and 0.7 μm, respectively.

Also in this case, since the amount of W to be blown at the cut portion of the W fuse wiring layer 28 can be reduced, the laser energy can be reduced and the damage due to the laser light irradiation can be reduced. Generation of cracks can be suppressed.

In the first to fifth embodiments, W is used as the conductor for the fuse wiring layer, but the conductor is not limited to W and W silicide may be used. Since the conductor has a higher absorption rate of infrared rays than Al, it is possible to reduce the laser energy for irradiation, reduce damage caused by laser light irradiation, and suppress the generation of cracks.

When embedding the fuse wiring layer,
Although an etching back may be used instead of the CMP method, the CMP method is preferable because it can be applied to a conductor in which an appropriate etching gas does not exist.

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091]

Next, with reference to FIG. 9, illustrating a sixth embodiment of the present invention. 9 (a) and 9 (b) First, similarly to the fifth embodiment, a thin TiN film (not shown) is deposited as a contact metal on the silicon substrate 41 through the interlayer insulating layer 42 by the sputtering method. After that, a W film having a thickness of 0.5 μm is deposited and patterned to form a redundancy wiring layer 43 having a width of 1 μm separated by a slit 44 having a gap of 0.5 μm, and then a cover film 45 is formed. With a thickness of 0.5 μm indicated by the broken line
After the iN film is deposited, the vicinity of the slit 44 is selectively etched to form the sidewall 46 of the SiN film on the side wall of the slit portion, and the side surface of the end portion of the redundant wiring layer 43 is exposed.

[0093] refer to FIG. 9 (c) Next, using focused ion beam method (FIB) method, the vicinity locally grown by the left and right redundant wiring to form a connection conductive layer 49 and W layer of the slit 44 The layers 43 are electrically connected to switch between defective bits and non-defective redundant bits.

In the sixth embodiment, a part of the cover film 45 on the end of the redundant wiring layer 43 may be removed to expose the upper surface of the end of the redundant wiring layer 43. However, depending on the case, the sidewall 46 in the slit 44 may be removed, but at least one of the side surface and the upper surface of the end portion of the redundant wiring layer 43 may be exposed.

Since the laser beam is not used to connect the redundant wiring layer 43, the cover film 45 and the interlayer insulating layer 4 are not used.
The thermal damage to 2 is reduced, and the occurrence of cracks is suppressed.

Next, referring to FIG. 1 0, seventh invention
An example will be described. Figure 1 0 (a) see First, as in the first embodiment, after forming the Al wiring layer 51 having a thickness of 1μm over the base insulating layer 50 on the silicon substrate 41, a SiO ₂ film and SOG film A 1.0 μm thick interlayer insulating layer 52 made of a composite film of
At the time of forming the via hole 53, a groove 55 for forming a redundant wiring layer, which is separated by a separation barrier 54 having a thickness of 0.5 μm and corresponding to a slit, is simultaneously formed.

[0097] Figure 1 0 (b) refer then by CMP like the same first embodiment, by embedding W in the via holes 53 and the groove 55, W contact conductor 56 and the W redundant wiring layer 57 After forming the film, a conductive film such as Al is deposited on the entire surface and patterned to form an upper wiring layer 58 connected to the W contact conductor and an upper wiring layer 59 connected to the W redundancy wiring layer 57. . A bonding pad 60 is formed on a part of the upper wiring layer 58.

[0098] Figure 1 0 (c) see Then, after the entire surface by depositing a cover film 61 of SiN film or the like, the bonding window for the bonding pads 60 6
2 is formed, the cover film 61 near the separation barrier 54 corresponding to the slit is removed to form the opening 63,
A part of the W redundancy wiring layer 57 is exposed. in this case,
Although part of the isolation barrier 54 is also etched in the process of forming the opening 63, it is not always necessary to etch it.

Then, similarly to the sixth embodiment, the W layer is locally grown by using the FIB method to electrically connect the left and right redundant wiring layers 43, and the defective bit and the non-defective redundancy. Switch to bit.

In the seventh embodiment, since the W redundant wiring layer 57 is formed by using the step of forming the via hole 53 and the step of forming the W contact conductor 56, the number of manufacturing steps is increased. It is possible to form a redundant wiring layer using a conductor having high humidity resistance and a high absorptance of laser light.

In the seventh embodiment, only one insulating film provided on the upper wiring layers 58 and 59 is shown as the cover film 61. However, a redundant wiring layer is provided in a lower wiring layer. When providing 43, the upper wiring layer 5
A multilayer cover film or interlayer insulating layer on 8,59,
In addition, a wiring layer is provided, and when the multilayer cover film or the interlayer insulating layer is etched to form the bonding window or the contact hole, the insulating layer near the separation barrier 54 is removed to form the opening 63. Become.

[0102]

[0103]

[0104]

In the sixth and seventh embodiments, W is used as the redundancy wiring layer, but it is not limited to W, and W silicide or Al such as TiN is used.
A conductor having a higher absorption rate of infrared light may be used.

In the first and seventh embodiments, the groove 26 for filling the W fuse wiring layer 28 or the groove 55 for filling the W redundancy wiring layer 57 is formed in the interlayer insulating layer 24 or the interlayer insulating layer. Although it is formed inside 52, it may be provided so as to bite into the base insulating layer 22 or the base insulating layer 50.

Further, the numerical values relating to the thickness and width of the wiring layer or the thickness of the insulating layer in each of the above embodiments are merely examples, and are not limited to the numerical values described.
It should be appropriately set according to the degree of integration of the semiconductor device to be formed.

[0108]

According to the present invention, a conductor such as W having a higher absorption rate of laser light and a higher moisture resistance than Al is used as the fuse wiring layer for redundancy, or the connection type redundancy means is used. Therefore, it is possible to prevent the occurrence of cracks due to laser light irradiation when switching the defective bit to the redundant bit, and thereby improve the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a principle configuration of the present invention.

FIG. 2 is an explanatory view of the operation of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process up to the middle of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of the manufacturing process after the process of FIG. 3 of the first embodiment of the present invention.

FIG. 5 is an explanatory diagram of a manufacturing process according to the second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a manufacturing process according to the third embodiment of the present invention.

FIG. 7 is an explanatory diagram of a manufacturing process according to the fourth embodiment of the present invention.

FIG. 8 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 9 is an explanatory diagram of the manufacturing process of the sixth embodiment of the present invention.

FIG. 10 is an explanatory diagram of the manufacturing process of the seventh embodiment of the present invention.

FIG. 11 is an explanatory diagram of a conventional fuse wiring layer.

[Explanation of symbols]

1 Substrate 2 Base Insulating Layer 3 Wiring Layer 4 Interlayer Insulating Layer 5 Hole 6 Contact Conductor 7 Fuse Wiring Layer 8 Groove 9 Wiring Layer 10 Insulating Film 11 Laser Light 12 Cutting Section 21 Silicon Substrate 22 Base Insulating Layer 23 Al Wiring Layer 24 Interlayer Insulating layer 25 Via hole 26 Groove 27 W contact conductor 28 W fuse wiring layer 29 Upper layer wiring layer 30 Upper layer wiring layer 31 Cover film 32 Laser beam 33 Cutting part 34 Etching stopper film 35 Bonding window 36 Opening 37 Bonding pad 38 Width detail 39 Contact part 41 Silicon substrate 42 Interlayer insulating layer 43 Redundant wiring layer 44 Slit 45 Cover film 46 Sidewall 49 Connection conductive layer 50 Base insulating layer 51 Al wiring layer 52 Interlayer insulating layer 53 Via hole 54 Separation barrier 55 Groove 56 W contact conductor 57 W Redundant wiring layer 58 Upper wiring layer 59 Upper wiring layer 60 Bonding pad 61 Cover film 62 Bonding window 63 Opening 65 First interlayer insulating layer 66 Second interlayer insulating layer 67 Third interlayer insulating layer 68 Al fuse wiring layer

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27/04 H01L 21/768 G06F 17/50 H01L 21/3205 H01L 21/3213

Claims (13)

(57) [Claims] 1. A contact conductor formed of the same conductor as a contact conductor embedded in a hole connecting upper and lower wiring layers provided through an interlayer insulating layer, and formed in an insulating layer including at least the interlayer insulating layer. A semiconductor device having a redundant means characterized by having a fuse wiring layer. 2. The semiconductor device having redundant means according to claim 1, wherein the contact conductor is thicker than the fuse wiring layer. 3. A semiconductor having redundant means according to claim 1, wherein a width of a part of the fuse wiring layer has a width smaller than that of the other part of the fuse wiring layer. apparatus. 4. The recessed portion in which the thickness of the insulating film is thinner than the thickness of the surrounding insulating film is provided in at least a part of the fuse wiring layer. 2. A semiconductor device having the redundant means according to item 1. 5. The at least part of the upper surface of the fuse wiring layer is exposed.
A semiconductor device having the redundant means according to any one of 1. 6. A step of forming a hole for connecting the upper and lower wiring layers and a groove for the fuse wiring layer in an interlayer insulating layer for separating the upper and lower wiring layers, and a conductor for forming the hole and the groove for the fuse wiring layer. A method of manufacturing a semiconductor device having redundant means, comprising: a step of burying at the same time; and a step of providing an insulating film on the conductor. 7. The step of simultaneously filling the hole and the groove for the fuse wiring layer with a conductor, after the conductor is deposited on the entire surface, is etched back or chemically mechanically polished into the hole and the hole. 7. The method of manufacturing a semiconductor device having redundant means according to claim 6, comprising the step of removing the conductor other than in the groove for the fuse wiring layer. 8. The method for manufacturing a semiconductor device having redundant means according to claim 6, wherein the groove for the fuse wiring layer is formed in the same step as the step of forming the hole. 9. A recess or an opening is provided in the insulating film on the fuse wiring layer at the same time when the contact hole is provided in the insulating film. A method of manufacturing a semiconductor device having the described redundant means. 10. An interlayer insulating layer for separating upper and lower wiring layers
Separated by a separation barrier provided at the portion corresponding to the slit.
The step of providing the two grooves formed and filling the grooves with a conductor
The redundant wiring layer consisting of the process and the process is divided by slits.
The process and the separated redundant wiring layer can be electrically connected.
And the process of switching the defective bit to the redundant bit by
Semiconductor device having redundant means characterized by having
Manufacturing method. 11. The step of forming the groove comprises the steps of
A step of forming a hole in the interlayer insulating layer to connect the wiring layers;
At the same time, the step of filling the groove with a conductor is
Simultaneously with the step of filling the hole with a contact conductor
11. Semi-comprising redundant means according to claim 10, characterized in that
A method for manufacturing a conductor device. 12. The electrical connection of the redundant wiring layer
A part of the redundant wiring layer near the slit was melted.
11. The method according to claim 10, wherein the fusion connection is performed.
Or 11, a method of manufacturing a semiconductor device having a redundancy means.
Law. 13. The electrical connection of the redundant wiring layer
By locally growing the conductor near the slit,
The method according to claim 10 or 11, characterized in that
A method of manufacturing a semiconductor device having redundant means.